IDT7223611L20PQF [IDT]
CMOS SyncFIFO 64 x 36; CMOS SyncFIFO 64× 36
| 型号： | IDT7223611L20PQF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncFIFO 64 x 36 |
| 文件： | 总20页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT723611
CMOS SyncFIFO
64 x 36
Integrated Device Technology, Inc.
• Fast access times of 10ns
FEATURES:
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power advanced CMOS technology
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military elecrical specifications
• 64 x 36 storage capacity
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full (AF) and Almost-Empty (AE)
flags
• Microprocessor Interface Control Logic
• Full Flag (FF) and Almost-Full (AF) flags synchronized by
CLKA
• Empty Flag (EF) and Almost-Empty (AE) flags synchro-
nized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Supports clock frequencies up to 67MHz
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports
clock frequencies up to 67MHz and has read access times as
fastas10ns.The64x36dual-portFIFObuffersdatafromPort
A to Port B. The FIFO has flags to indicate empty and full
conditions,andtwoprogrammableflags,Almost-Full(AF)and
Almost-Empty (AE), to indicate when a selected number of
words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
MBF1
PEFB
Parity
Gen/Check
Mail 1
Register
PGB
RST
Reset
Logic
ODD/
EVEN
64 x 36
SRAM
36
36
A0 - A35
Read
Pointer
Write
Pointer
B0 - B35
Status Flag
FF
AF
EF
AE
Logic
FIFO
Programmable
Flag Offset
Registers
FS0
FS1
PGA
Mail 2
Register
Parity
Gen/Check
CLKB
CSB
Port-B
Control
Logic
PEFA
MBF2
W/RB
ENB
MBB
3024 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 1997
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1997 Integrated Device Technology, Inc.
DSC-3024/4
1
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
chronous or coincident. The enables for each port are ar-
ranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Full-Flag (FF) and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to the port clock that writes data into
itsarray(CLKA). TheEmptyFlag(EF)andAlmost-Empty(AE)
flag of the FIFO are two-stage synchronized to the port clock
that reads data from its array.
DESCRIPTION (CONTINUED)
mailbox register has a flag to signal when new mail has been
stored. Parity is checked passively on each port and may be
ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices may be used
in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, mean-
ing each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asyn-
The IDT723611 is characterized for operation from 0°C to
70°C.
PIN CONFIGURATION
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
1
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B8
A8
B7
A7
VCC
B6
VCC
A6
B5
A5
B4
A4
B3
A3
GND
B2
GND
A2
B1
A1
A0
NC
NC
B0
EF
AE
NC
3024 drw 02
TQFP (PN120-1, order code: PF)
TOP VIEW
Note:
1. NC = No internal connection
2
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION (CONTINUED)
GND
NC
NC
A0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
*
EF
B0
A1
B1
A2
B2
GND
A3
GND
B3
A4
B4
A5
B5
A6
B6
VCC
A7
VCC
B7
A8
A9
B8
B9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3024 drw 03
PQFP (PQ132-1, order code: PQF)
TOP VIEW
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
3
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
Description
Port-A Data
I/O 36-bit bidirectional data port for side A.
Almost-Empty Flag
O
O
Programmable almost-empty flag synchronized to CLKB. It is LOW when
the number of words in the FIFO is less than or equal to the value in the offset
register, X.
AF
Almost-Full Flag.
Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in the FIFO is less than or equal to the value in the
offset register, X.
B0-B35
CLKA
Port-B Data.
Port-A Clock
I/O 36-bit bidirectional data port for side B.
I
CLKA is a continuous clock that synchronizes all data transfers through port-A
and can be aynchronous or coincident to CLKB. FF and AF are synchronized
to the LOW-to-HIGH transition of CLKA.
CLKB
CSA
CSB
EF
Port-B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port-B
and can be asynchronous or coincident to CLKA. EF and AE are synchronized
to the LOW-to-HIGH transition of CLKB.
Port-A Chip Select
Port-B Chip Select
Empty Flag
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when CSA is HIGH.
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when CSB is HIGH.
O
EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW,
the FIFO is empty, and reads from its memory are disabled. Data can be read
from the FIFO to its output register when EF is HIGH. EF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKB after data is loaded into empty FIFO memory.
ENA
ENB
FF
Port-A Enable
Port-B Enable
Full Flag
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
O
FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW,
the FIFO is full, and writes to its memory are disabled. FF is forced LOW when
the device is reset and is set HIGH by the second LOW-to-HIGH transition of
CLKA after reset.
FS1, FS0 Flag-Offset Selects
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1,
which loads one of four preset values into the almost-full and almost-empty
offset register (X).
MBA
MBB
Port-A Mailbox Select
Port-B Mailbox Select
I
I
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation.
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects the FIFO
output register data for output.
MBF1
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when the device is
reset.
4
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while MBF2 is
LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-
A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is
reset.
ODD/
EVEN
Odd/Even Parity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
PEFA
Port-A Parity Error
Flag
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having CSA LOW, ENA HIGH, W/RA LOW, MBA
HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of
A0-A35 inputs.
PEFB
Port-B Parity Error
Flag
O
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35, with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having CSB LOW, ENB HIGH, W/RB LOW,
MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the
state of the B0-B35 inputs
PGA
PGB
RST
Port-A Parity
Generation
I
I
I
Parity is generated for mail2 register reads from port A when PGA is HIGH.
The type of parity generated is selected by the state of the ODD/EVEN input.
Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The gener-
ated parity bits are output in the most significant bit of each byte.
Port-B Parity
Generation
Parity is generated for data reads from port B when PGB is HIGH. The type
of parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
Reset
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RST is LOW. This sets the AF,
MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-
to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to
select almost-full and almost-empty flag offset.
W/RA
W/RB
Port-A Write/Read
Select
I
I
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
Port-B Write/Read
Select
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
5
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UN-
LESS OTHERWISE NOTED)(1)
Symbol
VCC
VI(2)
Rating
Commercial
-0.5 to 7
-0.5 to VCC+0.5
-0.5 to VCC+0.5
±20
Unit
V
Supply Voltage Range
Input Voltage Range
Output Voltage Range
V
VO(2)
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO = < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
Operating Free Air Temperature Range
Storage Temperature Range
mA
mA
mA
mA
°C
°C
IOK
±50
IOUT
ICC
±50
±500
TA
0 to 70
TSTG
-65 to 150
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated condi-
tions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min. Max. Unit
Supply Voltage
4.5
2
5.5
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Current
Low-Level Output Current
VIL
0.8
-4
V
IOH
mA
mA
°C
IOL
8
TA
Operating Free-Air
Temperature
0
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA-
TURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
VOH
VOL
Test Conditions
IOH = -4 mA
IOL = 8 mA
Min. Typ.(1) Max.
Unit
V
VCC = 4.5V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
2.4
0.5
±50
±50
60
V
ILI
VI = VCC or 0
VO = VCC or 0
IO = 0 mA,
µA
µA
mA
ILO
ICC
VI = VCC or GND
Outputs HIGH
Outputs LOW
130
60
Outputs Disabled
CIN
VI = 0,
f = 1 MHz
f = 1 MHZ
4
pF
pF
COUT
VO = 0,
8
Notes:
1. All typical values are at VCC = 5 V, TA = 25°C.
6
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURES
IDT723611L15 IDT723611L20 IDT723611L30
Symbol
fS
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
Mhz
Mhz
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
–
15
6
66.7
–
20
8
50
–
–
33.4
tCLK
–
–
–
–
30
12
12
6
–
–
–
–
tCLKH
tCLKL
tDS
–
6
8
–
ns
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
4
5
–
ns
tENS1
CSA, W/RA, before CLKA↑; CSB, W/RB before
CLKB↑
6
–
6
–
7
–
ns
tENS2
tENS3
tPGS
ENA before CLKA↑; ENB before CLKB↑
MBA before CLKA↑; ENB before CLKB↑
4
4
4
–
–
–
5
5
5
–
–
–
6
6
6
–
–
–
ns
ns
ns
Setup Time, ODD/EVEN and PGB before
CLKB↑(1)
tRSTS
Setup Time, RST LOW before CLKA↑
or CLKB↑(2)
5
–
6
–
7
–
ns
tFSS
tDH
Setup Time, FS0 and FS1 before RST HIGH
5
1
–
–
6
1
–
–
7
1
–
–
ns
ns
Hold Time, A0-A35 after CLKA↑ and B0-B35
after CLKB↑
tENH1
CSA, W/RA after CLKA↑; CSB, W/RB
after CLKB↑
1
–
1
–
1
–
ns
tENH2
tENH3
tPGH
ENA after CLKA↑; ENB after CLKB↑
1
1
0
6
4
8
1
1
0
6
4
8
1
1
ns
ns
ns
ns
ns
ns
MBA after CLKA↑; MBB after CLKB↑
Hold TIme, ODD/EVEN and PGB after CLKB↑(1)
Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
Hold Time, FS0 and FS1 after RST HIGH
–
–
–
–
–
–
–
–
0
–
–
–
–
tRSTH
tFSH
7
4
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑
10
for EF, FF
tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑
9
–
16
–
20
–
ns
for AE, AF
Notes:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relation-
ship between CLKA cycle and CLKB cycle.
7
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT723611L15 IDT723611L20 IDT723611L30
Symbol
fS
Parameter
Min. Max. Min. Max.
Min. Max.
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
Access Time, CLKB↑ to B0-B35
Propagation Delay Time, CLKA↑ to FF
Propagation Delay Time, CLKB↑ to EF
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
–
2
2
2
2
2
1
66.7
10
10
10
10
10
9
–
2
2
2
2
2
1
50
12
12
12
12
12
12
–
2
2
2
2
2
1
33.4
15
tA
tWFF
tREF
tPAE
tPAF
tPMF
15
ns
15
ns
15
ns
15
ns
Propagation Delay Time, CLKA↑ to MBF1
LOW or MBF2 HIGH and CLKB↑ to MBF2
LOW or MBF1 HIGH
15
ns
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(1)
and CLKB↑ to A0-A35(2)
3
12
3
14
3
16
ns
tMDV
Propagation Delay Time, MBB to B0-B35 Valid
1
3
11
12
1
3
11.5
13
1
3
12
14
ns
ns
tPDPE
Propagation Delay Time, A0-A35 Valid to PEFA
Valid; B0-B35 Valid to PEFB Valid
tPOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
3
2
11
12
3
2
12
13
3
2
14
15
ns
ns
tPOPB(3)
Propagation Delay Time, ODD/EVEN to Parity
Bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
tPEPE
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGAto PEFA; CSB, ENB, W/RB,
MBB, or PGB to PEFB
1
3
12
14
1
3
13
15
1
3
15
16
ns
ns
tPEPB(3)
Propagation Delay Time, CSA, ENA W/RA,
MBA, or PGA to Parity Bits (A8, A17, A26,
A35); CSB, ENB, W/RB, MBB, or PGB to Parity
Bits (B8, B17, B26, B35)
tRSF
tEN
Propagation Delay Time, RST to AE LOW and
(AF, MBF1, MBF2) HIGH
1
2
15
10
1
2
20
12
1
2
30
14
ns
ns
Enable Time, CSA and W/RA LOW to A0-A35
Active and CSB LOW and W/RB HIGH to
B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
1
9
1
10
1
11
ns
Notes:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
8
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
The device must be reset after power up before data is written
to its memory.
SIGNAL DESCRIPTION
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the value
selected by the flag select (FS0, FS1) inputs. The values that
can be loaded into the register are shown in Table 1.
RESET (
)
RST
The IDT723611 is reset by taking the reset (RST) input
LOWforatleastfourport-Aclock(CLKA)andfourport-Bclock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of the FIFO and forces the full-
flag (FF) LOW, the empty flag (EF) LOW, the almost-empty
flag(AE)LOW,andthealmost-fullflag(AF)HIGH. Aresetalso
forces the mailbox flags (MBF1, MBF2) HIGH. After a reset,
FF is set HIGH after two LOW-to-HIGH transitions of CLKA.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (W/RA). The A0-A35 outputs are in the high-imped-
ance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW. Data
is loaded into the FIFO from the A0-A35 inputs on a LOW-to-
HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (CSB) and the port-B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW. Data is read from
the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition
ofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBB
is LOW, and EF is HIGH (see Table 3).
Almost-Full and
Almost-Empty Flag
Offset Register (X)
FS1
FS0
RST
16
12
8
H
H
L
H
L
↑
↑
↑
↑
H
L
4
L
Table 1. Flag Programming
W/ A
ENA
X
MBA
X
CLKA
A0-A35 Outputs
Port Functions
CSA
H
L
R
X
H
H
H
L
X
X
↑
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
None
L
X
None
L
H
L
FIFO Write
L
H
H
↑
Mail1 Write
L
L
L
X
↑
None
L
L
H
L
None
None
L
L
L
H
X
↑
L
L
H
H
Mail2 Read (set MBF2 HIGH)
Table 2. Port-A Enable Function Table
W/ B
ENB
X
MBB
X
CLKB
B0-B35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO Output Register
Active, FIFO Output Register
Active, Mail1 Register
Port Functions
CSB
H
L
R
X
H
H
H
L
X
X
↑
None
L
X
None
L
H
L
None
Mail2 Write
L
H
H
↑
L
L
L
X
↑
None
L
L
H
L
FIFO Read
L
L
L
H
X
↑
None
L
L
H
H
Active, Mail1 Register
Mail1 Read (set MBF1 HIGH)
Table 3. Port-B Enable Function Table
9
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
The setup and hold-time constraints to the port clocks for CLKB cycle can be the first synchronization cycle (see figure
the port chip selects (CSA, CSB) and write/read selects (W/ 4).
RA, W/RB)areonlyforenablingwriteandreadoperationsand
are not related to HIGH-impedance control of the data out-
puts. If a port enable is LOW during a clock cycle, the port’s
chip select and write/read select can change states during the
setup and hold-time window of the cycle.
FULL FLAG (
)
FF
The FIFO full flag is synchronized to the port clock that
writes data to its array (CLKA). When the full flag is HIGH, an
SRAM location is free to receive new data. No memory
locations are free when the full flag is LOW and attempted
writes to the FIFO are ignored.
SYNCHRONIZED FIFO FLAGS
EachFIFOflagissynchronizedtoitsportclockthroughtwo
flip-flop stages. This is done to improve the flags’ reliability by
reducingtheprobabilityofmestastableeventsontheiroutputs
when CLKA and CLKB operate asynchronously to one an-
other. FF and AF are synchronized to CLKA. EF and AE are
synchronized to CLKB. Table 4 shows the relationship to the
flags to the FIFO.
Each time a word is written to the FIFO, its write pointer is
incremented. The state machine that controls the full flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous
memory location is ready to be written in a minimum of three
port-A clock cycles. Therefore, a full flag is LOW if less than
two CLKA cycles have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on CLKA after the read sets the full flag HIGH and data can be
written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first syn-
chronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subse-
quent clock cycle can be the first synchronization cycle (see
figure 5).
EMPTY FLAG (
)
EF
The FIFO empty flag is synchronized to the port clock that
reads data from its array (CLKB). When the empty flag is
HIGH, new data can be read to the FIFO output register.
WhentheemptyflagisLOW,theFIFOisemptyandattempted
FIFO reads are ignored.
The FIFO read pointer is incremented each time a new
word is clocked to its output register. The state machine that
controls an empty flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to the
FIFO can be read to the FIFO output register in a minimum of
three port-B clock (CLKB) cycles. Therefore, an empty flag is
LOWifawordinmemoryisthenextdatatobesenttotheFIFO
output register and two CLKB cycles have not elapsed since
the time the word was written. The empty flag of the FIFO is
set HIGH by the second LOW-to-HIGH transition of CLKB,
and the new data word can be read to the FIFO output register
in the following cycle.
ALMOST-EMPTY FLAG (
)
AE
The FIFO almost empty-flag is synchronized to the port
clock that reads data from its array (CLKB). The state
machine that controls the almost-empty flag monitors a write
pointer and read pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+1, or
almost empty+2. The almost-empty state is defined by the
value of the almost-full and almost-empty offset register (X).
This register is loaded with one of four preset values during a
devicereset(seeresetabove). Thealmost-emptyflagisLOW
when the FIFO contains X or less words in memory and is
HIGH when the FIFO contains (X+1) or more words.
Two LOW-to-HIGH transitions on the port-B clock (CLKB)
are required after a FIFO write for the almost-empty flag to
reflect the new level of fill. Therefore, the almost-empty flag
of a FIFO containing (X+1) or more words remains LOW if two
CLKB cycles have not elapsed since the write that filled the
memory to the (X+1) level. The almost-empty flag is set HIGH
by the second CLKB LOW-to-HIGH transition after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition on CLKB begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the write that fills the
FIFO to (X+1) words. Otherwise, the subsequent CLKB cycle
can be the first synchronization cycle (see figure 6).
A LOW-to-HIGH transition on CLKB begins the first syn-
chronized cycle of a write if the clock transition occurs at time
tSKEW1 or greater after the write. Otherwise, the subsequent
Synchronized Synchronized
Number of Words
to CLKB
EF AE
to CLKA
AF FF
in the FIFO
0
1 to X
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X+1) to [64-(X+1)]
(64-X) to 63
64
H
H
H
ALMOST FULL FLAG (
)
AF
L
The FIFO almost-full flag is synchronized to the port clock
that writes data to its array (CLKA). The state machine that
controls an almost-full flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the value of the almost-full and almost-
Table 4. FIFO Flag Operation
Note:
X is the value in the almost-empty flag and almost-full
flag register.
10
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset above).
The almost-full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less words.
on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35, and port-B bytes are arranged as B0-B8,
B9-B17, B18-B26, and B27-B35. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is LOW if any
byte on the port has an odd/even number of LOW levels
applied to its bits.
The four parity trees used to check the A0-A35 inputs are
shared by the mail2 register when parity generation is se-
lected for port-A reads (PGA=HIGH). When port-A read from
the mail2 register with parity generation is selected with CSA
LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH,
the port-A parity error flag (PEFA) is held HIGH regardless of
the levels applied to the A0-A35 inputs. Likewise, the parity
trees used to check the B0-B35 inputs are shared by the mail1
register when parity generation is selected for port-B reads
(PGB=HIGH). Whenaport-Breadfromthemail1registerwith
parity generation is selected with CSB LOW, ENB HIGH, W/
RB LOW, MBB HIGH, and PGB HIGH, the port-B parity error
flag(PEFB)isheldHIGHregardlessofthelevelsappliedtothe
B0-B35 inputs.
Two LOW-to-HIGH transitions on the port-A clock (CLKA)
are required after a FIFO read for the almost-full flag to reflect
the new level of fill. Therefore, the almost-full flag of a FIFO
containing [64-(X+1)] or less words remains LOW if two CLKA
cycles have not elapsed since the read that reduced the
number of words in memory to [64-(X+1)]. The almost-full flag
is set HIGH by the second CLKA LOW-to-HIGH transition
after the FIFO read that reduces the number of words in
memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA
beginsthefirstsynchronizationcycleifitoccursattimetSKEW2
or greater after the read that reduces the number of words in
memory to [64-(X+1)]. Otherwise, the subsequent CLKA
cycle can be the first synchronization cycle (see figure 7).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723611 to pass
command and control information between port A and port B.
The mailbox-select (MBA, MBB) inputs choose between a
mail register and a FIFO for a port data transfer operation. A
LOW-to-HIGH transition on CLKA writes A0-A35 data to the
mail1 register when port-A write is selected by CSA, W/RA,
and ENA with MBA HIGH. A LOW-to-HIGH transition on
CLKB writes B0-B35 data to the mail2 register when port-B
write is selected by CSB, W/RB, and ENB with MBB HIGH.
Writing data to a mail register sets its corresponding flag
(MBF1or MBF2) LOW. Attempted writes to a mail register are
ignored while its mail flag is LOW.
Whentheport-Bdata(B0-B35)outputsareactive,thedata
onthebuscomesfromtheFIFOoutputregisterwhentheport-
B mailbox select (MBB) input is LOW and from the mail1
register when MBB is HIGH. Mail2 data is always present on
the port-A data (A0-A35) outputs when they are active. The
mail1 register flag (MBF1) is set HIGH by a LOW-to-HIGH
transition on CLKB when a port-B read is selected by CSB, W/
RB, and ENB with MBB HIGH. The mail2 register flag (MBF2)
is set HIGH by a LOW-to-HIGH transition on CLKA when a
port-A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA) or
port-B generate select (PGB) enables the IDT723611 to
generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35, with the most significant bit of each byte
usedastheparitybit. Port-BbytesarearrangedasB0-B8,B9-
B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regard-
less of the state of the parity generate select (PGA, PGB)
inputs. When data is read from a port with parity generation
selected,thelowereightbitsofeachbyteareusedtogenerate
a parity bit according to the level on the ODD/EVEN select.
The generated parity bits are substituted for the levels origi-
nally written to the most significant bits of each byte as the
word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port-B parity generate select (PGB)
and ODD/EVEN have setup and hold time constraints to the
port-B clock (CLKB) for a rising edge of CLKB used to read a
new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port-B bus (B0-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port-A bus (A0-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port write/read select (W/RA, W/RB)
input is LOW, the port mail select (MBA, MBB) input is HIGH,
chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH,
and the port parity generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the
contents of the register.
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
inputbusisreportedbyaLOWlevelontheportparityerrorflag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to the
level of the odd/even parity (ODD/EVEN) select input. A parity
error on one or more bytes of a port is reported by a LOW level
11
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKA
CLKB
tRSTH
tRSTS
tFSS
tFSH
RST
FS1,FS0
0,1
tWFF
tWFF
FF
tREF
EF
AE
AF
tPAE
tPAF
tRSF
MBF1,
MBF2
3024 drw 04
Figure 1. Device Reset Loading the X Register with the Value of Eight
tCLK
tCLKH
tCLKL
CLKA
FF
tENS1
tENH1
tENH1
CSA
tENS1
W/RA
MBA
tENH3
tENS3
tENS2
tDS
tENH2
tDH
tENH2
tENS2
tENH2
tENS2
ENA
A0 - A35
No Operation
W1
W2
ODD/
EVEN
tPDPE
tPDPE
PEFA
Valid
Valid
3024 drw 05
Figure 2. FIFO Write Cycle Timing
12
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
t
CLK
tCLKH
tCLKL
CLKB
EF
(HIGH)
CSB
W/RB
MBB
tENS2
tENH2
tENH2
tENH2
tENS2
tENS2
ENB
No
Operation
tMDV
tDIS
tA
t
A
tEN
B0 - B35
Word 1
Word 2
Previous Data
tPGH
tPGH
tPGS
tPGS
PGB,
ODD/
EVEN
3024 drw 06
Figure 3. FIFO Read Cycle Timing
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
WRA
MBA
HIGH
tENS3
tENS2
tENH3
tENH2
ENA
FFA
HIGH
tDS
tDH
A0 - A35
W1
(1)
tCLK
tCLKH
tSKEW1
tCLKL
1
2
CLKB
EF
tREF
tREF
Empty FIFO
LOW
CSB
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
tA
B0 -B35
W1
3024 drw 07
Note:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Figure 4.
Flag Timing and First Data Read when the FIFO is Empty
EF
13
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
MBB
ENB
tENH2
tENS2
HIGH
EFB
tA
Previous Word in FIFO Output Register
tSKEW1
Next Word From FIFO
tCLK
B0 -B35
(1)
tCLKH
tCLKL
1
2
CLKA
tWFF
tWFF
FF
FIFO Full
LOW
CSA
HIGH
WRA
MBA
tENH3
tENH2
tDH
tENS3
tENS2
ENA
tDS
A0 - A35
To FIFO
3024 drw 08
Note:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFto transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Figure 5.
Flag Timing and First Available Write when the FIFO is Full
FF
CLKA
ENA
tENS2
tENH2
(1)
tSKEW2
1
2
CLKB
AE
tPAE
tPAE
X Word in FIFO
(X+1) Words in FIFO
tENS2
tENH2
ENB
3024 drw 09
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next
CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 6. Timing for
when the FIFO is Almost Empty
AE
14
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
(1)
tSKEW2
1
2
CLKA
tENH2
tPAF
tENS2
ENA
tPAF
(64-X) Words in FIFO
[64-(X+1)] Words in FIFO
AF
CLKB
tENH2
tENS2
ENB
3024 drw 10
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next
CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for
when the FIFO is Almost Full
AF
CLKA
CSA
tENS1
tENH1
W/RA
MBA
ENA
tDH
tDS
W1
A0 - A35
CLKB
tPMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH2
tENS2
tMDV
tEN
tDIS
tPMR
B0 - B35
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
3024 drw 11
Note:
1. Port-B parity generation off (PGB = L)
Figure 8. Timing for Mail1 Register and
Flag
MBF1
15
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB
CSB
tENH1
tENS1
W/RB
MBB
ENB
B0 - B35
CLKA
tDH
tDS
W1
tPMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH2
tENS2
tEN
tDIS
tPMR
W1 (Remains valid in Mail2 Register after read)
A0 - A35
3024 drw 12
Note:
1. Port-A parity generation off (PGA = L)
Figure 9. Timing for Mail2 Register and
Flag
MBF2
ODD/
EVEN
W/RA
MBA
PGA
tPEPE
tPEPE
tPOPE
tPOPE
Valid
Valid
PEFA
Valid
Valid
3024 drw 13
Note:
1. CSA = L and ENA = H.
Figure 10. ODD/
, W/RA, MBA, and PGA to
EVEN
Timing
PEFA
16
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ODD/
EVEN
W/RB
MBB
PGB
t
PEPE
tPOPE
tPOPE
tPEPE
Valid
Valid
PEFB
Valid
Valid
3024 drw 14
Note:
1. CSB = L and ENB = H.
Figure 11. ODD/
, W/RB, MBB, and PGB to
EVEN
Timing
PEFB
ODD/
EVEN
LOW
CSA
W/RA
MBA
PGA
tEN
tPEPB
tPOPB
tPEPB
A8, A17,
A26, A35
Generated Parity
Mail2 Data
Generated Parity
Mail2 Data
3024 drw 15
Note:
1. ENA = H.
Figure 12. Parity Generation Timing when reading from the Mail2 Register
ODD/
EVEN
LOW
CSB
W/RB
MBB
PGB
tPEPB
tEN
tMDV
tPOPB
tPEPB
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
3024 drw 16
Note:
1. ENB = H.
Figure 13. Parity Generation Timing when reading from the Mail1 Register
17
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
V
CC = 5.5 V
350
300
= 1/2
f
f
s
data
T
°
= 25 C
A
C
= 0 pF
L
V
CC = 5.0 V
250
200
V
CC
= 4.5 V
150
100
50
0
0
80
10
20
30
40
50
60
70
f
– Clock Frequency – MHz
clock
3024 drw 17
Figure 14.
CALCULATING POWER DISSIPATION
The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with
CLKA and CLKB operating at frequency fS. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from FIgure 14, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT = VCC x ICC(f) + ∑(CL x VOH - VOL)2 X fO)
where:
CL
fO
=
=
output capacitance load
switching frequency of an output
VOH
VOL
=
=
output high-level voltage
output low-level voltage
When no read or writes are occurring on the IDT723611, the power dissipated by a single clock (CLKA or CLKB) input
running at frequency fS is calculated by:
PT = VCC x fS x 0.290 mA/MHz
18
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5 V
Ω
1.1 k
From Output
Under Test
30 pF(1)
Ω
680
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
1.5 V
1.5 V
GND
GND
tS
th
tW
3 V
3 V
Data,
1.5 V
1.5 V
Enable
Low-Level
1.5 V
GND
GND
Input
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
≈
3 V
Input
1.5 V
1.5 V
tPD
1.5 V
Low-Level
Output
GND
V
OL
tPZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
1.5 V
V
Output tPHZ
OL
≈
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3024 drw 18
Note:
1. Includes probe and jig capacitance.
Figure 15. Load Circuit and Voltage Waveforms
19
IDT723611 CMOS SyncFIFO
64 x 36
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
15
20
30
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
L
Low Power
3024 drw 19
723611 64 x 36 Synchronous FIFO
20
相关型号：
IDT72240L10TC
FIFO, 4KX8, 6.5ns, Synchronous, CMOS, CDIP28, 0.300 INCH, THIN, SIDE BRAZED, DIP-28
IDT
©2020 ICPDF网 联系我们和版权申明