IDT72251L25PFGI [IDT]
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| 型号： | IDT72251L25PFGI |
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INTEGRATED DEVICE TECHNOLOGY |
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ADVANCED
INFORMATION
IDT72251
CMOS SyncFIFO
8192 X 9
Integrated Device Technology, Inc.
FEATURES:
interprocessor communication.
• 8192 x 9-bit organization
• Pin/function compatible with IDT72421/722x1 family
• 15 ns read/write cycle time
This FIFO has a 9-bit input and output port. The input port
is controlled by a free-running clock (WCLK), and two write
enable pins (WEN1, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (REN1,
REN2). The read clock can be tied to the write clock for single
clockoperationorthetwoclockscanrunasynchronousofone
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
TheSynchronousFIFOhastwofixedflags, Empty(EF)and
Full (FF). Two programmable flags, Almost-Empty (PAE) and
Almost-Full (PAF), are provided for improved system control.
The programmable flags default to Empty+7 and Full-7 for
PAE and PAF, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (LD).
• Read and write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can
be set to any depth
• Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72251 is fabricated using IDT’s high-speed
submicron CMOS technology.
The IDT72251 SyncFIFO is a very high-speed, low-
power First-In, First-Out (FIFO) memory with clocked read
and write controls. The IDT72251 has a 8192 x 9-bit memory
array. This FIFO is applicable for a wide variety of data
buffering needs such as graphics, local area networks and
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN2
INPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
8192 x 9
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
3545 drw 01
Q0 - Q8
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
DECEMBER 1996
1996 Integrated Device Technology, Inc
DSC-3545/-
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.14
1
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
INDEX
4
3
2
32 31 30
1
5
RS
D
D
1
0
29
6
WEN1
WCLK
WEN2/LD
28
27
26
25
24
23
22
21
7
PAF
PAE
8
J32-1
9
V
CC
GND
REN1
RCLK
REN2
OE
10
11
12
13
Q
Q
Q
Q
8
7
6
5
14 15 16 17 18 19 20
2655 drw 02b
PLCC
TOP VIEW
PIN DESCRIPTIONS
Symbol
D0-D8
RS
Name
Data Inputs
Reset
I/O
Description
I
Data inputs for a 9-bit bus.
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
WCLK
WEN1
Write Clock
I
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
Write Enable 1
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin.
When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
WEN2/LD Write Enable 2/
Load
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag
offsets.
Q0-Q8
RCLK
Data Outputs
Read Clock
O
I
Data outputs for a 9-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are
asserted.
REN1
REN2
OE
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
I
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
EF
O
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
Almost-Empty
Flag
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF
FF
Programmable
Almost-Full Flag
O
O
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7. PAF is synchronized to WCLK.
Full Flag
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
2655 tbl 01
5.14
2
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Symbol
Rating
Commercial
Unit
VCCC
Commercial
4.5
5.0
5.5
V
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0
V
Supply Voltage
Supply Voltage
GND
VIH
0
0
0
V
V
Input High Voltage
Commercial
2.0
—
—
TA
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
°C
°C
VIL
Input Low Voltage
Commercial
—
—
0.8
V
TBIAS
TSTG
IOUT
°C
mA
2655 tbl 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
NOTE:
(2)
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthespecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CIN
Input Capacitance
VIN = 0V
10
10
pF
(1,2)
COUT
Output Capacitance
VOUT = 0V
pF
NOTES:
1. With output deselected (OE = HIGH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C)
IDT72251
Commercial
tCLK = 15, 20, 25, 35
Symbol
Parameter
Min.
-1
Typ.
Max.
Unit
µA
µA
V
(1)
ILI
Input Leakage Current (Any Input)
Output Leakage Current
—
1
(2)
ILO
-10
2.4
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = –2mA
Output Logic “0” Voltage, IOL = 8mA
Active Power Supply Current
—
—
—
0.4
80
V
(4)
ICC1
—
—
mA
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3 & 4.
Measurements are made with outputs unloaded. Tested at fCLK = 20MHz.
(3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA
(4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA
fCLK = 1/tCLK.
CL = external capacitive load (30pF typical)
5.14
3
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C
Commercial
72251L20 72251L25
Min. Max.
72251L15
Min. Max.
72251L35
Max. Min. Max. Unit
28.6 MHz
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Min.
—
3
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
—
2
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
3
tA
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
15
6
20
8
25
10
10
6
35
14
14
8
Clock HIGH Time
Clock LOW Time
6
8
Data Set-up Time
4
5
tDH
Data Hold Time
1
1
1
2
tENS
tENH
tRS
Enable Set-up Time
4
5
6
8
Enable Hold Time
Reset Pulse Width(1)
1
1
1
2
15
15
15
—
0
20
20
20
—
0
25
25
25
—
0
35
35
35
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
3
3
3
3
tOHZ
tWFF
tREF
tPAF
tPAE
3
8
3
3
3
—
—
—
—
6
10
10
10
10
—
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
tSKEW1 Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
tSKEW2 Skew Time Between Read Clock and Write Clock
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
28
—
35
—
40
—
42
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
30pF*
680Ω
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
3ns
2655 drw 03
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
1.5V
See Figure 1
2655 tbl 09
5.14
4
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
Read Enables (
,
) — When both Read Enables
REN1 REN2
(REN1, REN2) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
INPUTS:
When either Read Enable (REN1, REN2) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
Data In (D0 - D8) — Data inputs for 9-bit wide data.
When all the data has been read from the FIFO, the Empty
Flag(EF)willgoLOW,inhibitingfurtherreadoperations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
CONTROLS:
Reset ( ) — Reset is accomplished whenever the Reset
RS
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF)willberesettoHIGHaftertRSF. TheEmptyFlag(EF)and
ProgrammableAlmost-EmptyFlag(PAE)willberesettoLOW
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Output Enable ( ) — When Output Enable (OE) is
OE
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WriteEnable2/Load(WEN2/ )—Thisisadual-purpose
LD
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth
expansion. If Write Enable 2/Load (WEN2/LD) is set high at
Reset (RS= LOW), this pin operates as a second write enable
pin.
If the FIFO is configured to have two write enables, when
WriteEnable(WEN1)isLOWandWriteEnable2/Load(WEN2/
LD) is HIGH, data can be loaded into the input register and
RAMarrayontheLOW-to-HIGHtransitionofeverywriteclock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Write Clock (WCLK) — A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (
) — If the FIFO is configured for
WEN1
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is low, data can be loaded into the input register and
RAMarrayontheLOW-to-HIGHtransitionofeverywriteclock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowingavalidwritetobegin. WriteEnable1(WEN1)andWrite
Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset
(RS=low). The IDT7225 device contain four 8-bit offset
registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/
LD) are set low, data on the inputs D is written into the Empty
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full(LeastSignificantBit)offsetregisteronthethirdtransition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
againwritestotheEmpty(LeastSignificantBit)offsetregister.
Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
EmptyFlag(EF)andProgrammableAlmost-EmptyFlag(PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
5.14
5
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur
atonetime. Oneortwooffsetregisterscanbewrittenandthen
bybringingtheWriteEnable2/Load(WEN2/LD)pinHIGH,the
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence
is written.
The contents of the offset registers can be read on the
output lines when the Write Enable 2/Load (WEN2/LD) pin is
set low and both Read Enables (REN1, REN2) are set LOW.
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
LD
0
WEN1
0
WCLK(1)
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
0
1
No Operation
Write Into FIFO
No Operation
1
NOTE:
1. Thesameselectionsequenceappliestoreadingfromtheregisters. REN1
and REN2 are enabled and read is performed on the LOW-to-HIGH
transition of RCLK.
A read and write should not be performed simultaneously
to the offset registers.
Figure 2. Write Offset Register
OUTPUTS:
Full Flag ( ) — The Full Flag (FF) will go LOW, inhibiting
FF
72251 — 8192 x 9-BIT
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 8192 writes for the IDT72251.
The Full Flag (FF) is synchronized with respect to the LOW-
to-HIGH transition of the write clock (WCLK).
8
8
7
0
0
Empty Offset (LSB)
Default Value 007H
4
(MSB)
00000
Empty Flag ( ) — The Empty Flag (EF) will go LOW,
EF
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
8
8
7
0
0
Full Offset (LSB)
Default Value 007H
Programmable Almost-Full Flag (
) — The
PAF
Programmable Almost-Full Flag (PAF) will go LOW when the
FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS), the Programmable Almost-Full
Flag (PAF) will go LOW after 8192 writes for the IDT72251.
The offset “m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable
Almost-Full Flag (PAF) will go LOW at Full-7 words.
TheProgrammableAlmost-FullFlag(PAF)issynchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
4
(MSB)
00000
Figure 3. Offset Register Location and Default Values
Programmable Almost-Empty Flag (
) — The
PAE
TABLE 1: STATUS FLAGS
Programmable Almost-Empty Flag (PAE) will go LOW when
the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty offset registers. If no
reads are performed after Reset the Programmable Almost-
Empty Flag (PAE) will go HIGH after "n+1" for the IDT72251.
If there is no Empty offset specified, the Programmable
Almost-Empty Flag (PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty Flag (PAE) is
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).
NUMBER OF WORDS
IN FIFO
FF
PAF
H
PAE
L
EF
L
0
H
H
H
H
L
1 to n(1)
H
L
H
H
H
H
(n+1) to (8192-(m+1)
(8192-m)(2) to 8191
8192
H
H
L
H
L
H
Data Outputs (Q0 - Q8) — Data outputs for a 9-bit wide
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
data.
5.14
6
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
tRS
RS
tRSS
tRSR
REN1,
REN2
t
RSS
RSS
t
RSR
RSR
WEN1
t
t
(1)
WEN2/LD
t
RSF
RSF
EF, PAE
FF, PAF
t
tRSF
(2)
OE = 1
Q0 - Q8
OE = 0
2655 drw 06
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as
a load enable for the programmable flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
5.14
7
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
t
DH
tDS
D0 - D8
DATA IN VALID
tENH
tENS
NO OPERATION
NO OPERATION
WEN1
WEN2/
(If Applicable)
tWFF
tWFF
FF
(1)
SKEW1
t
RCLK
REN1,
REN2
2655 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 5. Write Cycle Timing
5.14
8
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
t
CLK
t
CLKL
t
CLKH
RCLK
tENH
t
ENS
REN1,
REN2
NO OPERATION
tREF
tREF
EF
t
A
Q0
- Q8
VALID DATA
tOLZ
t
OHZ
tOE
OE
(1)
SKEW1
t
WCLK
WEN1
WEN2
2655 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EFmay not change state until the next RCLK edge. Figure 6. Read Cycle
Timing
Figure 6. Read Cycle Timing
5.14
9
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
D0 - D8
D1
D2
D3
D0 (First Valid
tENS
WEN1
WEN2
(If Applicable)
(1)
tFRL
tSKEW1
RCLK
EF
tREF
REN1,
REN2
tA
tA
Q0 - Q8
D0
D1
tOLZ
tOE
OE
2655 drw 09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
5.14
10
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK
tDS
tDS
tSKEW1
tSKEW1
DATA WRITE
D0 - D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(If Applicable)
RCLK
tENH
tENH
tENS
tENS
REN1,
REN2
tA
LOW
OE
tA
Q0 - Q8
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.14
11
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
tDS
DATA WRITE 1
tENH
DATA WRITE 2
D0 - D8
tENH
tENS
tENS
tENS
WEN1
tENH
tENH
tENS
WEN2
(If Applicable)
(1)
tFFL
(1)
tFRL
tSKEW1
tSKEW1
RCLK
EF
tREF
tREF
tREF
REN1,
REN2
LOW
OE
tA
DATA READ
Q0 - Q8
DATA IN OUTPUT REGISTER
2655 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
5.14
12
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLKH
tCLKL
(4)
WCLK
WEN1
tENS
tENH
tENH
tENS
WEN2
(If Applicable)
tPAF
(1)
Full - m words in FIFO
(2)
Full - (m+1) words in FIFO
PAF
(3)
tSKEW2
tPAF
RCLK
tENS
tENH
REN1,
REN2
2655 drw 12
NOTES:
1. PAF offset = m.
2. 8192 - m words in FIFO IDT72251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAFto change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.14
13
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLKL
tCLKH
WCLK
WEN1
t
ENH
ENH
t
ENS
ENS
t
t
WEN2
(If Applicable)
(1)
n words in FIFO
n+1 words in FIFO
PAE
tPAE
tPAE
(2)
tSKEW2
(3)
RCLK
tENS
tENH
REN1,
REN2
2655 drw 13
NOTES:
1. PAE offset = n.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAEto change during that clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
5.14
14
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
t
t
ENS
ENS
tENH
LD
WEN1
tDS
tDH
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
2655 drw 14
Figure 12. Write Offset Registers Timing
tCLK
tCLKH
tCLKL
RCLK
LD
tENS
tENH
tENS
REN1,
REN2
tA
Q0 - Q7
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
2655 drw 15
Figure 13. Read Offset Registers Timing
5.14
15
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Configuration, the Read Enable 2 (REN2) control input can be
grounded (see Figure 14). In this configuration, the Write
Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the
pin operates as a control to load and read the programmable
flag offsets.
SINGLE DEVICE CONFIGURATION - A single IDT72251
may be used when the application requirements are for 8192
words or less. When the IDT72251 is in a Single Device
RESET
)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE 1
OUTPUT ENABLE (
WRITE ENABLE 1
)
)
)
)
WRITE ENABLE 2/LOAD (WEN/
)
IDT
72251
DATA IN (D
0
- D8
DATA OUT (Q
0
- Q8)
FULL FLAG
)
)
EMPTY FLAG
)
PROGRAMMABLE ALMOST FULL
PROGRAMMABLE ALMOST EMPTY
)
3545 drw 16
READ ENABLE 2 (
)
Figure 14. Block Diagram of Single 8192 x 9 Synchronous FIFO
using two IDT72251. Any word width can be attained by
adding additional IDT72251s.
WIDTH EXPANSION CONFIGURATION - Word width may
be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should
be created for each of the end-point status flags (EFand FF).
The partial status flags (AEand AF) can be detected from any
one device. Figure 15 demonstrates a 18-bit word width by
When the IDT72251is in a Width Expansion Configuration,
the Read Enable 2 (REN2) control input can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
RESET
)
RESET
)
DATA IN (D)
18
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE1
WRITE ENABLE2/LOAD (WEN
READ ENABLE
)
)
OUTPUT ENABLE
)
)
IDT
72251
IDT
72251
PROGRAMMABLE
)
FULL FLAG ) #1
FULL FLAG ) #2
EMPTY FLAG ) #1
EMPTY FLAG ) #2
9
PROGRAMMABLE
)
9
DATA OUT (Q)
18
READ ENABLE 2
)
READ ENABLE 2
)
3545 drw 17
Figure 15. Block Diagram of 8192 x 18 Synchronous FIFO
Used in a Width Expansion Configuration
5.14
16
IDT72251 CMOS SyncFIFO
8192 x 9
COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT72251 can be adapted to access from one device to the next in a sequential manner.
applications when the requirements are for greater than 8192 The IDT72251 operates in the Depth Expansion configuration
words. The existence of two enable pins on the read and write when the following conditions are met:
port allow depth expansion. The Write Enable 2/Load pin is 1. TheWEN2/ LDpinisheldHIGHduringResetsothatthispin
used as a second write enable in a depth expansion configu-
ration thus the Programmable flags are set to the default 2. External logic is used to control the flow of data.
values. Depth expansion is possible by using one enable Please see the Application Note" DEPTH EXPANSION OF
operates a second Write Enable.
input for system control while the other enable input is con- IDT'SSYNCHRONOUSFIFOsUSINGTHERINGCOUNTER
trolled by expansion logic to direct the flow of data. A typical APPROACH" for details of this configuration.
application would have the expansion logic alternate data
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
Device Type Power
Speed Package
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
J
Plastic Leaded Chip Carrier (PLCC)
Clock Cycle
15
20
25
35
Com'l. Only
Time (tCLK)
Speed in ns
L
Low Power
72251
8192 x 9 Synchronous FIFO
3545a drw 18
5.14
17
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