IDT72271LA20PFG8 [IDT]
FIFO, 32KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64;
| 型号： | IDT72271LA20PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64 先进先出芯片 |
| 文件： | 总27页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SuperSync FIFO™
16,384 x 9
32,768 x 9
IDT72261LA
IDT72271LA
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
IDT72261LA 16,384 x 9
IDT72271LA 32,768 x 9
• Pin-compatible with the IDT72281/72291 SuperSync FIFOs
• 10ns read/write cycle time (8ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
DESCRIPTION:
The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short. (The
variableclockcyclecountingdelayassociatedwiththelatencyperiodfound
on previous SuperSync devices has been eliminated on this SuperSync
family.)
• Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONAL BLOCK DIAGRAM
D0 -D8
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
16,384 x 9
32,768 x 9
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0 -Q8
4671 drw 01
OE
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
SEPTEMBER 2002
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4671/2
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsistsofactivatingRENandenabling
arisingRCLKedge,willshiftthewordfrominternalmemorytothedataoutput
lines.
DESCRIPTION (CONTINUED)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-
munications,datacommunicationsandotherapplicationsthatneedtobuffer
largeamountsofdata.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
and Read Enable (REN) input. Data is read from the FIFO on every rising
edgeofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovided
forthree-statecontroloftheoutputs.
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
WEN
SEN
DC(1)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
VCC
4
VCC
5
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
VCC
6
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
7
8
9
10
11
12
13
14
15
16
Q7
Q6
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4671 drw 02
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
2
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
areusedtoloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrising
edgeofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardless
ofwhetherserialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
DESCRIPTION (CONTINUED)
InFWFTmode,thefirstwordwrittentoanemptyFIFOis clockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
tothe correspondingdata inputs ofthe next). Noexternallogicis required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF
and FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallelprogramming,WENtogetherwithLDoneachrisingedgeofWCLK,
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72261LA/72271LA are fabricated using IDT’s high speed sub-
micron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72261LA
72271LA
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4671 drw 03
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
3
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
D0–D8
MRS
Name
DataInputs
I/O
I
Description
Datainputs fora9-bitbus.
MasterReset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),
and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the
first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Write Clock
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial
In After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into
the programmable registers forparallelprogramming, andwhenenabledbySEN, therising
edge of WCLK writes one bit of data into the programmable register for serial programming.
WEN
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets
fromtheprogrammableregisters.
REN
OE
ReadEnable
OutputEnable
SerialEnable
Load
I
I
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SEN
LD
SENenablesserialloadingofprogrammableflagoffsets.
DuringMasterReset, LD selects one oftwopartialflagdefaultoffsets (127or1,023) anddetermines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pinmustbe tiedtoeitherVCC orGNDandmustnottoggle afterMasterReset.
FF/IR
Full Flag/
Input Ready
O
Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemory
is full. Inthe FWFTmode, the IR functionis selected.IR indicates whetherornotthereis space
availableforwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
IntheIDTStandardmode, the EF functionis selected. EF indicates whetherornotthe FIFOmemory
is empty. InFWFTmode, the OR functionis selected.ORindicates whetherornotthereis validdata
availableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO
minusthefulloffsetvaluem,whichisstoredintheFullOffsetregister.Therearetwopossibledefault
values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAE goes LOWifthe numberofwords inthe FIFOmemoryis less thanoffsetn, whichis storedinthe
EmptyOffsetregister. There are twopossible defaultvalues forn:127or1,023. Othervalues forn
canbeprogrammedintothedevice.
HF
Half-FullFlag
DataOutputs
Power
O
O
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
Dataoutputsfora9-bus
Q0–Q8
VCC
+5 Volt power supply pins.
GND
Ground
Groundpins.
4
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+7
V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
SupplyVoltage
4.5
5.0
5.5
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50 to +50
°C
Commercial/Industrial
SupplyVoltage
GND
VIH
0
0
0
V
V
DC Output Current
mA
InputHighVoltage
2.0
—
—
Commercial/Industrial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
(1)
VIL
Input Low Voltage
Commercial/Industrial
—
0
—
—
—
0.8
+70
+85
V
TA
TA
OperatingTemperature
Commercial
°C
°C
OperatingTemperature
Industrial
–40
NOTE:
1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
IDT72261LA
IDT72271LA
Commercial and Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
–1
Max.
1
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
µ A
µA
V
ILO(3)
–10
2.4
—
10
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
—
0.4
75
VOL
V
ICC1(4,5,6)
ICC2(4,7)
—
mA
mA
—
20
NOTES:
1. Industrial temperature range product for the 15ns and 20ns speed grade are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 15 + 1.85*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Commercial
Commercial & Industrial(2)
IDT72261LA10
IDT72271LA10
IDT72261LA15
IDT72271LA15
Min. Max.
IDT72261LA20
IDT72271LA20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
100
8
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
—
2
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
—
—
tA
DataAccessTime
Clock Cycle Time
Clock High Time
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6
15
6
20
8
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0
1
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
3
4
5
0
1
1
3
4
5
tLDH
tRS
LoadHoldTime
0
1
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
10
10
10
—
0
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
3
4
5
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
0
0
0
2
3
3
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
OutputEnabletoOutputinHighZ
Write Clock to FF or IR
2
6
3
8
3
—
—
—
—
—
5
8
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
—
—
10
20
60
Read Clock to EF or OR
8
Write Clock to PAF
8
Read Clock to PAE
8
Clock to HF
16
—
—
—
tSKEW1
tSKEW2
tSKEW3
Skew time between RCLK and WCLK for FF/IR
Skew time between RCLK and WCLK for PAE and PAF
Skew time between RCLK and WCLK for EF/OR
12
60
15
60
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
30pF*
680Ω
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4671 drw 04
1.5V
1.5V
Figure 2. Output Load
See Figure 1
* Includes jig and scope capacitances.
6
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause
the FIFO to become empty. When the last word has been read from the
FIFO,theEF willgoLOWinhibitingfurtherreadoperations.RENis ignored
when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevanttimingdiagrams forIDTStandardmode canbe foundinFigure
7, 8 and 11.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72261LA/72271LAsupporttwodifferenttimingmodes ofopera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset,
by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whetherornotthereareanywords presentintheFIFO.Italsouses theFull
Flag function (FF) to indicate whether or not the FIFO has any free space
for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using the Read Enable (REN) and
RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
beselected. This modeuses OutputReady(OR)toindicatewhetherornot
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
upthe FIFO. PAE willgoHIGHaftern + 2words have beenloadedintothe
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
8,194thwordforthe IDT72261LAand 16,386thwordforthe IDT72271LA,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF willgoLOWafter(16,385-m)writes forthe IDT72261LA and(32,769-
m) writes for the IDT72271LA, where m is the full offset value. The default
setting for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 16,385 writes for the 72261LA and
32,769 writes for the IDT72271LA, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.
IftheFIFOis full,thefirstreadoperationwillcausetheIR flagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is
ignored when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After
the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where nis the emptyoffsetvalue.The defaultsettingforthis value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
oncethe8,193thwordfor IDT72261LAand 16,385thwordforIDT72271LA
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (16,384-m)
writes fortheIDT72261LAand(32,768-m)writes fortheIDT72271LA. The
offset “m” is the full offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 16,384 writes for the IDT72261LA and
32,768 for the IDT72271LA, respectively.
7
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PROGRAMMING FLAG OFFSETS
default PAE offset value of 07FH (a threshold 127 words from the empty
Full and Empty Flag offset values are user programmable. The boundary), and a default PAF offset value of 07FH (a threshold 127 words
IDT72261LA/72271LA has internal registers for these offsets. Default fromthe fullboundary). See Figure 3, OffsetRegisterLocationandDefault
settings are stated in the footnotes of Table 1 and Table 2. Offset values Values.
can be programmed into the FIFO in one of two ways; serial or parallel
In addition to loading offset values into the FIFO, it also possible to read
loading method. The selection of the loading method is done using the LD the currentoffsetvalues. Itis onlypossible toreadoffsetvalues via parallel
(Load) pin. During Master Reset, the state of the LD input determines read.
whether serial or parallel flag offset programming is enabled. A HIGH on
Figure 4, Programmable Flag Offset Programming Sequence, summa-
LD during Master Reset selects serial loading of offset values and in rizes the control pins and sequence for both serial and parallel program-
addition, sets a default PAE offset value of 3FFH (a threshold 1,023 words ming modes. For a more detailed description, see discussion that follows.
from the empty boundary), and a default PAF offset value of 3FFH (a
The offset registers may be programmed (and reprogrammed) any time
threshold1,023wordsfromthefullboundary). ALOWonLDduringMaster after Master Reset, regardless of whether serial or parallel programming
Reset selects parallel loading of offset values, and in addition, sets a has been selected.
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72261LA
0
IDT72271LA
0
1 to n (1)
FF PAF HF PAE EF
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) (2) to 16,383
16,384
(n+1) to 16,384
16,385 to (32,768-(m+1))
(2)
L
(32,768-m)
to 32,767
L
L
32,768
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72261LA
IDT72271LA
0
IR PAF HF PAE OR
0
1 to n+1(1)
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
(n+2) to 16,385
Number of
Words in
H
H
H
H
(n+2) to 8,193
(2)
(2)
(
1)
FIFO
8,194 to (16,385-(m+1))
16,386 to (32,769-(m+1))
L
(32,769-m)
(16,385-m)
to 32,768
32,769
to 16,384
L
L
16,385
4671 drw 05
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA 16,384 x 9 BIT
IDT72271LA 32,768 x 9 BIT
7
7
8
0
8
0
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
8
5
0
0
8
8
6
0
0
EMPTY OFFSET (MSB) REG.
00H
EMPTY OFFSET (MSB) REG.
00H
7
7
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
0
0
8
5
8
6
FULL OFFSET (MSB) REG.
00H
FULL OFFSET (MSB) REG.
00H
4671 drw 06
Figure 3. Offset Register Location and Default Values
WCLK
RCLK
X
Selection
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
0
0
1
1
Full Offset (MSB)
X
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
0
0
1
1
0
1
1
0
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72261LA
30 bits for the 72271LA
X
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
No Operation
Write Memory
X
1
1
0
1
1
X
X
X
X
Read Memory
No Operation
1
1
X
1
0
1
X
X
X
4671 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
registers can be written and then by bringing LD HIGH, write operations
can be redirected to the FIFO memory. When LD is set LOW again, and
WEN is LOW, the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel programming
can also be interrupted by setting LD LOW and toggling WEN.
Note thatthe status ofa partialflag(PAE orPAF)outputis invalidduring
the programming process. From the time parallel programming has
begun, a partialflagoutputwillnotbe validuntilthe appropriate offsetword
has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid
aftertwomorerisingWCLKedges plus tPAF,PAE willbevalidafterthenext
two rising RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
registerpointer. Thecontents oftheoffsetregisters canbereadontheQ0-
Qn pins when LD is set LOW and REN is set LOW. For the IDT72261LA
and the IDT72271LA, data are read via Qn from the Empty Offset LSB
Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read from the Empty Offset
MSB Register. Upon the third LOW-to-HIGH transition of RCLK, data are
read from the Full Offset LSB Register. Upon the fourth LOW-to-HIGH
transition of RCLK, data are read from the Full Offset MSB Register. The
fifth transition of RCLK reads, once again, from the Empty Offset LSB
Register. See Figure 15, Parallel Read of Programmable Flag Registers
for the IDT72261LA, for the timing diagram for this mode.
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: when LD and SEN are set LOW, data on
the SI input are written, one bit for each WCLK rising edge, starting with
the Empty Offset LSB and ending with the Full Offset MSB. A total of 28
bits for the IDT72261LA and 30 bits for the IDT72271LA. See Figure 13,
SerialLoadingofProgrammable FlagRegisters, forthe timingdiagramfor
this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written
to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in sequence is
written to the registers via SI. If an interruption of serial programming is
desired, it is sufficient either to set LD LOW and deactivate SEN or to set
SEN LOW and deactivate LD. Once LD and SEN are both restored to a
LOW level, serial offset programming continues.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria;PAF willbevalidaftertwomorerisingWCLKedges plus tPAF,PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
It is permissible to interrupt the offset register read sequence with reads
or writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,orbothtogether.WhenRENandLDarerestoredtoaLOW level,
readingofthe offsetregisters continues where itleftoff. Itshouldbe noted,
and care should be taken from the fact that when a parallel read of the flag
offsets is performed, the data word that was present on the output lines
Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, RETRANSMIT OPERATION
then programming of PAE and PAF values can be achieved by using a
The Retransmit operation allows data that has already been read to be
combination of the LD, WCLK, WEN and Dn input pins. For the accessed again. There are two stages: first, a setup procedure that resets
IDT72261LA and the IDT72271LA, programming PAE and PAF proceeds the read pointer to the first location of memory, then the actual retransmit,
as follows: when LD and WEN are set LOW, data on the inputs Dn are which consists of reading out the memory contents, starting at the
written into the Empty Offset LSB Register on the first LOW-to-HIGH beginning of memory.
transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK,
Retransmit setup is initiated by holding RT LOW during a rising RCLK
data are written into the Empty Offset MSB Register. Upon the third LOW- edge. REN andWENmustbe HIGHbefore bringingRTLOW. Atleastone
to-HIGH transition of WCLK, data are written into the Full Offset LSB word, but no more than D - 2words should have been written into the FIFO
Register. Upon the fourth LOW-to-HIGH transition of WCLK, data are between Reset (Master or Partial) and the time of Retransmit setup.
written into the Full Offset MSB Register. The fifth transition of WCLK D = 16,384fortheIDT72261LAandD = 32,768fortheIDT72271LAinIDT
writes, once again, to the Empty Offset LSB Register. See Figure 14, Standard mode. In FWFT mode, D = 16,385 for the IDT72261LA and D
ParallelLoadingofProgrammable FlagRegisters forthe IDT72261LA, for = 32,769 for the IDT72271LA.
the timing diagram for this mode.
IfIDTStandardmodeis selected,theFIFOwillmarkthebeginningofthe
The act of writing offsets in parallel employs a dedicated write offset Retransmit setup by setting EF LOW. The change in level will only be
registerpointer.Theactofreadingoffsets employs adedicatedreadoffset noticeable if EF was HIGH before setup. During this period, the internal
registerpointer. The twopointers operate independently;however, a read read pointer is initialized to the first location of the RAM array.
anda write shouldnotbe performedsimultaneouslytothe offsetregisters.
AMasterResetinitializes bothpointers tothe EmptyOffset(LSB)register. may begin starting with the first location in memory. Since IDT Standard
A Partial Reset has no effect on the position of these pointers. mode is selected, every word read including the first word following
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
Write operations to the FIFO are allowed before and during the parallel Retransmit setup requires a LOW on REN to enable the rising edge of
programming sequence. In this case, the programming of all offset RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
registers does not have to occur at one time. One, two or more offset relevant timing diagram.
10
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by settingOR HIGH. During this period, the internal read and PAF flags begin with the rising edge of RCLK that RT is setup. PAE
pointer is set to the first location of the RAM array.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
is synchronized to RCLK, thus on the second rising edge of RCLK afterRT
When OR goes LOW, Retransmit setup is complete; at the same time, is setup, the PAE flag will be updated. HF is asynchronous, thus the rising
the contents of the first location appear on the outputs. Since FWFT mode edge of RCLK that RT is setup will update HF. PAF is synchronized to
is selected, the first word appears on the outputs, no LOW on REN is WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
necessary. Reading all subsequent words requires a LOW on REN to rising edge of RCLK that RT is setup will update PAF. RT is synchronized
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT to RCLK.
Mode), for the relevant timing diagram.
11
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
which consists of reading out the memory contents, starting at the
beginning of the memory.
SIGNAL DESCRIPTION
INPUTS:
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
IfIDTStandardmodeis selected,theFIFOwillmarkthebeginningofthe
Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
Retransmit setup requires a LOW on REN to enable the rising edge of
RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by settingOR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array. PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH.
If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along
with IR and OR, are selected. OR will go HIGH and IR will go LOW.
IfLD is LOWduringMasterReset, thenPAE is assigneda threshold127
words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO memory. It also
usestheFullFlagfunction(FF)toindicatewhetherornottheFIFOmemory
has any free space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the Read
Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Qn after three
RCLK rising edges, REN = LOW is not necessary. Subsequent words must
be accessed using the Read Enable (REN) and RCLK.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a
LOW state. As in the case of the Master Reset, the internal read and write
pointers are settothe firstlocationofthe RAMarray,PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
atthe time ofPartialResetis alsoretained. The outputregisteris initialized
to all zeroes. PRS is asynchronous.
AfterMasterReset, FWFT/SIacts as a serialinputforloadingPAE and
PAF offsets intothe programmable registers. The serialinputfunctioncan
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
WRITE CLOCK (WCLK)
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
Awrite cycle is initiatedonthe risingedge ofthe WCLKinput.Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
theWCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,
the FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
12
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output buffers
array on the rising edge of every WCLK cycle if the device is not full. Data receive data from the output register. When OE is HIGH, the output data
is stored in the RAM array sequentially and independently of any ongoing bus (Qn) goes into a high impedance state.
read operation.
When WEN is HIGH, no new data is written in the RAM array on each LOAD (LD)
WCLK cycle.
This is adualpurposepin. DuringMasterReset,thestateoftheLDinput
To prevent data overflow in the IDT Standard mode, FF will go LOW, determines one of two default offset values (127 or 1,023) for the PAE and
inhibiting further write operations. Upon the completion of a valid read PAF flags, along with the method by which these offset registers can be
cycle, FF will go HIGH allowing a write to occur. The FF is updated by two programmed, parallel or serial. After Master Reset, LD enables write
WCLK cycles + tSKEW after the RCLK cycle.
operations to and read operations from the offset registers. Only the offset
Topreventdata overflow inthe FWFTmode, IR willgoHIGH, inhibiting loading method currently selected can be used to write to the registers.
further write operations. Upon the completion of a valid read cycle, IR will Offset registers can be read only in parallel. A LOW on LD during Master
go LOW allowing a write to occur. The IR flag is updated by two WCLK Reset selects a default PAE offset value of 07FH (a threshold 127 words
cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard 127 words from the full boundary), and parallel loading of other offset
mode.
from the empty boundary), a default PAF offset value of 07FH (a threshold
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a
default PAF offset value of 3FFH (a threshold 1,023 words from the full
boundary), and serial loading of other offset values.
After Master Reset, the LD pin is used to activate the programming
process of the flag offset values PAE and PAF. Pulling LD LOW will begin
a serial loading or parallel load or read of these offset values. See Figure
4, Programmable Flag Offset Programming Sequence.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can
be read on the outputs, on the rising edge of the RCLK input. It is
permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR,
PAE and HF flags will not be updated. (Note that RCLK is only capable of
updating the HF flag to HIGH.) The Write and Read Clocks can be
independent or coincident.
OUTPUTS:
READ ENABLE (REN)
FULL FLAG (FF/IR)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
Whenthe RENinputis HIGH,the outputregisterholds the previous data
and no new data is loaded into the output register. The data outputs Q0-
Qn maintain the previous data value.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibitingfurtherreadoperations. REN is ignoredwhenthe FIFOis empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flagis updatedbytwoRCLKcycles +tSKEW afterthevalidWCLKcycle.
Inthe FWFTmode, the firstwordwrittentoanemptyFIFOautomatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
is empty.
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
functionisselected.WhentheFIFOisfull,FFwillgoLOW,inhibitingfurther
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performedaftera reset(either MRS orPRS), FF willgoLOWafterDwrites
to the FIFO (D = 16,384 for the IDT72261LA and 32,768 for the
IDT72271LA). See Figure 7, Write Cycle and Full Flag Timing (IDT
Standard Mode), for the relevant timing information.
InFWFTmode, the InputReady(IR)functionis selected. IR goes LOW
when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write opera-
tions. If no reads are performed after a reset (either MRS or PRS), IR will
go HIGH after D writes to the FIFO (D = 16,385 for the IDT72261LA and
32,769 for the IDT72271LA) See Figure 9, Write Timing (FWFT Mode), for
the relevant timing information.
The IR status not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
are double register-buffered outputs.
SERIAL ENABLE (SEN)
EMPTY FLAG (EF/OR)
The SEN input is an enable used only for serial programming of the
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
offset registers. The serial programming method must be selected during (EF) function is selected. When the FIFO is empty, EF will go LOW,
Master Reset. SEN is always used in conjunction with LD. When these inhibiting further read operations. When EF is HIGH, the FIFO is not
lines are both LOW, data at the SI input can be loaded into the program empty. See Figure 8, Read Cycle, Empty Flag and First Word Latency
registerone bitforeachLOW-to-HIGHtransitionofWCLK. (See Figure 4.) Timing (IDT Standard Mode), for the relevant timing information.
When SEN is HIGH, the programmable registers retains the previous
In FWFT mode, the Output Ready (OR) function is selected. OR goes
settings and no offsets are loaded. SEN functions the same way in both LOW at the same time that the first word written to an empty FIFO appears
IDT Standard and FWFT modes.
13
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
validontheoutputs. OR stays LOWaftertheRCLKLOWtoHIGHtransition LOW when there are n words or less in the FIFO. The offset “n” is the empty
that shifts the last word from the FIFO memory to the outputs. OR goes offset value. The default setting for this value is stated in the footnote of
HIGH only with a true read (RCLK with REN = LOW). The previous data Table 1.
stays at the outputs, indicating the last word was read. Further data reads
are inhibiteduntilOR goes LOWagain. See Figure 10, ReadTiming(FWFT intheFIFO.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable
Mode), for the relevant timing information.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
2.
EF/OR is synchronous and updated on the rising edge of RCLK.
See Figure 17, Programmable Almost-EmptyFlagTiming(IDTStandard
In IDT Standard mode, EF is a double register-buffered output. In FWFT and FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PAE is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
HALF-FULL FLAG (HF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
This output indicates a half-full FIFO. The rising WCLK edge that fills the
reaches the almost-full condition. In IDT Standard mode, if no reads are FIFO beyond half-full sets HF LOW. The flag remains LOW until the
performed after reset (MRS), PAF will go LOW after (D - m) words are difference between the write and read pointers becomes less than or equal
written to the FIFO. The PAF will go LOW after (16,384-m) writes for the to half of the total depth of the device; the rising RCLK edge that accom-
IDT72261LA and (32,768-m) writes for the IDT72271LA. The offset “m” is plishes this condition sets HF HIGH.
the fulloffsetvalue. The defaultsettingforthis value is statedinthe footnote
of Table 1.
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the for the IDT72261LA and 32,768 for the IDT72271LA.
IDT72261LAand(32,769-m)writes forthe IDT72271LA, where mis the full
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
offset value. The default setting for this value is stated in the footnote of will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
IDT72261LA and 32,769 for the IDT72271LA.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
DATA OUTPUTS (Q0-Q8)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go
(Q0 - Q8) are data outputs for 9-bit wide data.
14
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
WEN
t
RSS
RSS
t
RSR
RSR
t
t
t
RSR
RSR
t
FWFT
FWFT/SI
LD
tRSS
tRSS
tRSS
t
RT
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4671 drw 08
Figure 5. Master Reset Timing
15
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
t
RSS
RSS
t
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4671 drw 09
Figure 6. Partial Reset Timing
16
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4671 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW3(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4671 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
18
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
19
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4671 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
3
1
2
4
RCLK
tENH
tENH
tENS
tENH
tRTS
REN
- Q
tA
tA
W2
(4)
Q0
n
Wx
Wx+1
W1
W3
tSKEW2
1
2
WCLK
tRTS
WEN
tENS
tENH
RT
OR
(5)
tREF
tREF
tPAE
PAE
tHF
HF
PAF
tPAF
4671 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4671 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 13 for the IDT72261LA and X = 14 for the IDT72271LA.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4671 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
t
LDH
ENH
LD
t
ENS
tENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT
REGISTER
PAE OFFSET
(MSB)
Q0 - Q7
4671 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
t
PAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4671 drw 19
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
In FWFT mode: D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
PAE
t
PAE
t
SKEW2
1
2
1
2
RCLK
REN
t
ENS
tENH
4671 drw 20
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D-1
[
+ 2]
words in FIFO(2)
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4671 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
suchproblems canbeavoidedbycreatingcompositeflags,thatis,ANDing
EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT
mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing IR of every FIFO.
Figure 21 demonstrates a width expansion using two IDT72261LA/
72271LA devices. D0 - D8 from each device form a 18-bit wide input bus
andQ0-Q8 fromeachdevice forma 18-bitwide outputbus. Anywordwidth
can be attained by adding additional IDT72261LA/72271LA devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF andFF functions inIDTStandardmode
andthe IR andORfunctions inFWFTmode. Becauseofvariations inskew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode,
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72261LA
72271LA
PROGRAMMABLE (PAE)
72261LA
72271LA
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4671 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
24
IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
tSKEW3 specificationisnotmetbetweenWCLKandtransferclock,orRCLK
The IDT72261LAcaneasilybe adaptedtoapplications requiringdepths and transfer clock, for the OR flag.
greater than 16,384 and 32,768 for the IDT72271LA with a 9-bit bus width.
The "ripple down" delay is only noticeable for the first word written to an
In FWFT mode, the FIFOs can be connected in series (the data outputs of empty depth expansion configuration. There will be no delay evident for
one FIFO connected to the data inputs of the next) with no external logic subsequent words written to the configuration.
necessary. The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO. Figure 22 configuration will "bubble up" from the last FIFO to the previous one until
shows a depth expansion using two IDT72261LA/72271LA devices. it finally moves into the first FIFO of the chain. Each time a free location
The first free location created by reading from a full depth expansion
Care should be taken to select FWFT mode during Master Reset for all is createdinone FIFOofthe chain, thatFIFO's IR line goes LOW, enabling
FIFOs in the depth expansion configuration. The first word written to an the preceding FIFO to write a word to fill it.
emptyconfigurationwillpassfromoneFIFOtothenext("rippledown")until
For a full expansion configuration, the amount of time it takes for IR of
it finally appears at the outputs of the last FIFO in the chain–no read the first FIFO in the chain to go LOW after a word has been read from the
operation is necessary but the RCLK of each FIFO must be free-running. last FIFO is the sum of the delays for each individual FIFO:
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakes forOR
(N – 1)*(3*transfer clock) + 2 TWCLK
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last where N is the number of FIFOs in the expansion and TWCLK is the WCLK
FIFO's outputs) after a word has been written to the first FIFO is the sum period. Note that extra cycles should be added for the possibility that the
of the delays for each individual FIFO:
tSKEW1 specificationisnotmetbetweenRCLKandtransferclock,orWCLK
and transfer clock, for the IR flag.
(N – 1)*(4*transfer clock) + 3*TRCLK
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly
where N is the number of FIFOs in the expansion and TRCLK is the RCLK as possible, to the end of the chain and free locations to the beginning of
period. Note that extra cycles should be added for the possibility that the the chain.
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
IDT
72261LA
72271LA
IDT
72261LA
72271LA
INPUT READY
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4671 drw 23
Figure 20. Block Diagram of 32,768 x 9 and 65,536 x 9 Depth Expansion
25
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
10
15
20
Commercial
Com’l & Ind’l
Com’l & Ind’l
Clock Cycle Time (tCLK
)
Speed in Nanoseconds
Low Power
LA
72261
72271
16,384 x 9 SuperSync FIFO
32,768 x 9 SuperSync FIFO
4671 drw 24
NOTE:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
DATASHEET DOCUMENT HISTORY
04/26/2001
pgs. 1, 5, 6 and 26.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for TECH SUPPORT:
408-330-1753
e-mail: FIFOhelp@idt.com
www.idt.com
26
3.3 VOLT CMOS SuperSync FIFO™
16,384 x 9
IDT72261LA
IDT72271LA
32,768 x9
ADDENDUM
DIFFERENCES BETWEEN THE IDT72261LA/72271LA AND IDT72261L/72271L
IDT has improved the performance of the IDT72261/72271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part
is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
Item
NEW PART
OLD PART
Comments
IDT72261LA
IDT72271LA
IDT72261L
IDT72271L
Pin #3
DC (Don’t Care) - There is
no restriction on WCLK and
RCLK. See note 1.
FS (Frequency Select)
In the LA part this pin must be tied
to either VCC or GND and must
not toggle after reset.
(4)
(3)
(4)
First Word Latency
60ns(2) + tREF + 1 TRCLK
tFWL = 10*Tf + 2TRCLK (ns) First word latency in the LA part
1
(IDT Standard Mode)
is a fixed value, independent of
the frequency of RCLK or WCLK.
(4)
(3)
(4)
First Word Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tFWL = 10*Tf + 3TRCLK (ns) First word latency in the LA part
2
is a fixed value, independent of
the frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(IDT Standard Mode)
60ns(2) + tREF + 1 TRCLK
tRTF1 = 14*Tf + 3TRCLK (ns) Retransmit latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tRTF2 = 14*Tf + 4TRCLK (ns) Retransmit latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
ICC1
75mA
20mA
150mA
15mA
Active supply current
Standby current
ICC2
Typical ICC1(5)
15 + 1.85*fS + 0.02*CL*fS(mA) Not Given
Typical ICC1 Current calculation
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is tSKEW3.
3. Tf is the period of the ‘selected clock’.
4. TRCLK is the cycle period of the read clock.
5. Typical ICC1 is based on VCC = 5V, tA = 25C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
27
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
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