IDT72275L15TFI [IDT]
FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64;
| 型号： | IDT72275L15TFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64 先进先出芯片 |
| 文件： | 总25页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SUPERSYNC FIFO™
32,768 x 18
PRELIMINARY
IDT72275
65,536 x 18
IDT72285
Integrated Device Technology, Inc.
• Independent Read and Write Clocks (permit reading and
writing simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)
FEATURES:
• Choose among the following memory organizations:
IDT72275
IDT72285
32,768 x 18
65,536 x 18
• High-performance submicron CMOS technology
• Pin-compatible with the IDT72255LA/72265LA SuperSync
FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
DESCRIPTION:
The IDT72275/72285 are exceptionally deep, high speed,
CMOS First-In-First-Out (FIFO) memories with clocked read
and write controls. These FIFOs offer numerous improve-
mentsoverpreviousSuperSyncFIFOs,includingthefollowing:
• The limitation of the frequency of one clock input with
respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed
and short.
• The first word data latency period, from the time the first
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
•
Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
FUNCTIONAL BLOCK DIAGRAM
D0 -D17
WCLK
OFFSET REGISTER
INPUT REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
FWFT/SI
RAM ARRAY
32,768 x 18
65,536 x 18
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
OUTPUT REGISTER
RESET
LOGIC
RCLK
4674 drw 01
Q0 -Q17
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1998
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
©1998 Integrated Device Technology, Inc
DSC-4674/-
1
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Continued)
There are two possible timing modes of operation with
thesedevices:IDTStandardmodeandFirstWordFallThrough
(FWFT) mode.
delay associated with the latency period found on previous
SuperSync devices has been eliminated on this SuperSync
family.)
In IDT Standard mode, the first word written to an empty
FIFO will not appear on the data output lines unless a specific
read operation is performed. A read operation, which consists
of activating REN and enabling a rising RCLK edge, will shift
the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is
clocked directly to the data output lines after three transitions
of the RCLK signal. A REN does not have to be asserted for
accessing the first word. However, subsequent words written
to the FIFO do require a LOW on REN for access. The state
of the FWFT/SI input during Master Reset determines the
timing mode in use.
SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other
applications that need to buffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) input
and a Write Enable (WEN) input. Data is written into the FIFO
on every rising edge of WCLK when WEN is asserted. The
output port is controlled by a Read Clock (RCLK) input and
ReadEnable(REN)input. DataisreadfromtheFIFOonevery
risingedgeofRCLKwhen RENisasserted. AnOutputEnable
(OE) input is provided for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals
may vary from 0 to fMAX with complete independence. There
are no restrictions on the frequency of the one clock input with
respect to the other.
For applications requiring more data storage capacity than
a single FIFO can provide, the FWFT timing mode permits
depth expansion by chaining FIFOs in series (i.e. the data
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q17
Q16
GND
Q15
Q14
2
3
DC
4
V
CC
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
5
6
V
CC
7
Q13
Q12
Q11
GND
Q10
Q9
8
9
10
11
12
13
14
15
16
Q8
Q7
D8
Q6
D7
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4674 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Continued)
outputs of one FIFO are connected to the corresponding data
inputs of the next). No external logic is required.
DuringMasterReset(MRS)thefollowingeventsoccur:The
read and write pointers are set to the first location of the FIFO.
The FWFT pin selects IDT Standard mode or FWFT mode.
The LD pin selects either a partial flag default setting of 127
with parallel programming or a partial flag default setting of
1,023withserialprogramming. Theflagsareupdatedaccord-
ing to the timing mode and default offsets selected.
The Partial Reset (PRS) also sets the read and write
pointers to the first location of the memory. However, the
timing mode, partial flag programming method, and default or
programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting
a device in mid-operation, when reprogramming partial flags
would be undesirable.
These FIFOs have five flag pins, EF/OR (Empty Flag or
Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full
Flag), PAE(Programmable Almost-Empty flag) and PAF(Pro-
grammable Almost-Full flag). The EF and FF functions are
selected in IDT Standard mode. The IRand ORfunctions are
selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.
PAEand PAFcan be programmed independently to switch
at any point in memory. (See Table I and Table II.) Program-
mable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, so that PAE can be set to
switch at 127 or 1,023 locations from the empty boundary and
thePAFthresholdcanbesetat127or1,023locationsfromthe
full boundary. These choices are made with the LD pin during
Master Reset.
The Retransmit function allows data to be reread from the
FIFO more than once. A LOW on the RTinput during a rising
RCLK edge initiates a retransmit operation by setting the read
pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an
operation, the chip will automatically power down. Once in the
power down state, the standby supply current consumption is
minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down
state.
For serial programming, SEN together with LD on each
rising edge of WCLK, are used to load the offset registers via
the Serial Input (SI). For parallel programming, WENtogether
with LD on each rising edge of WCLK, are used to load the
offset registers via Dn. REN together with LD on each rising
edge of RCLK can be used to read the offsets in parallel from
Qn regardless of whether serial or parallel offset loading has
been selected.
The IDT72275/72285 are fabricated using IDT’s high speed
submicron CMOS technology.
PARTIAL RESET
)
MASTER RESET
)
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE
)
WRITE ENABLE
LOAD
)
OUTPUT ENABLE
)
)
DATA OUT (Q
RETRANSMIT
EMPTY FLAG/OUTPUT READY
PROGRAMMABLE ALMOST-EMPTY
HALF FULL FLAG
0 - Qn)
DATA IN (D
0 - Dn)
IDT
72275
72285
)
SERIAL ENABL
)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
)
)
FULL FLAG/INPUT READY )
)
PROGRAMMABLE ALMOST-FULL
)
4674 drw 03
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO
3
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
Data Inputs
I/O
Description
Data inputs for a 18-bit bus.
I
I
Master Reset
MRSinitializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
OE
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN
LD
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023
and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
Programmable
Almost-Full Flag
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
whichisstoredintheEmptyOffsetregister. Therearetwopossibledefaultvalues
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
Q0–Q17
VCC
+5 Volt power supply pins.
GND
Ground
Ground pins.
4
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Min. Typ.
Max. Unit
VTERM
Terminal Voltage
with respect to GND
–0.5 to +7
V
VCC
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
GND
VIH
Supply Voltage
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
Input High Voltage
Input Low Voltage
2.0
—
0
—
—
—
—
0.8
70
V
(1)
VIL
V
DC Output Current
mA
TA
Operating Temperature
Commercial
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72275
IDT72285
Commercial
tCLK = 10, 15, 20 ns
Symbol
Parameter
Input Leakage Current
Min.
Max.
Unit
(1)
ILI
–1
–10
2.4
—
1
µA
µA
V
(2)
ILO
Output Leakage Current
10
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
0.4
V
(3,4,5)
ICC1
Active Power Supply Current
Standby Current
—
—
90
20
mA
mA
(3,6)
ICC2
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 20 + 1.8*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels),
data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
72275L15
72285L15
72275L10
72285L10
72275L20
72285L20
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Min.
Max.
100
6.5
—
Min.
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
Min.
—
2
Max.
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
20
8
Clock High Time
—
Clock Low Time
—
6
8
Data Setup Time
—
4
5
tDH
Data Hold Time
0
—
1
1
tENS
tENH
tLDS
tLDH
tRS
Enable Setup Time
Enable Hold Time
3
—
4
5
0
—
1
1
Load Setup Time
3
—
4
5
Load Hold Time
Reset Pulse Width(2)
0
—
1
1
10
10
10
—
0
—
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
Reset Setup Time
—
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
—
10
—
Retransmit Setup Time
Output Enable to Output in Low Z(3)
Output Enable to Output Valid
Output Enable to Output in High Z(3)
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
3
—
4
5
0
—
0
0
2
6
3
3
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
10
Read Clock to PAE
Clock to HF
tSKEW1
Skew time between RCLK and WCLK
for FF/IR
tSKEW2
tSKEW3
Skew time between RCLK and WCLK
for PAE and PAF
12
60
—
—
15
60
—
—
20
60
—
—
ns
ns
Skew time between RCLK and WCLK
for EF/OR
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
680Ω
AC TEST CONDITIONS
30pF*
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4674 drw 04
1.5V
1.5V
Figure 2. Output Load
* Includes jig and scope capacitances.
See Figure 1
6
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
D = 32,768 writes for the IDT72275 and 65,536 for the
IDT72285, respectively.
FUNCTIONAL DESCRIPTION
If the FIFO is full, the first read operation will causeFF to go
HIGH. Subsequent read operations will cause PAFand HF to
go HIGH at the conditions described in Table 1. If further read
operations occur, without write operations, PAE will go LOW
when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO
to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF
outputs are double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be
found in Figure 7, 8 and 11.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL
THROUGH (FWFT) MODE
The IDT72275/72285 support two different timing modes
of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is
determined during Master Reset, by the state of the FWFT/
SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO. It also uses the Full Flag function (FF) to
indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read
Enable (REN) and RCLK.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR
operate in the manner outlined in Table 2. To write data into
to the FIFO, WEN must be LOW. Data presented to the DATA
IN lines will be clocked into the FIFO on subsequent transi-
tions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue
to fill up the FIFO. PAE will go HIGH after n + 2 words have
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of
Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the HFwould
toggle to LOW once the 16,386th word for the IDT72275 and
32,770th word for the IDT72285, respectively was written into
the FIFO. Continuing to write data into the FIFO will cause the
PAFto go LOW. Again, if no reads are performed, thePAFwill
go LOW after (32,769-m) writes for the IDT72275 and
If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges, REN = LOW is not neces-
sary. Subsequent words must be accessed using the Read
Enable (REN) and RCLK.
Various signals, both input and output signals operate
differently depending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF
operate in the manner outlined in Table 1. To write data into to
the FIFO, Write Enable (WEN) must be LOW. Data presented to
the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is (65,537-m) writes for the IDT72285, where m is the full offset
value. Thedefaultsettingforthisvalueisstatedinthefootnote
of Table 2.
performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable
Almost-Empty flag (PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where n is the empty offset value.
ThedefaultsettingforthisvalueisstatedinthefootnoteofTable
1. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the Half-Full
flag (HF) would toggle to LOW once the 16,385th word for
IDT72275 and 32,769th word for IDT72285 respectively was
written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (PAF) to go
LOW. Again, if no reads are performed, the PAFwill go LOW
after (32,768-m) writes for the IDT72275 and (65,536-m)
writes for the IDT72285. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of
Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Input Ready (IR) flag will go HIGH,
inhibiting further write operations. If no reads are performed
after a reset, IR will go HIGH after D writes to the FIFO.
D = 32,769 writes for the IDT72275 and 65,537 writes for the
IDT72285, respectively. Note that the additional word in FWFT
mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR
flag to go LOW. Subsequent read operations will cause the
PAF and HF to go HIGH at the conditions described in Table
2. If further read operations occur, without write operations,
the PAE will go LOW when there are n + 1 words in the FIFO,
where n is the empty offset value. Continuing read operations
will cause the FIFO to become empty. When the last word has
been read from the FIFO, OR will go HIGH inhibiting further
read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinFWFTmode,theORflagoutputistriple
register-buffered, and the IR flag output is double register-
buffered.
When the FIFO is full, the Full Flag (FF) will go LOW,
inhibiting further write operations. If no reads are performed
after a reset, FF will go LOW after D writes to the FIFO.
Relevant timing diagrams for FWFT mode can be found in
Figure 9, 10 and 12.
7
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
PROGRAMMING FLAG OFFSETS
setsadefaultPAEoffsetvalueof07FH(athreshold127words
Full and Empty Flag offset values are user programmable. from the empty boundary), and a default PAF offset value of
The IDT72275/72285 has internal registers for these offsets. 07FH (a threshold 127 words from the full boundary). See
Default settings are stated in the footnotes of Table 1 and Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also
possible to read the current offset values. It is only possible to
read offset values via parallel read.
Figure 4, Programmable Flag Offset Programming Se-
quence, summarizes the control pins and sequence for both
serial and parallel programming modes. For a more detailed
description, see discussion that follows.
The offset registers may be programmed (and repro-
grammed) any time after Master Reset, regardless of whether
serial or parallel programming has been selected.
Table 2. Offset values can be programmed into the FIFO in
one of two ways; serial or parallel loading method. The
selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of theLD input determines
whether serial or parallel flag offset programming is enabled.
A HIGH on LD during Master Reset selects serial loading of
offset values and in addition, sets a default PAE offset value
of 3FFH (a threshold 1,023 words from the empty boundary),
and a default PAF offset value of 3FFH (a threshold 1,023
words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition,
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
72275
72285
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
0
0
1 to n (1)
1 to n(1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m)(2) to 32,767
32,768
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m)(2) to 65,535
65,536
L
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE II –– STATUS FLAGS FOR FWFT MODE
72275
72285
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
1 to n+1(1)
Number of
Words in
(n+2) to 32,769
(n+2) to 16,385
16,386 to (32,769-(m+1))(2)
H
H
H
H
32,770 to (65,537-(m+1)) (2)
1)
FIFO(
(32,769-m)
(65,537-m)
L
to 32,768
to 65,536
32,769
65,537
L
L
4674 drw 05
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
72275 (32,768 x 18–BIT)
72285 (65,536 x 18–BIT)
15 14
17
17
0
17
17
16 15
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
EMPTY OFFSET REGISTER
DEFAULT VALUE
007FH if
is LOW at Master Reset,
is HIGH at Master Reset
007FH if
is LOW at Master Reset,
is HIGH at Master Reset
03FFH i
03FFH if
0
0
15 14
16 15
FULL OFFSET REGISTER
DEFAULT VALUE
FULL OFFSET REGISTER
DEFAULT VALUE
007FH i
03FFH if
is LOW at Master Reset,
is HIGH at Master Reset
007FH i
03FFH if
is LOW at Master Reset,
is HIGH at Master Reset
4674 drw 06
Figure 3. Offset Register Location and Default Values
72275
WCLK
RCLK
X
72285
Parallel write to registers:
Empty Offset
0
0
0
1
1
0
1
1
0
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
X
Serial shift into registers:
30 bits for the 72275
0
1
1
X
32 bits for the 72285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
1
1
0
1
1
X
X
X
No Operation
Write Memory
X
0
X
X
X
X
1
1
X
1
Read Memory
1
X
X
No Operation
4674 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
Offset (LSB) register. A Partial Reset has no effect on the
position of these pointers.
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as de-
WriteoperationstotheFIFOareallowedbeforeandduring
the parallel programming sequence. In this case, the pro-
gramming of all offset registers does not have to occur at one
time. One,twoormoreoffsetregisterscanbewrittenandthen
bybringingLD HIGH, writeoperationscanberedirectedtothe
FIFO memory. When LD is set LOW again, andWEN is LOW,
the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LDLOW and
toggling WEN.
Note that the status of a partial flag (PAEor PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
theregister(s)pertainingtothatflag.Measuringfromtherising
WCLK edge that achieves the above criteria; PAFwill be valid
after two more rising WCLK edges plus tPAF, PAEwill be valid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset regis-
ters can be read on the Q0-Qn pins when LD is set LOW and
REN is set LOW. Data are read via Qn from the Empty Offset
Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read
from the Full Offset Register. The third transition of RCLK
reads, once again, from the Empty Offset Register. See
Figure15, ParallelReadofProgrammableFlagRegisters, for
the timing diagram for this mode.
s
cribedabove, thenprogrammingofPAEand PAFvaluescan
be achieved by using a combination of the LD, SEN, WCLK
and SI input pins. Programming PAE and PAF proceeds as
follows: when LD and SEN are set LOW, data on the SI input
are written, one bit for each WCLK rising edge, starting with
the Empty Offset LSB and ending with the Full Offset MSB. A
total of 30 bits for the IDT72275 and 32 bits for the IDT72285.
See Figure 13, Serial Loading of Programmable Flag Regis-
ters, for the timing diagram for this mode.
Using the serial method, individual registers cannot be
programmed selectively. PAE and PAF can show a valid
status only after the complete set of bits (for all offset regis-
ters) has been entered. The registers can be reprogrammed
as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the
registers can occur.
WriteoperationstotheFIFOareallowedbeforeandduring
the serial programming sequence. In this case, the program-
ming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memoryviaDn bytoggling WEN. WhenWENisbroughtHIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If an interruption
ofserialprogrammingisdesired, itissufficienteithertosetLD
LOW and deactivate SEN or to set SEN LOW and deactivate
LD. Once LDand SENarebothrestoredtoaLOWlevel,serial
offset programming continues.
From the time serial programming has begun, neither
partial flag will be valid until the full set of bits required to fill all
the offset registers has been written. Measuring from the
risingWCLKedgethatachievestheabovecriteria;PAFwillbe
valid after two more rising WCLK edges plus tPAF, PAEwill be
valid after the next two rising RCLK edges plus tPAE plus
tSKEW2.
It is permissible to interrupt the offset register read se-
quence with reads or writes to the FIFO. The interruption is
accomplished by deasserting REN, LD, or both together.
WhenREN andLD are restored to a LOW level, reading of the
offset registers continues where it left off. It should be noted,
and care should be taken from the fact that when a parallel
read of the flag offsets is performed, the data word that was
present on the output lines Qn will be overwritten.
It is not possible to read the flag offset values in a serial
mode.
Parallel reading of the offset registers is always permitted
regardless of which timing mode (IDT Standard or FWFT
modes) has been selected.
PARALLEL MODE
If Parallel Programming mode has been selected, as
describedabove, thenprogrammingofPAEandPAFvaluescan
beachievedbyusingacombinationoftheLD, WCLK,WEN and
Dn input pins. Programming PAEand PAF proceeds as follows:
when LD and WEN are set LOW, data on the inputs Dn are
written into the Empty Offset Register on the first LOW-to-HIGH
transitionofWCLK.UponthesecondLOW-to-HIGHtransitionof
WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset
Register. See Figure 14, Parallel Loading of Programmable
Flag Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated
write offset register pointer. The act of reading offsets em-
ploys a dedicated read offset register pointer. The two point-
ers operate independently; however, a read and a write
should not be performed simultaneously to the offset regis-
ters. A Master Reset initializes both pointers to the Empty
RETRANSMIT OPERATION
The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
Retransmit setup is initiated by holding RT LOW during a
rising RCLK edge. REN and WEN must be HIGH before
bringing RT LOW. At least one word, but no more than D - 2
words should have been written into the FIFO between Reset
(MasterorPartial)andthetimeofRetransmitsetup. D = 32,768
for the IDT72275 and D = 65,536 for the IDT72285. In FWFT
mode, D = 32,769 for the IDT72275 and D= 65,537 for the
IDT72285.
If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit setup by setting EF LOW. The
10
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
change in level will only be noticeable if EFwas HIGH before outputs. Since FWFT mode is selected, the first word
setup. Duringthisperiod,theinternalreadpointerisinitialized appears on the outputs, no LOW on REN is necessary.
to the first location of the RAM array.
Reading all subsequent words requires a LOW on REN to
When EF goes HIGH, Retransmit setup is complete and enable the rising edge of RCLK. See Figure 12, Retransmit
read operations may begin starting with the first location in Timing (FWFT Mode), for the relevant timing diagram.
memory. Since IDT Standard mode is selected, every word
For either IDT Standard mode or FWFT mode, updating
read including the first word following Retransmit setup re- of the PAE, HF and PAF flags begin with the rising edge of
quires a LOW on REN to enable the rising edge of RCLK. See RCLK that RT is setup. PAE is synchronized to RCLK, thus
Figure 11, Retransmit Timing (IDT Standard Mode), for the onthesecondrisingedgeofRCLKafterRTissetup, thePAE
relevant timing diagram.
flag will be updated. HF is asynchronous, thus the rising
IfFWFTmodeisselected, theFIFOwillmarkthebeginning edge of RCLK that RT is setup will update HF. PAF is
of the Retransmit setup by setting OR HIGH. During this synchronized to WCLK, thus the second rising edge of
period, the internal read pointer is set to the first location of the WCLK that occurs tSKEW after the rising edge of RCLK that
RAM array.
When ORgoes LOW, Retransmit setup is complete; at the
same time, the contents of the first location appear on the
RT is setup will update PAF. RT is synchronized to RCLK.
11
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
RETRANSMIT (RT)
SIGNAL DESCRIPTION
INPUTS:
The Retransmit operation allows data that has already been
read to be accessed again. There are two stages: first, a setup
procedure that resets the read pointer to the first location of
memory, thentheactualretransmit, whichconsistsofreadingout
the memory contents, starting at the beginning of the memory.
Retransmit setup is initiated by holding RT LOW during a
rising RCLK edge. REN and WEN must be HIGH before
bringing RT LOW.
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input
is taken to a LOW state. This operation sets the internal read
and write pointers to the first location of the RAM array. PAE
will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT
Standard mode, along with EFand FFare selected. EF will go
LOW and FF will go HIGH. If FWFT is HIGH, then the First
Word Fall Through mode (FWFT), along with IR and OR, are
selected. OR will go HIGH and IR will go LOW.
If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit setup by setting EF LOW. The
change in level will only be noticeable if EFwas HIGH before
setup. Duringthisperiod,theinternalreadpointerisinitialized
to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard mode is selected, every word
read including the first word following Retransmit setup re-
quires a LOW on REN to enable the rising edge of RCLK. See
If LD is LOW during Master Reset, then PAE is assigned a
threshold 127 words from the empty boundary and PAF is Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
If LD is HIGH during Master Reset, then PAEis assigned
a threshold 1,023 words from the empty boundary and PAFis
assigned a threshold 1,023 words from the full boundary;
1,023 words corresponds to an offset value of 3FFH. Follow-
ing Master Reset, serial loading of the offsets is permitted, but
not parallel loading.
Parallel reading of the registers is always permitted. (See
section describing the LD pin for further details.)
During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing
diagram.
If FWFT mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting ORHIGH. During this period, the
internal read pointer is set to the first location of the RAM array.
When ORgoes LOW, Retransmit setup is complete; at the
same time, the contents of the first location appear on the
outputs. SinceFWFTmodeisselected, thefirstwordappears
on the outputs, no LOW on REN is necessary. Reading all
subsequentwordsrequiresaLOWonRENtoenabletherising
edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the
FWFT/SI input determines whether the device will operate in IDT
Standard mode or First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
presentintheFIFOmemory. ItalsousestheFullFlagfunction
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directlytoQn afterthreeRCLKrisingedges,REN=LOWisnot
necessary. Subsequent words must be accessed using the
Read Enable (REN) and RCLK.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is
taken to a LOW state. As in the case of the Master Reset, the
internal read and write pointers are set to the first location of the
RAM array,PAE goes LOW, PAFgoes HIGH, and HFgoes HIGH.
Whichever mode is active at the time of Partial Reset, IDT
Standard mode or First Word Fall Through, that mode will
remainselected. IftheIDTStandardmodeisactive, thenFFwill
go HIGH and EF will go LOW. If the First Word Fall Through
mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset regis-
ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes. PRS
is asynchronous.
After Master Reset, FWFT/SI acts as a serial input for
loading PAEand PAFoffsetsintotheprogrammableregisters.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming partial flag offset
settings may not be convenient.
See Figure 6, Partial Reset Timing, for the relevant timing Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
diagram.
12
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
WRITE CLOCK (WCLK)
to HIGH transition after the last word has been read from the
FIFO, OutputReady(OR)willgoHIGHwithatrueread(RCLK
with REN = LOW), inhibiting further read operations. REN is
ignored when the FIFO is empty.
A write cycle is initiated on the rising edge of the WCLK
input. Data setup and hold times must be met with respect to
the LOW-to-HIGH transition of the WCLK. It is permissible to
stop the WCLK. Note that while WCLK is idle, the FF/IR, PAF
and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read
Clocks can either be independent or coincident.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial program-
ming of the offset registers. The serial programming method
must be selected during Master Reset. SEN is always used
in conjunction with LD. When these lines are both LOW, data
at the SI input can be loaded into the program register one bit
for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains
theprevioussettingsandnooffsetsareloaded. SENfunctions
the same way in both IDT Standard and FWFT modes.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the
FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially
and independently of any ongoing read operation.
When WEN is HIGH, no new data is written in the RAM
array on each WCLK cycle.
Topreventdataoverflow intheIDTStandardmode, FFwill
go LOW, inhibiting further write operations. Upon the comple-
tion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF is updated by two WCLK cycles + tSKEW after
the RCLK cycle.
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output
buffers receive data from the output register. When OEis HIGH,
the output data bus (Qn) goes into a high impedance state.
To prevent data overflow in the FWFT mode, IR will go
HIGH,inhibitingfurtherwriteoperations. Uponthecompletion
of a valid read cycle, IR will go LOW allowing a write to occur.
The IR flag is updated by two WCLK cycles + tSKEW after the
valid RCLK cycle.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of
the LD input determines one of two default offset values (127 or
1,023)forthePAEandPAFflags,alongwiththemethodbywhich
these offset registers can be programmed, parallel or serial.
After Master Reset, LD enables write operations to and read
operations from the offset registers. Only the offset loading
method currently selected can be used to write to the registers.
Offsetregisterscanbereadonlyinparallel. ALOWonLD during
Master Reset selects a default PAE offset value of 07FH (a
threshold 127 words from the empty boundary), a default PAF
offset value of 07FH (a threshold 127 words from the full
boundary), and parallel loading of other offset values. A HIGH
on LD during Master Reset selects a default PAEoffset value of
3FFH (a threshold 1,023 words from the empty boundary), a
default PAFoffset value of 3FFH (a threshold 1,023 words from
the full boundary), and serial loading of other offset values.
After Master Reset, the LD pin is used to activate the
programming process of the flag offset values PAE and PAF.
Pulling LD LOW will begin a serial loading or parallel load or
readoftheseoffsetvalues. SeeFigure4, ProgrammableFlag
Offset Programming Sequence.
WENis ignored when the FIFO is full in either FWFT or IDT
Standard mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of
the RCLK input. It is permissible to stop the RCLK. Note that
while RCLK is idle, the EF/OR, PAE and HF flags will not be
updated. (Note that RCLK is only capable of updating the HF
flag to HIGH.) The Write and Read Clocks can be indepen-
dent or coincident.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM
array into the output register on the rising edge of every RCLK
cycle if the device is not empty.
When the REN input is HIGH, the output register holds the
previous data and no new data is loaded into the output register.
The data outputs Q0-Qn maintain the previous data value.
OUTPUTS:
In the IDT Standard mode, every word accessed at Qn,
including the first word written to an empty FIFO, must be
requestedusingREN. Whenthelastwordhasbeenreadfrom
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EFwill go HIGH allowing a read to
occur. The EF flag is updated by two RCLK cycles + tSKEW
after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, on the third valid LOW
to HIGH transition of RCLK + tSKEW after the first write. REN
doesnotneedtobeassertedLOW. Inordertoaccessallother
words, a read must be executed using REN. The RCLK LOW
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full
Flag (FF) function is selected. When the FIFO is full, FF will go
LOW, inhibiting further write operations. When FF is HIGH, the
FIFO is not full. If no reads are performed after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 32,768 for the IDT72275 and 65,536 for the IDT72285).
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard
Mode), for the relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected.
IR goes LOW when memory space is available for writing in
data. When there is no longer any free space left, IR goes
13
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
HIGH, inhibiting further write operations. If no reads are where m is the full offset value. The default setting for this
performed after a reset (either MRS or PRS), IR will go HIGH value is stated in the footnote of Table 2.
after D writes to the FIFO (D = 32,769 for the IDT72275 and
See Figure 16, Programmable Almost-Full Flag Timing
65,537 for the IDT72285) See Figure 9, Write Timing (FWFT (IDT Standard and FWFT Mode), for the relevant timing
Mode), for the relevant timing information.
information.
The IR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
PAFis synchronous and updated on the rising edge of WCLK.
register. Thus, in FWFT mode, the total number of writes PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
necessary to deassertIRis one greater than needed to assert
FF in IDT Standard mode.
The Programmable Almost-Empty flag (PAE) will go LOW
when the FIFO reaches the almost-empty condition. In IDT
FF/IRissynchronousandupdatedontherisingedgeofWCLK. Standard mode, PAE will go LOW when there are n words or
FF/IR are double register-buffered outputs.
less in the FIFO. The offset “n” is the empty offset value. The
default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1
words or less in the FIFO. The default setting for this value is
stated in the footnote of Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing
information.
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the
EmptyFlag(EF)functionisselected. WhentheFIFOisempty,
EF will go LOW, inhibiting further read operations. When EF
is HIGH, the FIFO is not empty. See Figure 8, Read Cycle,
Empty Flag and First Word Latency Timing (IDT Standard
Mode), for the relevant timing information.
PAEis synchronous and updated on the rising edge of RCLK.
In FWFT mode, the Output Ready (OR) function is selected.
ORgoes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs. ORstays LOW after
the RCLK LOW to HIGH transition that shifts the last word from
theFIFOmemorytotheoutputs. ORgoesHIGHonlywithatrue
read (RCLK with REN = LOW). The previous data stays at the
outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read
Timing (FWFT Mode), for the relevant timing information.
EF/OR is synchronous and updated on the rising edge of
RCLK.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK
edge that fills the FIFO beyond half-full setsHFLOW. The flag
remains LOW until the difference between the write and read
pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this
condition sets HF HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset
(MRS or PRS), HF will go LOW after (D/2 + 1) writes to the
FIFO, where D = 32,768 for the IDT72275 and 65,536 for the
IDT72285.
In FWFT mode, if no reads are performed after reset (MRS
or PRS), HF will go LOW after (D-1/2 + 2) writes to the FIFO,
where D = 32,769 for the IDT72275 and 65,537 for the
IDT72285.
See Figure 18, Half-Full Flag Timing (IDT Standard and
FWFT Modes), for the relevant timing information. Because
HF is updated by both RCLK and WCLK, it is considered
asynchronous.
In IDT Standard mode, EF is a double register-buffered
output. In FWFT mode, ORis a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when
the FIFO reaches the almost-full condition. In IDT Standard
mode, if no reads are performed after reset (MRS), PAF will go
LOW after (D - m) words are written to the FIFO. The PAF will
goLOWafter(32,768-m)writesfortheIDT72275and (65,536-m)
writes for the IDT72285. The offset “m” is the full offset value.
ThedefaultsettingforthisvalueisstatedinthefootnoteofTable
1.
DATA OUTPUTS (Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
In FWFT mode, the PAF will go LOW after (32,769-m)
writesfortheIDT72275and(65,537-m)writesfortheIDT72285,
14
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
tRS
tRSS
tRSR
tRSR
tRSS
tRSR
tFWFT
FWFT/SI
tRSS
tRSR
tRSS
tRSS
t
RSF
If FWFT = HIGH
If FWFT = LOW
If FWFT = LOW
= HIGH
= LOW
= HIGH
t
RSF
If FWFT = HIGH= LOW
tRSF
tRSF
,
tRSF
= HIGH
= LOW
Q0 - Qn
4674 drw 08
Figure 5. Master Reset Timing
15
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
tRS
tRSS
tRSR
t
RSS
tRSR
t
t
RSS
RSS
If FWFT = HIGH
If FWFT = LOW
If FWFT = LOW
If FWFT = HIGH
= HIGH
= LOW
= HIGH
= LOW
t
RSF
tRSF
t
RSF
tRSF
tRSF
= HIGH
= LOW
Q0 - Qn
4674 drw 09
Figure 6. Partial Reset Timing
16
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
t
CLK
tCLKH
NOWRITE
NOWRITE
tCLKL
2
1
WCLK
1
2
(1)
t
SKEW1(1)
t
SKEW1
t
DS
tDH
t
DS
tDH
DX
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
RCLK
t
ENS
tENH
t
ENS
tENH
t
A
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4674 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FFwill go high (after one WCLK cycle pus tWFF).
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one
extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
t
CLKL
1
2
RCLK
t
ENH
t
ENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
t
A
tA
tA
D0
Q
0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
tOLZ
t
OHZ
tOE
(1)
SKEW3
t
WCLK
tENH
tENH
t
ENS
tENS
tDS
tDH
t
DHS
t
DS
D0
- Dn
D0
D1
4674 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF).
If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EFdeassertion may be delayed one extra RCLK cycle.
2. LD = HIGH
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
18
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
19
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
1
2
RCLK
tENS
tENH
tENS
tENH
tRTS
t
A
tA
tA
(3)
(3)
Q0 - Qn
Wx
Wx+1
W1
W
2
t
SKEW2
1
2
WCLK
tRTS
tENS
tENH
(5)
t
REF
tREF
t
PAE
tHF
tPAF
4674 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the
Retransmit setup procedure. D = 32,768 for IDT72275 and 65,536 for IDT72285.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
3
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
t
RTS
t
A
t
A
(4)
Q0 - Qn
Wx
W
x+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
t
RTS
t
ENS
tENH
(5)
REF
t
t
REF
t
PAE
t
HF
t
PAF
4674 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IRwill be LOW throughout the
Retransmit setup procedure. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
tENH
t
ENS
tENH
tLDH
tLDH
tLDS
t
DS
tDH
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4674 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 14 for the IDT72275 and X = 15 for the IDT72285.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
t
CLK
t
CLKH
t
CLKL
WCLK
t
LDH
t
LDS
t
LDH
tENH
t
ENH
t
ENS
t
DS
tDH
t
DH
PAE
OFFSET
PAF
OFFSET
D0
- D15
4674 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
LDH
t
ENS
tENH
t
ENH
t
A
t
A
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
Q
0
- Q15
4674 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
WCLK
1
2
2
1
t
ENS
tENH
tPAF
tPAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
2)
in FIFO(
(3)
SKEW2
t
RCLK
t
ENH
t
ENS
4674 drw 19
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee thatPAF will go HIGH (after one WCLK cycle plus tPAF). If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAFdeassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
t
CLKH
t
CLKL
WCLK
t
ENH
tENS
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
PAE
tPAE
t
SKEW2
1
2
1
2
RCLK
tENS
tENH
4674 drw 20
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the
time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
t
HF
D/2 + 1 words in FIFO(1)
+ 2
words in FIFO(2)
,
D/2 words in FIFO(1)
+ 1
words in FIFO(2)
,
D/2 words in FIFO(1)
+ 1
words in FIFO(2)
,
[
]
[
]
]
t
HF
RCLK
t
ENS
4674 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
IDT Standard mode, such problems can be avoided by
creating composite flags, that is, ANDing EF of every FIFO,
and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO,
and separately ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two
IDT72275/72285 devices. D0 - D17 from each device form a
36-bit wide input bus and Q0-Q17 from each device form a 36-
bit wide output bus. Any word width can be attained by adding
additional IDT72275/72285 devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting to-
getherthecontrolsignalsofmultipledevices. Statusflagscan
be detected from any one device. The exceptions are the EF
and FF functions in IDT Standard mode and the IR and OR
functions in FWFT mode. Because of variations in skew
betweenRCLKandWCLK,itispossiblefor EF/FFdeassertion
and IR/OR assertion to vary by one cycle between FIFOs. In
PARTIAL RESE
MASTER RESET
)
)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMI
)
Dm+1 - Dn
n
m + n
m
D
0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE
)
WRITE ENABLE
LOAD
FULL FLAG/INPUT READ
FULL FLAG/INPUT READ
)
)
OUTPUT ENABLE
PROGRAMMABLE
)
IDT
72275
72285
IDT
72275
72285
)
)
#1
EMPTY FLAG/OUTPUT READY
EMPTY FLAG/OUTPUT READ
) #1
) #2
(1)
(1)
GATE
) #2
GATE
PROGRAMMABLE
HALF-FULL FLAG
)
)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4674 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO,
that device's OR line goes LOW, enabling a write to the next
FIFO in line.
For an empty expansion configuration, the amount of time
ittakesfor ORofthelastFIFOinthechaintogoLOW(i.e. valid
data to appear on the last FIFO's outputs) after a word has
been written to the first FIFO is the sum of the delays for each
individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE
ONLY)
The IDT72275 can easily be adapted to applications requir-
ing depths greater than 32,768 and 65,536 for the IDT72285
with an 18-bit bus width. In FWFT mode, the FIFOs can be
connected in series (the data outputs of one FIFO connected
tothedatainputsofthenext)withnoexternallogicnecessary.
The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO.
Figure 24 shows a depth expansion using two IDT72275/
72285 devices.
Care should be taken to select FWFT mode during Master
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK
is the RCLK period. Note that extra cycles should be added
for the possibility that the tSKEW3 specification is not met
24
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
FWFT/SI
•
TRANSFER CLOCK
RCLK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WCLK
RCLK
•
IDT
72275
72285
IDT
72275
72285
INPUT READY
OUTPUT READY
OUTPUT ENABLE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4674 drw 23
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
between WCLK and transfer clock, or RCLK and transfer has been read from the last FIFO is the sum of the delays for
clock, for the OR flag.
each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK
The "ripple down" delay is only noticeable for the first word
writtentoanemptydepthexpansionconfiguration. Therewill
be no delay evident for subsequent words written to the
configuration.
The first free location created by reading from a full depth is the WCLK period. Note that extra cycles should be added
expansion configuration will "bubble up" from the last FIFO to for the possibility that the tSKEW1 specification is not met
the previous one until it finally moves into the first FIFO of the between RCLK and transfer clock, or WCLK and transfer
chain. Each time a free location is created in one FIFO of the clock, for the IR flag.
chain, that FIFO's IR line goes LOW, enabling the preceding
FIFO to write a word to fill it.
The Transfer Clock line should be tied to either WCLK or
RCLK, whichever is faster. Both these actions result in data
For a full expansion configuration, the amount of time it moving, asquicklyaspossible, totheendofthechainandfree
takesforIRofthefirstFIFOinthechaintogoLOWafteraword locations to the beginning of the chain.
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
Commercial (0°C to +70°C)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
10
15
20
Clock Cycle Time (tCLK
)
Commercial
Low Power
Speed in Nanoseconds
L
72275
72285
32,768 x 18 SuperSyncFIFO
65,536 x 18 SuperSyncFIFO
4674 drw 24
NOTE:
1. Industrial temperature range is available by special order.
25
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