IDT723612L20PQFI9 [IDT]
FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132;
| 型号： | IDT723612L20PQFI9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132 先进先出芯片 |
| 文件： | 总25页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncBiFIFOTM
64 x 36 x 2
IDT723612
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Available in 132-pin plastic quad flat package (PQF) or space-
saving 120-pin thin quad flat package (TQFP)
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage capacity
each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
TheIDT723612isamonolithichigh-speed,low-powerCMOSbi-directional
clockedFIFOmemory.Itsupportsclockfrequenciesupto67MHzandhasread
accesstimesasfastas10ns.Twoindependent64x36dual-portSRAMFIFOs
on board the chip buffer data in opposite directions. Each FIFO has flags to
indicateemptyandfullconditionsandtwoprogrammableflags(Almost-Fulland
Almost-Empty) to indicate when a selected number of words is stored in
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
FUNCTIONALBLOCKDIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
PEFB
MBA
Parity
Gen/Check
Mail 1
Register
PGB
RAM
36
ARRAY
64 x 36
RST
Device
Control
ODD/
EVEN
Read
Pointer
Write
Pointer
EFB
AEB
FFA
AFA
Status Flag
Logic
FIFO1
36
FS0
FS1
Programmable Flag
Offset Register
B0 - B36
A
0
- A35
FIFO2
FFB
AFB
EFA
AEA
Status Flag
Logic
Write
Pointer
Read
Pointer
36
RAM
ARRAY
64 x 36
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
CLKB
Port-B
Control
Logic
CSB
W/RB
ENB
MBB
3136 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MARCH 2002
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3136/1
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
memory.CommunicationbetweeneachportcanbypasstheFIFOsviatwo independent of one another and can be asynchronous or coincident. The
36-bitmailboxregisters.Eachmailboxregisterhasaflagtosignalwhennew enablesforeachportarearrangedtoprovideasimplebi-directionalinterface
mailhas beenstored.Parityis checkedpassivelyoneachportandmaybe betweenmicroprocessorsand/orbuseswithsynchronouscontrol.
ignoredifnotdesired.Paritygenerationcanbe selectedfordata readfrom
eachport.Twoormoredevices canbeusedinparalleltocreatewiderdata two-stagesynchronizedtotheportclockthatwritesdatatoitsarray.TheEmpty
paths. Flag(EFA,EFB)andAlmost-Empty(AEA,AEB)flagofaFIFOaretwostage
ThisdeviceisaclockedFIFO,whichmeanseachportemploysasynchronous synchronizedtotheportclockthatreads datafromits array.
The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are
interface. All data transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each port are
The IDT723612 is characterized for operation from 0°C to 70°C.
PINCONFIGURATIONS
GND
AEA
EFA
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
GND
AEB
EFB
A0
B0
*
A
1
B
1
A
2
B
2
GND
GND
A
3
B
3
A
4
B
4
A
5
B
5
A
6
CC
B
6
V
VCC
A
7
B
7
A
8
B
8
A
9
B
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
94
GND
A
A
A
A
A
A
15
16
17
18
19
20
93
B
B
B
B
B
B
15
16
17
18
19
20
92
91
90
89
88
GND
87
GND
A21
A22
A23
86
B21
B22
B23
85
84
3136 drw02
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP(2) (PQ132-1, ORDER CODE: PQF)
TOP VIEW
NOTE:
1. NC - No internal connection
2. Uses Yamaichi socket IC51-1324-828
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
PINCONFIGURATIONS(CONTINUED)
A
A
A
23
22
21
1
B
22
21
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
B
3
GND
GND
4
B
B
B
B
B
B
B
B
B
B
B
20
19
18
17
16
15
14
13
12
11
10
A
A
A
A
A
A
A
A
A
A
A
20
19
18
17
16
15
14
13
12
11
10
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
9
A
A
9
8
7
B
8
B
7
A
VCC
V
CC
B
6
A
6
5
4
3
B
5
A
B
4
A
B
3
A
GND
GND
B
2
A
2
1
0
B
1
A
B
0
A
EFB
AEB
AFB
EFA
AEA
3136 drw03
NOTE:
1. NC - No internal connection
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
PINDESCRIPTION
Symbol
A0-A35
AEA
Name
I/O
Description
Port-AData
I/O
36-bitbidirectionaldataportforsideA.
Almost-EmptyFlag
O
(Port A)
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA. ItisLOWwhenthenumberofwordsin
the FIFO2is less thanorequaltothe value inthe offsetregister, X.
AEB
AFA
AFB
Port-BAlmost-Empty
Flag
O
(Port B)
ProgrammableAlmost-FullflagsynchronizedtoCLKB. Itis LOWwhenthe numberofwords in
FIFO1is less thanorequaltothe value inthe offsetregister, X.
Port-AAlmost-Full
Flag
O
(Port A)
ProgrammableAlmost-FullflagsynchronizedtoCLKA. ItisLOWwhenthe numberofempty
locations inFIFO1is less thanorequaltothe value inthe offsetregister, X.
Port-BAlmost-Empty
Flag
O
(Port B)
ProgrammableAlmost-FullflagsynchronizedtoCLKB. ItisLOWwhenthenumberofempty
locations inFIFO2is less thanorequaltothe value inthe offsetregister, X.
B0-B35
CLKA
Port-BData.
Port-A Clock
I/O
I
36-bitbidirectionaldataportforsideB.
CLKAisacontinuousclockthatsynchronizesalldatatransfersthroughport-Aandcanbe
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the
LOW-to-HIGHtransitionofCLKA.
CLKB
Port-BClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughport-Bandcanbe
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-
to-HIGHtransitionofCLKB.
CSA
CSB
EFA
Port-AChipSelect
Port-BChipSelect
Port-AEmptyFlag
I
I
CSA mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A.
The A0-A35outputs are inthe high-impedance state whenCSA is HIGH.
B mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B.
The B0-B35outputs are inthe high-impedance state whenCSB is HIGH.
EFAissynchronizedtotheLOW-to-HIGHtransitionofCLKA. WhenEFA is LOW,FIFO2is
empty, andreads fromits memoryare disabled. Data canbe readfromFIFO2tothe output
register whenEFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by
thesecondLOW-to-HIGHtransitionofCLKAafterdataisloadedintoemptyFIFO2memory.
O
(Port A)
EFB
Port-BEmptyFlag
O
(Port B)
EFB is synchronizedtotheLOW-to-HIGHtransitionofCLKB. WhenEFB is LOW,theFIFO1is
empty, andreads fromits memoryare disabled. Data canbe readfromFIFO1tothe output
register whenEFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
secondLOW-to-HIGHtransitionofCLKBafterdataisloadedintoemptyFIFO1memory.
ENA
ENB
FFA
Port-AEnable
Port-BEnable
Port-A Full Flag
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B.
O
(Port A)
FFA is synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenFFA is LOW, FIFO1is full,
and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
HIGHbythesecondLOW-to-HIGHtransitionofCLKAafterreset.
FFB
Port-B Full Flag
O
(Port B)
FFBis synchronizedtotheLOW-to-HIGHtransitionofCLKB. WhenFFBis LOW,FIFO2is full,
and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGHbythesecondLOW-to-HIGHtransitionofCLKBafterreset.
FS1, FS0 Flag-OffsetSelects
I
I
TheLOW-to-HIGHtransitionofRST latches thevalues ofFS0andFS1,whichselects oneoffour
presetvaluesfortheAlmost-Fullflagandalmost-Emptyflag.
MBA
MBB
MBF1
Port-AMailbox
Select
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0-A35outputs areactive,aHIGHlevelonMBAselects datafromthemail2registerforoutput,and
aLOWlevelselectsFIFO2output registerdataforoutput.
Port-BMailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutput,and
aLOWlevelselectsFIFO1outputregisterdataforoutput.
Mail1RegisterFlag
O
MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.
Writes tothe mail1registerare inhibitedwhileMBF1 is setLOW. MBF1 is setHIGHbya LOW-
to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH
whenthe device is reset.
MBF2
Mail2RegisterFlag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.
Writes tothe mail2registerare inhibitedwhile MBF2 is setLOW. MBF2 is setHIGHbya LOW-to-
HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH
whenthe device is reset.
4
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/O
Description
ODD/
EVEN
Odd/EvenParity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVENalsoselects thetypeofparitygeneratedforeachportifparity
generation is enabled for a read operation.
PEFA
PEFB
Port-A Parity Error
Flag
O
Whenanybyte appliedtoterminals A0-A35fails parity,PEFA is LOW. Bytes are organizedas
(Port A) A0-A8,A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyteservingas
the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
paritytrees usedtocheckthe A0-A35inputs are sharedbythe mail2registertogenerate parityif
paritygenerationis selectedbyPGA. Therefore, ifa mail2readwith paritygenerationis setupby
having W/RA LOW, MBA HIGH, andPGA HIGH, the PEFA flag is forcedHIGHregardless ofthe
A0-A35inputs.
Port-B Parity Error
Flag
O
Whenanybyte appliedtoterminals B0-B35fails parity,PEFB is LOW. Bytes are organizedas
(Port B) B0-B8,B9-B17,B18-B26,B27-B35withthemostsignificantbitofeachbyteservingastheparitybit.
The type ofparitycheckedis determinedbythe state ofthe ODD/EVENinput. The paritytrees used
tocheckthe B0-B35inputs are sharedbythe mail1registertogenerate parityifparitygenerationis
selectedbyPGB. Therefore, ifa mail1readwithparitygenerationis setupbyhavingW/RBLOW,
MBBHIGH, andPGBHIGH, the PEFB flagis forcedHIGHregardless ofthe state ofthe B0-B35
inputs.
PGA
PGB
RST
Port-AParity
Port-BParity
Reset
I
I
I
Parity is generated for data reads from port A when PGA is HIGH. Generation The type of parity
generatedis selectedbythe state ofthe ODD/EVEN input. Bytes are organizedas A0-A8, A9-A17,
A18-A26,andA27-A35. Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selectedbythe state ofthe ODD/EVEN input. Bytes are organizedas B0-B8, B9-B17, B18-B26,
andB27-B35. Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.
Toresetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsof
CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and
theEFA, EFB, AEA,AEB,FFA, andFFBflags LOW. The LOW-to-HIGHtransitionofRST latches
thestatusoftheFS1andFS0inputstoselectAlmost-FullandAlmost-Emptyflagoffset.
W/RA
W/RB
Port-AWrite/Read
Select
I
I
A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGH
transitionofCLKA. TheA0-A35outputs areinthehigh-impedancestatewhenW/RAis HIGH.
A HIGHselects a write operationanda LOWselects a readoperationonportBfora LOW-to-HIGH
transitionofCLKB. TheB0-B35outputs areinthehigh-impedancestatewhenW/RBis HIGH.
Port-BWrite/Read
Select
5
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE
RANGE (UNLESS OTHERWISE NOTED)(2)
Symbol
Rating
Commercial
–0.5 to 7
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
VO(2)
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±500
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device
at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
SupplyVoltage
Min.
4.5
2
Max. Unit
5.5
–
V
V
HIGHLevelInputVoltage
LOW-LevelInputVoltage
VIL
–
0.8
–4
8
V
IOH
HIGH-LevelOutputCurrent
LOW-LevelOutputCurrent
OperatingFree-airTemperature
–
mA
mA
°C
IOL
–
TA
0
70
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
FREE-AIRTEMPERATURERANGE(UNLESSOTHERWISENOTED)
Parameter
VOH
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min.
2.4
—
Typ.(1)
—
—
—
—
—
4
Max.
—
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
VCC 5.5V,
VI=0,
VOL
0.5
±50
±50
1
V
ILI
VI = VCC or 0
VO = VCC or 0
IO = 0 mA,
—
µA
µA
mA
pF
pF
ILO
ICC(2)
—
VI = VCC or GND
—
CIN
f = 1 MHz
—
—
COUT
VO = 0,
f = 1 MHZ
—
8
—
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see following page.
6
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
400
VCC = 5.5V
350
300
fdata = 1/2 fS
TA= 25°C
CL = 0 pF
VCC = 5.0V
250
200
VCC = 4.5V
150
100
50
0
0
10
20
30
40
Clock Frequency
50
MHz
60
70
80
3136 drw04
fS
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
CALCULATINGPOWERDISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723612 with CLKA and CLKB set
tofS.Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnectedtonormalize
thegraphtoazero-capacitanceload.Oncethecapacitanceloadperdata-outputchannelisknown,thepowerdissipationcanbecalculatedwiththeequation
below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PD) of the IDT723612 may be calculated by:
PD = VCC x ICC(f) + Σ(CL x VCC x (VOH - VOL) x fo)
where:
CL
fo
VOH
VOL
=
=
=
=
outputcapacitanceload
switching frequency of an output
output HIGH level voltage
output LOW level voltage
When no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.290 mA/MHz
7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
DCELECTRICALCHARACTERISTICSOVERRECOMMENDEDRANGESOF
SUPPLYVOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Commercial
Com’l & Ind’l(1)
IDT723612L20
IDT723612L15
Symbol
fS
Parameter
Min.
–
Max.
Min.
–
Max.
50
–
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
66.7
–
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
15
6
20
8
Pulse Duration, CLKA and CLKB HIGH
–
–
ns
Pulse Duration, CLKAandCLKBLOW
6
–
8
–
ns
SetupTime, A0-A35before CLKA↑ andB0-B35before CLKB↑
SetupTime,CSA,W/RAbeforeCLKA↑;CSB,W/RBbeforeCLKB↑
SetupTime,ENA,beforeCLKA↑;ENBbeforeCLKB↑
SetupTime,MBAbeforeCLKA↑:MBBbeforeCLKB↑
4
–
5
–
ns
tENS1
tENS2
tENS3
tPGS
6
–
6
–
ns
4
–
5
–
ns
4
–
5
–
ns
SetupTime, ODD/EVEN andPGAbefore CLKA↑;ODD/EVENandPGB
4
–
5
–
ns
beforeCLKB↑(2)
tRSTS
tFSS
SetupTime,RST LOWbeforeCLKA↑ orCLKB↑(3)
Setup Time, FS0/FS1 before RST HIGH
HoldTime,A0-A35afterCLKA↑ andB0-B35afterCLKB↑
HoldTime,CSAW/RAafterCLKA↑;CSB,W/RBafterCLKB↑
HoldTime,ENA,afterCLKA↑;ENBafterCLKB↑
HoldTime,MBAafterCLKA↑;MBBafterCLKB↑
5
5
–
–
–
–
–
–
–
6
6
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
tDH
2.5
2
2.5
2
tENH1
tENH2
tENH3
tPGH
2.5
1
2.5
1
HoldTime, ODD/EVEN andPGAafterCLKA↑;ODD/EVENandPGB
1
1
afterCLKB↑(2)
tRSTH
HoldTime,RST LOWafterCLKA↑ orCLKB↑(3)
Hold Time, FS0 and FS1 after RST HIGH
Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB
Skew Time, between CLKA↑ and CLKB↑ For AEA, AEB, AFA, and AFB
5
4
–
–
–
–
6
4
–
–
–
–
ns
ns
ns
ns
tFSH
tSKEW1(4)
tSKEW2(4)
8
8
14
16
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Commercial
IDT723612L15 IDT723612L20
Com’l & Ind’l(1)
Symbol
tA
Parameter
Min.
2
Max.
10
10
10
10
10
9
Min.
2
Max.
12
Unit
ns
AccessTime,CLKA↑ toA0-A35andCLKB↑ toB0-B35
Propagation Delay Time, CLKA↑ to FFAand CLKB↑ toFFB
Propagation Delay Time, CLKA↑ to EFA and and CLKB↑ to EFB
PropagationDelayTime, CLKA↑ toAEA andCLKB↑ toAEB
Propagation Delay Time, CLKA↑ toAFA and CLKB↑ to AFB
tWFF
tREF
tPAE
tPAF
tPMF
2
2
12
ns
2
2
12
ns
2
2
12
ns
2
2
12
ns
Propagation Delay Time, CLKA↑ toMBF1 LOW orMBF2 HIGH and CLKB↑ to
MBF2 LOW or MBF1 HIGH
1
1
12
ns
tPMR
tMDV
tPDPE
tPOPE
Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3)
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
3
1
3
3
2
11
11
10
11
11
3
1
3
3
2
13
11.5
11
ns
ns
ns
ns
ns
12
(4)
tPOPB
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and
(B8, B17, B26, B35)
12
tPEPE
PropagationDelayTime, W/RA,CSA, ENA, MBAorPGAtoPEFA;W/RB,CSB,
ENB,MBB,PGBtoPEFB
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to parity bits( A8, A17, A26, A35);
W/RB, CSB, bits (B8, B17, B26, B35) ENB, MBB or PGB to parity
Propagation Delay Time, RST to (AEA, AEB) LOW and (AFA, AFB, MBF1, MBF2)
HIGH
1
3
1
2
1
11
12
15
10
8
1
3
1
2
1
12
13
20
12
9
ns
ns
ns
ns
ns
(4)
tPEPB
tRSF
tEN
tDIS
Enable Time, CSA andW/RALOWtoA0-A35active and CSB LOWandW/RBHIGH
toB0-B35active
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH
orW/RBLOWtoB0-B35athighimpedance.
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3 Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when reading data from a mail register.
9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Emptyregisters(X)withthevaluesselectedbytheFlagSelect(FS0,
FS1) inputs. The values that can be loaded into the registers are shown in
Table 1.
SIGNALDESCRIPTIONS
RESET
The IDT723612is resetbytakingthe Reset(RST)inputLOWforatleast
four port-A clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH
transitions.TheResetinputcanswitchasynchronouslytotheclocks.Adevice
resetinitializes theinternalreadandwritepointers ofeachFIFOandforces
theFullFlags(FFA,FFB)LOW,theEmptyFlags(EFA,EFB)LOW,theAlmost-
Emptyflags(AEA,AEB)LOWandtheAlmost-Fullflags(AFA,AFB)HIGH.A
resetalsoforcestheMailboxFlags(MBF1,MBF2)HIGH.Afterareset,FFA
issetHIGHaftertwoLOW-to-HIGHtransitionsofCLKAandFFBissetHIGH
aftertwoLOW-to-HIGHtransitionsofCLKB.Thedevicemustberesetafter
powerupbefore data is writtentoits memory.
FIFO WRITE/READ OPERATION
The state of port-A data A0-A35 outputs is controlled by the port-A Chip
Select(CSA)andtheport-AWrite/Readselect(W/RA).TheA0-A35outputs
areinthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-
A35 outputs are active when bothCSA andW/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA
isLOW,andFFAisHIGH.DataisreadfromFIFO2totheA0-A35outputsby
aLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENAis
HIGH, MBA is LOW, and EFA is HIGH (see Table 2).
Theport-Bcontrolsignals areidenticaltothoseofportA.Thestateofthe
port-Bdata(B0-B35)outputsiscontrolledbytheport-BChipSelect(CSB)and
the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high-
impedancestatewheneitherCSBorW/RBisHIGH.TheB0-B35outputsare
active when bothCSB andW/RB are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhen CSBis LOW,W/RBisHIGH,ENBisHIGH,MBBis
LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by
aLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBis
HIGH, MBB is LOW, and EFB is HIGH (see Table 3).
TABLE 1 FLAG PROGRAMMING
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTYFLAG
OFFSET REGISTER (X)
H
H
L
L
H
L
H
L
↑
↑
↑
↑
16
12
8
4
TABLE 2 PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
A0-A35 Outputs
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
Active,FIFO2OutputRegister
Active,FIFO2OutputRegister
Active,Mail2Register
Port Functions
X
X
↑
None
None
H
L
X
L
H
H
L
FIFO1Write
Mail1Write
L
H
H
H
↑
L
L
L
L
X
↑
None
L
L
H
L
FIFO2 Read
None
L
L
L
H
X
↑
L
L
H
H
Active,Mail2Register
Mail2 Read (Set MBF2 HIGH)
TABLE 3 PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
B0-B35 Outputs
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
Active,FIFO1OutputRegister
Active,FIFO1OutputRegister
Active,Mail1Register
Port Functions
X
X
↑
None
None
H
L
X
L
H
H
L
FIFO2Write
Mail2Write
L
H
H
H
↑
L
L
L
L
X
↑
None
L
L
H
L
FIFO1 read
None
L
L
L
H
X
↑
L
L
H
H
Active,Mail1Register
Mail1 Read (Set MBF1 HIGH)
10
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
EachtimeawordiswrittentoaFIFO,thewritepointerisincremented.The
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite statemachinethatcontrolsaFullFlagmonitorsawrite-pointerandreadpointer
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata comparatorthatindicateswhentheFIFOSRAMstatusisfull,full-1,orfull-2.
outputs.IfaportenableisLOWduringaclockcycle,theportchipselectand From the time a word is read from a FIFO, the previous memory location is
write/readselectmaychangestatesduringthesetupandholdtimewindow readytobewritteninaminimumofthreecyclesoftheFullFlagsynchronizing
ofthecycle.
clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag
synchronizingclockhaveelapsedsincethenextmemorywritelocationhas
beenread.ThesecondLOW-to-HIGHtransitionontheFullFlagsynchroni-
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughtwoflip-flopstages.This zationclockafterthereadsetstheFullFlagHIGHandthedatacanbewritten
is done to improve flag reliability by reducing the probability of metastable inthefollowingclockcycle.
eventsontheoutputwhenCLKAandCLKBoperateasynchronouslytoone
ALOW-to-HIGHtransitionona FullFlagsynchronizingclockbegins the
another. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB, firstsynchronizationcycleofareadiftheclocktransitionoccursattimetSKEW1
FFB,andAFBaresynchronizedtoCLKB.Tables4and5showtherelationship orgreateraftertheread.Otherwise,thesubsequentclockcyclecanbethefirst
of each port flag to FIFO1 and FIFO2.
synchronizationcycle.
EMPTY FLAGS (EFA, EFB)
ALMOST EMPTY FLAGS (AEA, AEB)
The Empty Flag of a FIFO is synchronized to the port clock that reads
The Almost-Empty flag of a FIFO is synchronized to the port clock that
data fromits array. Whenthe EmptyFlagis HIGH, newdata canbe readto readsdatafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflag
theFIFOoutputregister.WhentheEmptyFlagisLOW,theFIFOisemptyand monitorsawrite-pointercomparatorthatindicateswhentheFIFOSRAMstatus
attemptedFIFOreads areignored.
isalmost-empty,almost-empty+1,oralmost-empty+2.Thealmost-emptystate
The read pointer of a FIFO is incremented each time a new word is isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
clockedtotheoutputregister.ThestatemachinethatcontrolsanEmptyFlag Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see
monitorsawrite-pointerandread-pointercomparatorthatindicateswhenthe Resetabove).AnAlmost-EmptyflagisLOWwhentheFIFOcontainsXorless
FIFOSRAMstatusisempty,empty+1,orempty+2.AwordwrittentoaFIFO wordsinmemoryandisHIGHwhentheFIFOcontains(X+1)ormorewords.
canbereadtotheFIFOoutputregisterinaminimumofthreecyclesoftheEmpty
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclocks
Flagsynchronizingclock.Therefore,anEmptyFlagisLOWifawordinmemory arerequiredafteraFIFOwritefortheAlmost-Emptyflagtoreflectthenewlevel
isthenextdatatobesenttotheFIFOoutputregisterandtwocyclesoftheport offill. Therefore, the Almost-Emptyflagofa FIFOcontaining(X+1)ormore
clockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword wordsremainsLOWiftwocyclesofthesynchronizingclockhavenotelapsed
waswritten.TheEmptyFlagoftheFIFOissetHIGHbythesecondLOW-to- sincethewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflag
HIGHtransitionofthesynchronizingclock,andthenewdatawordcanberead issetHIGHbythesecondLOW-to-HIGHtransitionofthesynchronizingclock
totheFIFOoutputregisterinthefollowingcycle.
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
ALOW-to-HIGHtransitiononanEmptyFlagsynchronizingclockbeginsthe transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-
firstsynchronizationcycleofawriteiftheclocktransitionoccursattimetSKEW1 nizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFO
orgreaterafterthewrite.Otherwise,thesubsequentclockcyclecanbethefirst to(X+1)words.Otherwise,thesubsequentsynchronizingclockcyclecanbe
synchronizationcycle.
the first synchronizationcycle (see Figure 7 and 8).
ALMOST FULL FLAGS (AFA, AFB)
FULL FLAG (FFA, FFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write-pointer and read-pointer comparator that indicates when the FIFO
TheFullFlagofaFIFOissynchronizedtotheportclockthatwritesdatato
itsarray.WhentheFullFlagisHIGH,amemorylocationisfreeintheSRAM
toreceivenewdata.NomemorylocationsarefreewhentheFullFlagisLOW
andattemptedwrites tothe FIFOare ignored.
TABLE 4 FIFO1 FLAG OPERATION
TABLE 5 FIFO2 FLAG OPERATION
Synchronized
to CLKB
Synchronized
to CLKA
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words
in the FIFO1(1)
Number of Words
in the FIFO1(1)
EFB
L
AEB
L
AFA
H
FFA
H
EFA
L
AEA
L
AFB
H
FFB
H
0
1 to X
0
1 to X
H
L
H
H
H
L
H
H
(X+1) to [64–(X+1)]
(64–X) to 63
64
H
H
H
H
(X+1) to [64–(X+1)]
(64–X) to 63
64
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
L
H
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.
11
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
SRAMstatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate
isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see
Resetabove).AnAlmost-FullflagisLOWwhentheFIFOcontains(64-X)or
more words in memory and is HIGH when the FIFO contains [64-(X+1)] or
less words.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
requiredafteraFIFOreadfortheAlmost-Fullflagtoreflectthenewleveloffill.
Therefore,theAlmost-FullflagofaFIFOcontaining[64-(X+1)]orlesswords
remainsLOWiftwocyclesofthesynchronizingclockhavenotelapsedsince
thereadthatreducedthenumberofwordsinmemoryto[64-(X+1)].AnAlmost-
FullflagissetHIGHbythesecondLOW-to-HIGHtransitionofthesynchronizing
clockaftertheFIFOreadthatreducesthenumberofwordsinmemoryto[64-
(X+1)].AsecondLOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizing
clockbeginsthefirstsynchronizationcycleifitoccursattimetSKEW2orgreater
after the read that reduces the number of words in memory to [64-(X+1)].
Otherwise,thesubsequentsynchronizingclockcyclecanbethefirstsynchro-
nization cycle (see Figure 14 and 15).
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26,andA27-A35withthemostsignificantbitofeachbyteusedastheparity
bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35,
withthemostsignificantbitofeachbyteusedastheparitybit.Whenodd/even
parityisselected,aportparityerrorflag(PEFA,PEFB)isLOWifanybyteon
the porthas anodd/evennumberofLOWlevels appliedtothe bits.
ThefourparitytreesusedtochecktheA0-A35inputsaresharedbythemail2
registerwhenparitygenerationis selectedforport-Areads (PGA=HIGH).
Whenaport-Areadfromthemail2registerwithparitygenerationisselected
withW/RALOW,CSALOW,ENAHIGH,MBAHIGH,andPGAHIGH,theport-
A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to
theA0-A35inputs.Likewise,theparitytreesusedtochecktheB0-B35inputs
aresharedbythemail1registerwhenparitygenerationis selectedforport-
Breads(PGB=HIGH).Whenaport-Breadfromthemail1registerwithparity
generationisselectedwithW/RBLOW,CSB LOW,ENBHIGH,MBBHIGH,
andPGBHIGH,theport-Bparityerrorflag(PEFB)is heldHIGHregardless
ofthelevels appliedtotheB0-B35inputs.
PARITYGENERATION
MAILBOX REGISTERS
AHIGHlevelonthe port-AParityGenerate select(PGA)orport-BParity
Generate select (PGB) enables the IDT723612 to generate parity bits for
portreadsfromaFIFOormailboxregister.Port-AbytesarearrangedasA0-
A8,A9-A17,A18-26,andA27-A35,withthemostsignificantbitofeachbyte
usedastheparitybit.Port-BbytesarearrangedasB0-B8,B9-B17,B18-B26,
andB27-B35,withthemostsignificantbitofeachbyteusedastheparitybit.
AwritetoaFIFOormailregisterstoresthelevelsappliedtoallthirty-sixinputs
regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs.When
dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
EVENselect.Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
writtentothemostsignificantbitsofeachbyteasthewordisreadtothedata
outputs.
Paritybits forFIFOdata are generatedafterthe data is readfromSRAM
andbeforethedataiswrittentotheoutputregister.Therefore,theport-Aparity
generateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)havesetup
and hold time constraints to the port-A Clock (CLKA) and the port-B Parity
Generateselect(PGB)andODD/EVENhavesetupandhold-timeconstraints
totheport-BClock(CLKB).Thesetimingconstraintsonlyapplyforarisingclock
edge used to read a new word to the FIFO output register.
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue.TheMailbox
select(MBA, MBB)inputs choose betweena mailregisteranda FIFOfora
portdatatransferoperation.ALOW-to-HIGHtransitiononCLKAwritesA0-
A35datatothemail1registerwhenaport-AwriteisselectedbyCSA,W/RA,
andENAandMBAHIGH.ALOW-to-HIGHtransitiononCLKBwritesB0-B35
datatothemail2registerwhenaport-BwriteisselectedbyCSB,W/RB,and
ENBandMBBisHIGH.Writingdatatoamailregistersetsthecorresponding
flag(MBF1orMBF2)LOW.Attemptedwritestoamailregisterareignoredwhile
themailflagisLOW.
Whenaport'sdataoutputsareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailbox-selectinput(MBA,MBB)isLOW
andfromthemailregisterwhentheportmailbox-selectinputisHIGH.TheMail1
registerFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen
aport-BreadisselectedbyCSB,W/RB,andENBandMBBisHIGH.TheMail2
registerFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhen
port-AreadisselectedbyCSA,W/RA,andENAandMBAisHIGH.Thedata
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister.
Thecircuitusedtogenerateparityforthemail1dataissharedbytheport-
Bbus(B0-B35)tocheckparityandthecircuitusedtogenerateparityforthe
mail2dataissharedbytheport-Abus(A0-A35)tocheckparity.Theshared
paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
whentheportWrite/Readselect(W/RA,W/RB)inputisLOW,theportmailselect
(MBA,MBB)inputis HIGH,ChipSelect(CSA, CSB)is LOW,Enable (ENA,
ENB) is HIGH, and port Parity Generate select (PGA, PGB) is HIGH.
Generatingparityformailregisterdatadoes notchangethecontents ofthe
register.
PARITY CHECKING
The port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four
paritytreestochecktheparityofincoming(oroutgoing)data.Aparityfailure
onone ormore bytes ofthe inputbus is reportedbya LOWlevelonthe port
ParityErrorFlag(PEFA,PEFB).Oddorevenparitycheckingcanbeselected,
and the Parity Error Fags can be ignored if this feature is not desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Evenparity(ODD/EVEN)selectinput.Aparityerrorononeormorebytesof
aportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
12
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST
0,1
FS1,FS0
t
WFF
t
t
WFF
REF
t
FFA
EFA
FFB
EFB
t
WFF
WFF
t
REF
PAE
PAF
t
AEA
AFA
t
t
RSF
MBF1,
MBF2
t
PAE
PAF
AEB
AFB
t
3136 drw05
Figure 2. Device Reset Loading the X Register with the Value of Eight
13
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
tCLK
tCLKL
tCLKH
CLKA
FFA
CSA
HIGH
t
ENS1
t
ENH1
tENS1
t
ENH1
W/RA
t
ENS3
t
ENH3
ENH2
MBA
tENS2
tENS2
t
ENS2
tENH2
tENH2
t
ENA
tDS
tDH
(1)
W2(1)
A0 - A35
No Operation
W1
ODD/
EVEN
tPDPE
tPDPE
PEFA
Valid
Valid
3136 drw06
NOTE:
1. Written to FIFO1.
Figure 3. Port-A Write Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKB
FFB
CSB
HIGH
t
ENS1
t
ENH1
ENH1
tENS1
t
W/RB
MBB
t
ENS3
ENS2
t
ENH3
tENS2
t
t
ENH2
tENH2
tENS2
tENH2
ENB
tDS
tDH
(1)
W2(1)
B0 - B35
No Operation
W1
ODD/
EVEN
tPDPE
tPDPE
PEFB
Valid
Valid
3136 drw07
NOTE:
1. Written to FIFO2.
Figure 4. Port-B Write Cycle Timing for FIFO2
14
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKB
EFB
CSB
HIGH
W/RB
tENS2
MBB
tENH2
tENH2
tENH2
tENS2
tENS2
ENB
No Operation
Word 2(1)
t
MDV
EN
t
A
tDIS
tA
t
(1)
Previous Data (1)
B0 - B35
Word 1
tPGH
tPGH
tPGS
tPGS
PGB,
ODD/
EVEN
3136 drw08
NOTE:
1. Read from FIFO1.
Figure 5. Port-B Read Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKA
EFA
CSA
HIGH
W/RA
tENS2
MBA
ENA
t
ENH2
tENH2
t
ENH2
t
ENS2
tENS2
No Operation
Word 2(1)
t
MDV
tA
tDIS
t
A
tEN
(1)
Previous Data (1)
A0 - A35
Word 1
tPGH
tPGH
tPGS
tPGS
PGA,
ODD/
EVEN
3136 drw09
NOTE:
1. Read from FIFO2.
Figure 6. Port-A Read Cycle Timing for FIFO2
15
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
t
CLK
t
CLKL
tCLKH
CLKA
CSA LOW
WRA HIGH
tENH3
tENS3
MBA
tENS2
tENH2
ENA
FFA
HIGH
tDS
tDH
A0 - A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKB
t
REF
t
REF
EFB
CSB
FIFO1 Empty
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
tA
B0 -B35
W1
3136 drw10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 7. EFB Flag Timing and First Data Read when FIFO1 is Empty
16
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
t
CLK
t
CLKH
t
CLKL
CLKB
CSB LOW
W/RB HIGH
tENS3
tENH3
MBB
ENB
tENS2
tENH2
FFB
HIGH
tDS
tDH
B0 - B35
W1
(1)
SKEW1
t
CLK
t
CLKH
t
t
CLKL
1
2
CLKA
t
REF
t
REF
EFA
FIFO2 Empty
CSA LOW
LOW
LOW
W/RA
MBA
tENS2
tENH2
ENA
tA
A0 -A35
W1
3136 drw11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 8. EFA Flag Timing and First Data Read when FIFO2 is Empty
17
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
tA
ENB
EFB
HIGH
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0 - B35
(1)
tSKEW1
tCLK
tCLKH
tCLKL
1
2
CLKA
tWFF
tWFF
FFA
CSA
FIFO1 Full
LOW
HIGH
WRA
tENS3
tENS2
tDS
tENH3
MBA
tENH2
tDH
ENA
A0 - A35
3136 drw12
To FIFO1
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 9. FFA Flag Timing and First Available Write when FIFO1 is Full
18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
LOW
W/RA
MBA
tENS2
tENH2
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0 - A35
(1)
SKEW1
tCLK
t
tCLKH
tCLKL
1
2
CLKB
t
WFF
t
WFF
FFB
CSB
FIFO2 Full
LOW
HIGH
W/RB
tENS3
tENH3
MBB
tENS2
tENH2
ENB
tDH
tDS
B0 - B35
3136 drw13
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 10. FFB Flag Timing and First Available Write when FIFO2 is Full
CLKA
tENS2
tENH2
ENA
(1)
SKEW2
t
1
2
CLKB
t
PAE
tPAE
X Word in FIFO1
(X+1) Words in FIFO1
AEB
tENH2
tENS2
ENB
3136 drw14
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 11. Timing for AEB when FIFO1 is Almost Empty
19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
CLKB
tENS2
tENH2
ENB
(1)
SKEW2
t
1
2
CLKA
t
PAE
t
PAE
AEA
(X+1) Words in FIFO2
ENS2
X Words in FIFO2
t
tENH2
ENA
3136 drw15
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 12. Timing for AEA when FIFO2 is Almost Empty
(1)
SKEW2
t
1
2
CLKA
ENA
tENH2
tENS2
t
PAF
t
PAF
(64-X) Words in FIFO1
AFA
CLKB
ENB
[64-(X+1)] Words in FIFO1
tENS2
tENH2
3136 drw16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 13. Timing for AFA when FIFO1 is Almost Full
(1)
SKEW2
t
1
2
CLKB
ENB
t
ENH2
PAF
tENS2
t
t
PAF
(64-X) Words in FIFO2
AFB
[64-(X+1)] Words in FIFO2
CLKA
tENS2
tENH2
ENA
3136 drw17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 14. Timing for AFB when FIFO2 is Almost Full
20
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
CLKA
tENS1
tENH1
CSA
W/RA
MBA
tENS1
tENS1
tENS1
tENH1
tENH1
tENH1
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH2
tENS2
t
MDV
tEN
t
PMR
tDIS
W1 (Remains valid in Mail1 Register after read)
B0 - B35
3136 drw18
FIFO1 Output Register
NOTE:
1. Port-B parity generation off (PGB = LOW).
Figure 15. Timing for Mail1 Register and MBF1 Flag
21
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
W1 (Remains valid in Mail2 Register after read)
NOTE:
1. Port-A parity generation off (PGA = LOW).
Figure 16. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
tPOPE
tPOPE
t
PEPE
PEFA
Valid
Valid
Valid
Valid
3136 drw20
NOTE:
1. ENA is HIGH, and CSA is LOW.
Figure 17. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing
22
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
ODD/
EVEN
W/RB
MBB
PGB
t
PEPE
tPOPE
tPEPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
3136 drw21
NOTE:
1. ENB is HIGH, and CSB is LOW.
Figure 18. ODD/EVEN W/RB, MBB, and PGB to PEFB Timing
ODD/
EVEN
LOW
CSA
W/RA
MBA
PGA
t
PEPB
tEN
tMDV
tPOPB
tPEPB
A8, A17,
A26, A35
Generated Parity
Generated Parity
Mail2 Data
3136 drw22
Mail2
Data
NOTE:
1. ENA is HIGH.
Figure 19. Parity Generation Timing when Reading from Mail2 Register
ODD/
EVEN
LOW
CSB
W/RB
MBB
PGB
t
PEPB
tEN
t
MDV
tPOPB
tPEPB
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
3136 drw23
NOTE:
1. ENB is HIGH.
Figure 20. Parity Generation Timing when Reading from Mail1 Register
23
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 k Ω
From Output
Under Test
30 pF (1)
680 Ω
LOAD CIRCUIT
3 V
3 V
1.5 V
High-Level
Input
Timing
Input
1.5 V
1.5 V
1.5 V
GND
3 V
GND
tS
th
tW
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
≈
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
≈
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3136 drw24
NOTE:
1. Includes probe and jig capacitance.
Figure 21. Load Circuit and Voltage Waveforms
24
ORDERINGINFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (40°C to +85°C)
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Com’l & Ind’l
Speed in Nanoseconds
Low Power
L
723612 64 x 36 x 2 SyncBiFIFO
3136 drw25
NOTE:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
03/05/2002
pgs. 1, 8, 9 and 25.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for TECH SUPPORT:
e-mail:FIFOhelp@idt.com
Phone: (408) 330-1753
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
25
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