IDT723622L15PQF [IDT]
CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2; CMOS SyncBiFIFOO 256 ×36× 2 512 ×36× 2 1024 ×36× 2
| 型号： | IDT723622L15PQF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 |
| 文件： | 总26页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT723622
IDT723632
IDT723642
CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2
Integrated Device Technology, Inc.
FEATURES:
• Fast access times of 11ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power 0.8-Micron Advanced CMOS technology
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs buffering data in oppo-
site directions
• Memory storage capacity:
IDT723622–256 x 36 x 2
IDT723632–512 x 36 x 2
DESCRIPTION:
TheIDT723622/723632/723642isamonolithic,high-speed,
low-power, CMOS Bidirectional SyncFIFO (clocked) memory
which supports clock frequencies up to 67MHz and have read
access times as fast as 11ns. Two independent 256/512/
1024x36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. Each FIFO has flags to indicate
empty and full conditions and two programable flags (almost
IDT723642–1024 x 36 x 2
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 67MHz
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
Port-A
Control
Logic
CSA
W/RA
ENA
256 x 36
512 x 36
1024 x 36
SRAM
MBA
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
IRA
AFA
ORB
AEB
FIFO 1
Programmable Flag
Offset Registers
FS0
FS1
B0 - B35
A0 - A35
9
FIFO 2
ORA
AEA
Status Flag
Logic
IRB
AFB
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
256 x 36
512 x 36
1024 x 36
SRAM
CLKB
CSB
Port-B
Control
Logic
W/RB
ENB
MBB
Mail 2
Register
MBF2
3022 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 1996
1996 Integrated Device Technology, Inc.
DSC-3022/3
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.22
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
asynchronous or coincident. The enables for each port are
arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB)
flags of a FIFO are two-stage synchronized to the port clock
that writes data into its array. The Output Ready (ORA, ORB)
and Almost-Empty (AEA, AEB) flags of a FIFO are two-stage
synchronized to the port clock that reads data from its array.
Offset values for the Almost-Full and Almost-Empty flags of
both FIFOs can be programmed from Port A.
DESCRIPTION (CONTINUED)
Full and almost Empty) to indicate when a selected number of
words is stored in memory. Communication between each
port may bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has
been stored. Two or more devices may be used in parallel to
create wider data paths.
TheIDT723622/723632/723642isasynchronous(clocked)
FIFO, meaning each port employs a synchronous interface.
All data transfers through a port are gated to the LOW-to-
HIGH transition of a port clock by enable signals. The clocks
for each port are independent of one another and can be
The IDT723622/723632/723642 is characterized for op-
eration from 0°C to 70°C.
PIN CONFIGURATION
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
NC
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PQ132-1
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
84
3022 drw 02
PQF Package
TOP VIEW
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
5.22
2
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PN120-1
3022 drw 03
TQFP
TOP VIEW
5.22
3
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
A0-A35
AEA
Name
I/O
I/0
O
Description
36-bit bidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW
Port-A Data
Port-A Almost
-Empty Flag
(Port A) when the number of words in FIF02 is less than or equal to the value in the
almost-empty A offset register, X2.
AEB
AFA
AFB
Port-B Almost
-Empty Flag
O
Programmable almost-empty flag synchronzed to CLKB. It is LOW
(Port B) when the number of words in FIF01 is less than or equal to the value in the
almost-empty B offset register, X1.
Port-A Almost
-Full Flag
O
Programmable almost-full flag synchronized to CLKA. It is LOW when
(Port A) the number of empty locations in FIF01 is less than or equal to the value in
the almost-full A offset register, Y1.
Port-B Almost
-Full Flag
O
Programmable almost-full flag synchronized to CLKB. It is LOW when
(Port B) the number of empty locations in FIF02 is less than or equal to the value in
the almost-full B offset register, Y2.
B0 - B35 Port-B Data
I/O
I
36-bit bidirectional data port for side B.
CLKA
CLKB
CSA
Port-A Clock
CLKA is a continuous clock that synchronizes all data transfers through port A
and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA
are all synchronized to the LOW-to-HIGH transition of CLKA.
Port-B Clock
I
I
CLKB is a continuous clock that synchronizes all data transfers through port B
and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB
are synchronized to the LOW-to-HIGH transition of CLKB.
Port-A Chip
Select
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or
write on port A. The AO-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port-B Chip
Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port B. The BO- B35 outputs are in the high-impedance state
when CSB is HIGH.
ENA
ENB
Port-A Enable
Port-B Enable
I
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port B.
FS1,
FS0
Flag Offset
Selects
The LOW-to-HIGH transition of a FlFO’s reset input latches the values of FSO
and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one
of the three preset values is selected as the offset for the FlFOs almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO
and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to
FIFO1 almost empty offsets for both FlFOs.
IRA
IRB
MBA
Input-Ready
Flag
O
IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is
(Port A) LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW
when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition
of CLKA after reset.
Input-Ready
Flag
O
IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is
(Port B) LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when
FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of
CLKB after reset.
Port-A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a port-A read or
write operation. When the AO-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output and a LOW level selects FIF02
output-register data for output.
5.22
4
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONT.)
Symbol
Name
I/O
Description
MBB
Port-B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or
write operation. When the B0-B35 outputs are active, a HIGH level on
MBB selects data from the mail1 register or output and a LOW level selects
FIFO1 output-register data for output.
MBF1
MBF2
ORA
Mail1 Register
Flag
O
O
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data
to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset.
Mail2 Register
Flag
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW.
MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is
selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset.
Output-Ready
Flag
ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is
(Port A) LOW, FIFO2 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO2 when ORA is HIGH. ORA is
forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH
transition of CLKA after a word is loaded to empty memory.
ORB
Output-Ready
Flag
O
ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB
(Port B) is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW
when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB
after a word is loaded to empty memory.
RST1
RST2
FIFO1 Reset
FIFO2 Reset
I
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition
of RST1 latches the status of FSO and FS1 for AFA and AEB offset selection.
FIFO1 must be reset upon power up before data is written to its RAM.
I
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition
of RST2 latches the status of FSO and FS1 for AFB and AEA offset selection.
FIFO2 must be reset upon power up before data is written to its RAM.
W/RA
W/RB
Port-A Write/
Read Select
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A
for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in
the HIGH impedance state when W/RA is HIGH.
Port-B Write/
Read Select
A LOW selects a write operation and a HIGH selects a read operation on port B
for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH
impedance state when W/RB is LOW.
5.22
5
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UN-
LESS OTHERWISE NOTED)(1)
Symbol
VCC
VI(2)
Rating
Commercial
-0.5 to 7
-0.5 to VCC+0.5
-0.5 to VCC+0.5
±20
Unit
V
Supply Voltage Range
Input Voltage Range
Output Voltage Range
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
Continuous Current Through VCC or GND
Operating Free Air Temperature Range
Storage Temperature Range
mA
mA
mA
mA
°C
°C
IOK
±50
IOUT
ICC
±50
±400
TA
0 to 70
TSTG
-65 to 150
NOTES:
1. Stressesbeyondthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice. Thesearestressratingsonlyandfunctional
operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min. Max. Unit
Supply Voltage
4.5
2
5.5
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Current
Low-Level Output Current
VIL
0.8
-4
V
IOH
mA
mA
°C
IOL
8
TA
Operating Free-Air
Temperature
0
70
5.22
6
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA-
TURE RANGE (UNLESS OTHERWISE NOTED)
IDT723622
IDT723632
IDT723642
Commerical
tA = 15, 20, 30 ns
Parameter
VOH
Test Conditions
IOH = -4 mA
Min. Typ.(1) Max.
Unit
V
VCC = 4.5V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
2.4
0.5
±5
±5
400
0
VOL
IOL = 8 mA
V
ILI
VI = VCC or 0
µA
µA
µA
mA
ILO
VO = VCC or 0
VI = VCC -0.2 V or 0
One Input at 3.4 V,
ICC
∆ICC(2)
CSA = VIH
CSB = VIH
CSA = VIL
A0-A35
B0-B35
A0-A35
B0-35
Other Inputs at VCC or GND
0
1
CSB = VIL
1
All Other Inputs
1
CIN
VI = 0,
f = 1 MHz
f = 1 MHZ
4
pF
pF
COUT
VO = 0,
8
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
5.22
7
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER-
ATING FREE-AIR TEMPERATURE
723622-15
723622-20
723632-20
723642-20
723622-30
723632-30
723642-30
723632-15
723642-15
Symbol
fS
Parameter
Min. Max.
Min. Max. Min. Max.
50 33.4
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
66.7
tCLK
15
6
20
8
30
10
10
6
tCLKH Pulse Duration, CLKA or CLKB HIGH
tCLKL Pulse Duration, CLKA and CLKB LOW
ns
6
8
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
4
5
ns
tENS
Setup Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑
4.5
5
5
6
6
7
ns
ns
ns
ns
ns
ns
tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑
or CLKB↑(1)
tFSS
Setup Time, FS0 and FS1 before RST1 and RST2
HIGH
7.5
1
8.5
1
9.5
1
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after
CLKB↑
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
1
1
1
tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or
CLKB↑(1)
4
4
5
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
2
3
9
3
ns
ns
tSKEW1(2) Skew Time, between CLKA↑ and CLKB↑ for ORA,
7.5
11
ORB, IRA, and IRB
tSKEW2(2) Skew Time, between CLKA↑ and CLKB↑ for AEA,
12
16
20
ns
AEB, AFA, and AFB
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB
cycle.
5.22
8
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
723622L15
723632L15
723642L15
723622L20
723632L20
723642L20
723622L30
723632L30
723642L30
Min. Max.
Symbol
Parameter
Min. Max. Min. Max.
Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑
to B0-B35
3
2
1
1
1
0
11
3
2
1
1
1
0
13
10
10
10
10
10
3
2
1
1
1
0
15
12
12
12
12
12
ns
tPIR
tPOR
tPAE
tPAF
tPMF
Propagation Delay Time, CLKA↑ to IRA and
CLKB↑ to IRB
8
ns
ns
ns
ns
ns
Propagation Delay Time, CLKA↑ to ORA and
CLKB↑ to ORB
8
Propagation Delay Time, CLKA↑ to AEA and
CLKB↑ to AEB
8
Propagation Delay Time, CLKA↑ to AFA and
and CLKB↑ to AFB
8
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
8
tPMR
tMDV
tPRF
Propagation Delay Time, CLKA↑ to B0-B35(1) and
CLKB↑ to A0-A35(2)
3
3
1
13.5
11
3
3
1
15
13
20
3
3
1
17
15
30
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and
MBB to B0-B35 Valid
Propagation Delay Time, RST1 LOW to AEB LOW,
AFA HIGH, and MBF1 HIGH, and RST2 LOW to
AEA LOW, AFB HIGH, and MBF2 HIGH
15
tEN
Enable Time, CSA and W/RA LOW to A0-A35 Active
and CSB LOW and W/RB HIGH to B0-B35 Active
2
1
12
8
2
1
13
10
2
1
14
11
ns
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at
high impedance and CSB HIGH or W/RB LOW
to B0-B35 at HIGH impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
5.22
9
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
during the LOW-to-HIGH transition of its reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0
and FS1 must be HIGH when FlFO1 reset (RST1) returns
HIGH. Flag-offset registers associated with FIFO2 are loaded
withoneofthepresetvaluesinthesamewaywithFIFO2reset
(RST2). When using one of the preset values for the flag
offsets, the FlFOs can be reset simultaneously or at different
times.
To program the X1, X2, Y1, and Y2 registers from port A,
both FlFOs should be reset simultaneously with FS0 and FS1
LOW during the LOW-to-HIGH transition of the reset inputs.
Afterthisresetiscomplete, thefirstfourwritestoFIFO1donot
store data in RAM but load the offset registers in the order Y1,
X1, Y2, X2. The port A data inputs used by the offset registers
are (A7-A0), (A8-A0), or (A9-A0) for the IDT723622,
IDT723632, or IDT723642, respectively. The highest num-
bered input is used as the most significant bit of the binary
number in each case. Valid programming values for the
registers ranges from 1 to 252 for the IDT723622; 1 to 508 for
the IDT723632; and 1 to 1020 for the IDT723642. After all the
offset registers are programmed from port A, the port-B input-
ready flag (IRB) is set HIGH, and both FIFOs begin normal
operation.
SIGNAL DESCRIPTION
RESET
The FIFO memories of the IDT723622/723632/723642
are reset separately by taking their reset (RST1, RST2) inputs
LOWforatleastfourport-Aclock(CLKA)andfourport-Bclock
(CLKB)LOW-to-HIGHtransitions.Theresetinputscanswitch
asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheinput-readyflag
(IRA, IRB) LOW, the output-ready flag (ORA, ORB) LOW, the
almost-empty flag (AEA, AEB) LOW, and the almost-full flag
(AFA, AFB) HIGH. Resetting a FIFO also forces the mailbox
flag (MBF1, MBF2) of the parallel mailbox register HIGH. After
a FlFO is reset, its input-ready flag is set HIGH after two clock
cycles to begin normal operation. A FIFO must be reset after
power up before data is written to its memory.
A LOW-to HIGH transition on a FlFO reset (RST1, RST2)
input latches the value of the flag-select (FS0, FS1) inputs for
choosing the almost-full and almost-empty offset program-
ming method (see almost-empty and almost-full flag offset
programming below).
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFF-
SET PROGRAMMING
FIFO WRITE/READ OPERATION
FourregistersintheIDT723622/723632/723642areused
to hold the offset values for the almost-empty and almost-full
flags. The port-B almost-empty flag (AEB) offset register is
labeled X1 and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset
register is labeled Y1 and the port-B almost-full flag (AFB)
offset register is labeled Y2. The index of each register name
corresponds to its FIFO number. The offset registers can be
loaded with preset values during the reset of a FIFO or they
can be programmed from port A (see Table 1 ) .
The state of the port-A data (A0-A35) outputs is controlled
by port-A chip select (CSA) and port-A write/read select (W/
RA). The A0-A35 outputs are in the High-impedance state
when either CSA or W/RA is HIGH. The A0-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH , MBA is LOW, and IRA is HIGH. Data is
read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO
reads and writes on port A are independent of any concurrent
To load a FIFO almost-empty flag and almost-full flag
offset registers with one of the three preset values listed in
Table1, at least one of the flag-select inputs must be HIGH
FS1
H
FS0
H
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
RST1
RST2
↑
X
↑
X
↑
64
X
H
H
X
64
H
L
X
↑
16
X
H
L
X
↑
X
16
L
H
X
↑
8
X
L
H
X
↑
X
8
L
L
↑
Programmed from port A
Programmed from port A
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset tor AEA; Y2 register holds the offset for AFB.
Table 1. Flag Programming
5.22
10
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
port-B operation.
during a clock cycle, the port’s chip select and write/read
The port-B control signals are identical to those of port A select may change states during the setup and hold time
with the exception that the port-B write/read select (W/RB) is window of the cycle.
the inverse of the port-A write/read select (W/RA). The state
When a FIFO output-ready flag is LOW, the next data
of the port-B data (B0-B35) outputs is controlled by the port- word is sent to the FIFO output register automatically by the
B chip select (CSB) and port-B write/read select (W/RB). The LOW-to-HIGH transition of the port clock that sets the output-
B0-B35 outputs are in the high-impedance state when either ready flag HIGH. When the output-ready flag is HIGH, an
CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active available data word is clocked to the FIFO output register only
when CSB is LOW and W/RB is HIGH.
when a FIFO read is selected by the port’s chip select, write/
Data is loaded into FIFO2 from the B0-B35 inputs on a read select, enable, and mailbox select.
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is SYNCHRONIZED FIFO FLAGS
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
Each FIFO is synchronized to its port clock through at
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is least two flip-flop stages. This is done to improve flag-signal
HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reliability by reducing the probability of metastable events
reads and writes on port B are independent of any concurrent when CLKA and CLKB operate asynchronously to one an-
port-A operation.
other. ORA, AEA, IRA, and AFA are synchronized to CLKA.
The setup and hold time constraints to the port clocks for ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables
the port chip selects and write/read selects are only for 4 and 5 show the relationship of each port flag to FIFO1 and
enablingwriteandreadoperationsandarenotrelatedtohigh- FIF02.
impedance control of the data outputs. If a port enable is LOW
W/ A
ENA
X
MBA
X
CLKA
A0-A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO2 output register
Active, FIFO2 output register
Active, mail2 register
PORT FUNCTION
CSA
H
L
R
X
H
H
H
L
X
X
↑
None
None
L
X
L
H
L
FIFO1 write
Mail1 write
L
H
H
↑
L
L
L
X
↑
None
L
L
H
L
FIFO2 read
None
L
L
L
H
X
↑
L
L
H
H
Active, mail2 register
Mail2 read (set MBF2 HIGH)
Table 2. Port-A Enable Functlon Table
/RB
W
ENB
X
MBB
X
CLKB
B0-B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO1 output register
Active, FIFO1 output register
Active, mail1 register
PORT FUNCTION
CSB
H
L
X
L
X
X
↑
None
None
L
X
L
L
H
L
FIFO2 write
Mail2 write
L
L
H
H
↑
L
H
H
H
H
L
L
X
↑
None
L
H
L
FIFO1 read
None
L
L
H
X
↑
L
H
H
Active, mail1 register
Mail1 read (set MBF1 HIGH)
Table 3. Port-B Enable Function Table
5.22
11
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
OUTPUT-READY FLAGS (ORA, ORB)
occurs, simultaneously forcing the output-ready flag HIGH
Theoutput-readyflagofaFIFOissynchronizedtotheport and shifting the word to the FIFO output register.
clock that reads data from its array. When the output-ready A LOW-to-HIGH transition on an output-ready flag syn-
flag is HIGH, new data is present in the FIFO output register. chronizing clock begins the first synchronization cycle of a
When the output-ready flag is LOW, the previous data word is write if the clock transition occurs at time tSKEW1 or greater
present in the FIFO output register and attempted FIFO reads after the write. Otherwise, the subsequent clock cycle can be
are ignored.
A FIFO read pointer is incremented each time a new word
the first synchronization cycle (see Figures 7 and 8).
is clocked to its output register. The state machine that
controlsanoutput-readyflagmonitorsawritepointerandread
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. From the time a word
iswrittentoaFIFO, itcanbeshiftedtotheFIFOoutputregister
in a minimum of three cycles of the output-ready flag synchro-
nizing clock. Therefore, an output-ready flag is LOW if a word
in memory is the next data to be sent to the FlFO output
registerandthreecyclesoftheportClockthatreadsdatafrom
the FIFO have not elapsed since the time the word was
written. The output-ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock
INPUT-READY FLAGS (IRA, IRB)
The input-ready flag of a FlFO is synchronized to the port
clock that writes data to its array. When the input-ready flag
isHIGH, amemorylocationisfreeintheSRAMtoreceivenew
data. No memory locations are free when the input-ready flag
is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write pointer and read pointer comparator that
indicates when the FlFO SRAM status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO, itspreviousmemory
locationisreadytobewritteninaminimumoftwocyclesofthe
ynchronized
to CLKB
Synchronized
to CLKA
S
Number of Words in FIFO
IDT723622(1,2)
IDT723632(1,2)
IDT723642(1,2)
ORB
IRA
AEB
AFA
0
0
0
L
L
H
H
H
H
H
L
1 to X1
(X1+1) to [256-(Y1+1)]
(256-Y1) to 255
256
1 to X1
(X1+1) to [512-(Y1+1)]
(512-Y1) to 511
512
1 to X1
(X1+1) to [1024-(Y1+1)]
(1024-Y1) to 1023
1024
H
H
H
H
L
H
H
H
H
H
L
L
Table 4. FIF01 Flag Operatlon
Notes:
1. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1
and Y1 are selected during a reset of FIFO1 or programmed from port A.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
ynchronized
to CLKA
Synchronized
to CLKB
S
Number of Words in FIFO
IDT723632(1,2)
IDT723622(1,2)
IDT723642(1,2)
ORA
IRB
AEA
AFB
0
0
1 to X2
0
L
L
H
H
H
H
H
L
1 to X2
(X2+1) to [256-(Y2+1)]
(256-Y2) to 255
256
1 to X2
(X2+1) to [1024-(Y2+1)]
(1024-Y2) to 1023
1024
H
H
H
H
L
H
H
H
H
H
L
(X2+1) to [512-(Y2+1)]
(512-Y2) to 511
512
L
Table 5. FIF02 Flag Operatlon
Notes:
1. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and
Y2 are selected during a reset of FIFO2 or programmed from port A.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
5.22
12
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
input-ready flag synchronizing clock. Therefore, an input- almost-empty flag and almost-full flag offset programming
readyflagisLOWiflessthantwocyclesoftheinput-readyflag above). An almost-full flag is LOW when the number of words
synchronizing clock have elapsed since the next memory in its FIFO is greater than or equal to (256-Y), (512-Y), or
write location has been read. The second LOW-to-HIGH (1024-Y) for the IDT723622, IDT723632, or IDT723642 re-
transitionontheinput-readyflagsynchronizingClockafterthe spectively. An almost-full flag is HIGH when the number of
read sets the input-ready flag HIGH.
words in its FIFO is less than or equal to [256-(Y+1)], [512-
A LOW-to-HIGH transition on an input-ready flag syn- (Y+1)], or [1024-(Y+1)] for the IDT723622, IDT723632, or
chronizing clock begins the first synchronization cycle of a IDT723642 respectively. Note that a data word present in the
read if the clock transition occurs at time tSKEW1 or greater FIFO output register has been read from memory.
after the read. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 9 and 10).
Two LOW-to-HIGH transitions of the almost-full flag syn-
chronizing clock are required after a FIFO read for its almost-
full flag to reflect the new level of fill. Therefore, the almost-full
flag of a FIFO containing [256/512/1024-(Y+1)] or less words
ALMOST-EMPTY FLAGS (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the remains LOW if two cycles of its synchronizing clock have not
port clock that reads data from its array. The state machine elapsed since the read that reduced the number of words in
thatcontrolsanalmost-emptyflagmonitorsawritepointerand memory to [256/512/1024-(Y+1)]. An almost-full flag is set
read pointer comparator that indicates when the FIFO SRAM HIGH by the second LOW-to-HIGH transition of its synchro-
status is almost empty, almost empty+1, or almost empty+2. nizing clock after the FIFO read that reduces the number of
The almost-empty state is defined by the contents of register words in memory to [256/512/1024-(Y+1)]. A LOW-to-HIGH
X1 for AEB and register X2 for AEA. These registers are transition of an almost-full flag synchronizing clock begins the
loaded with preset values during a FIFO reset or programmed first synchronization cycle if it occurs at time tSKEW2 or greater
from port A (see almost-empty flag and almost-full flag offset after the read that reduces the number of words in memory to
programming above). An almost empty Flag is LOW when its [256/512/1024-(Y+1)]. Otherwise, the subsequent synchro-
FIFO contains X or less words and is HIGH when its FIFO nizing clock cycle may be the first synchronization cycle (see
contains(X+1)ormorewords.AdatawordpresentintheFIFO Figures 13 and 14).
output register has been read from memory.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an almost-empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figures 11 and 12).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port-A write is
selected by CSA, W/RA, and ENA and with MBA HIGH. A
LOW-to-HIGH transition on CLKB writes BO-B35 data to the
mail2 register when a port-B write is selected by CSB, W/RB,
and ENB and with MBB HIGH. Writing data to a mail register
sets its corresponding flag (MBF1 or MBF2) LOW. Attempted
writes to a mail register are ignored while the mail flag is LOW.
Whendataoutputsofaportareactive, thedataonthebus
comes from the FIFO output register when the port mailbox
select input is LOW and from the mail register when the port-
ALMOST-FULL FLAGS (
,
)
AFA AFB
The almost-full flag of a FIFO is synchronized to the port mailbox select input is HIGH. The mail1 register flag (MBF1 )
clock that writes data to its array. The state machine that is set HIGH by a LOW-to-HIGH transition on CLKB when a
controls an almost-full flag monitors a write pointer and read port-BreadisselectedbyCSB, W/RB, andENBandwithMBB
pointer comparator that indicates when the FIFO SRAM HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-
status is almost full, almost full-1, or almost full-2. The almost- to-HIGH transition on CLKA when a port-A read is selected by
full state is defined by the contents of register Y1 for AFA and CSA, W/RA, and ENA and with MBA HIGH. The data in a mail
register Y2 for AFB. These registers are loaded with preset register remains intact after it is read and changes only when
values during a FlFO reset or programmed from port A (see new data is written to the register.
5.22
13
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
tRSTH
CLKB
tRSTS
tFSS
tFSH
RST1
FS1,FS0
0,1
tPIR
tPIR
IRA
tPOR
ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
3022 drw 04
Figure 1. FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight(1)
.
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
CLKA
4
tFSS
tFSH
RST1,
RST2
0,0
FS1,FS0
IRA
tPIR
(1)
tSKEW1
tENS
tENH
ENA
tDH
tDS
A0 - A35
AEA Offset
(X2)
AFB Offset
(Y2)
AEB Offset
(X1)
AFA Offset
(Y1)
First Word to FIFO1
CLKB
IRB
1
2
tPIR
3022 drw 05
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the
rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset.
5.22
14
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
IRA
tENS
tENH
tENH
CSA
tENS
W/RA
MBA
ENA
tENH
tENS
tENS
tDS
tENH
tDH
tENH
tENS
tENH
tENS
(1)
W2(1)
A0 - A35
No Operation
W1
3022 drw 06
NOTE:
1. Written to FIFO1.
Figure 3. Port-A Write Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKB
IRB
t
ENH
t
ENS
ENS
CSB
t
ENH
t
W/RB
MBB
t
ENH
tENS
t
ENH
tENH
tENH
tENS
tENS
tENS
ENB
t
DH
t
DS
(1)
W2(1)
B0 - B35
No Operation
W1
3022 drw 07
NOTE:
1. Written to FIFO2.
Figure 4. Port-B Write Cycle Timing for FIFO2.
5.22
15
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
ORB
CSB
W/RB
MBB
tENS
tENH
tA
tENH
tENH
tENS
tENS
ENB
No
tDIS
tMDV
tA
Operation
tEN
B0 - B35
W1(1)
W2(1)
W3(1)
3022 drw 08
NOTE:
1. Read From FIFO1.
Figure 5. Port-B Read Cycle Timing for FIFO1.
tCLK
tCLKH
tCLKL
CLKA
ORA
CSA
W/RA
MBA
tENS
tENH
tENH
tA
tENH
tENS
tENS
ENA
No
Operation
tDMV
tDIS
tA
tEN
A0 - A35
(1)
W2(1)
W3(1)
W1
3022 drw 09
NOTE:
1. Read From FIFO2.
Figure 6. Port-A Read Cycle Timing for FIFO2.
5.22
16
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
MBA
tENS
tENS
tENH
tENH
ENA
HIGH
tDS
tDH
IRA
A0 - A35
W1
tCLK
(1)
tCLKH
tSKEW1
tCLKL
1
2
3
CLKB
ORB
tPOR
tPOR
Old Data in FIFO1 Output Register
LOW
CSB
HIGH
LOW
W/RB
MBB
tENS
tENH
ENB
tA
B0 -B35
Old Data in FIFO1 Output Register
W1
3022 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Figure 7. ORB Flag Timing and First Data Word Fallthrough when FIFO1 is Empty.
5.22
17
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
W/RB
tENS
tENS
tENH
tENH
MBB
ENB
HIGH
IRB
tDH
tDS
B0 - B35
W1
tCLK
(1)
tCLKH
tCLKL
tSKEW1
1
2
3
CLKA
tPOR
tPOR
Old Data in FIFO2 Output Register
ORA
CSA
LOW
LOW
LOW
W/RA
MBA
tENS
tENH
ENA
tA
A0 -A35
Old Data in FIFO2 Output Register
W1
3022 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Figure 8. ORA Flag Timing and First Data Word Fallthrough when FIFO2 is Empty.
5.22
18
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
HIGH
LOW
W/RB
MBB
tENH
tENS
ENB
HIGH
ORB
tA
Previous Word in FIFO1 Output Register
tSKEW1
Next Word From FIFO1
tCLK
B0 -B35
(1)
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
IRA
FIFO1 Full
LOW
CSA
HIGH
WRA
MBA
tENH
tENH
tDH
tENS
tENS
ENA
A0 - A35
NOTE:
tDS
To FIFO1
3022 drw 12
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 9. IRA Flag Timing and First Available Write when FIFO1 is Full.
5.22
19
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
LOW
W/RA
MBA
ENA
tENS
tENH
HIGH
ORA
tA
Previous Word in FIFO2 Output Register
tSKEW1
A0 -A35
Next Word From FIFO2
tCLK
(1)
tCLKH
tCLKL
1
2
CLKB
IRB
tPIR
tPIR
FIFO2 FULL
CSB
WRB
MBB
LOW
LOW
tENS
tENS
tENH
tENH
ENB
tDS
tDH
B0 - B35
To FIFO2
3022 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 10. IRB Flag Timing and First Available Write when FIFO2 is Full.
CLKA
tENS
tENH
ENA
(1)
tSKEW2
1
2
CLKB
AEB
tPAE
tPAE
X1 Word in FIFO1
(X1+1) Words in FIFO1
tENS
tENH
ENB
3022 drw 14
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has
been read from the FIFO.
Figure 11. Timing for
when FIFO2 is Almost Empty.
AEB
5.22
20
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
tENH
tENS
ENB
(1)
tSKEW2
1
2
CLKA
AEA
tPAE
tPAE
X2 Words in FIFO2
(X2+1) Words in FIFO2
tENS
tENH
ENA
3022 drw 15
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has
been read from the FIFO.
Figure 12. Timing for
when FIFO2 is Almost Empty.
AEA
(1)
tSKEW2
1
2
CLKA
ENA
tENH
tENS
tPAF
tPAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
ENB
tENH
tENS
3022 drw 16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has
been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642.
Figure 13. Timing for
when FIFO1 is Almost Full.
AFA
5.22
21
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
(1)
tSKEW2
1
2
CLKB
tENH
tPAF
tENS
ENB
AFB
tPAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS
tENH
ENA
3022 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has
been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642.
Figure 14. Timing for
when FIFO2 is Almost Full.
AFB
CLKA
CSA
tENH
tENS
W/RA
MBA
ENA
tDH
tDS
W1
A0 - A35
CLKB
tPMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS
tMDV
tEN
tDIS
tPMR
B0 - B35
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
3022 drw 18
Figure 15. Timing for Mail1 Register and
Flag.
MBF1
5.22
22
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
tENH
tENS
CSB
W/RB
MBB
ENB
B0 - B35
CLKA
tDH
tDS
W1
tPMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS
tEN
tMDV
tDIS
tPMR
W1 (Remains valid in Mail 2 Register after read)
A0 - A35
FIFO2 Output Register
3022 drw 19
Figure 16. Timing for Mail2 Register and
Flag.
MBF2
5.22
23
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
f
= 1/2 f
data
T = 25°C
A
C = 0pF
L
250
V
CC = 5.5 V
V
CC = 5.0 V
200
150
100
V
CC
= 4.5 V
50
0
0
10
20
30
40
50
60
70
3022 drw 18
fs – Clock Frequency – MHz
Figure 17.
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 17 was taken while simultaneously reading and writing a FIFO on the
IDT723622/723632/723642 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero
capacitance load. Once the capacitance load per data-output channel and the number of IDT723622/723632/723642
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 17, the maximum power dissipation (PT) of the IDT723622/723632/723642 may be
calculated by:
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + ∑(CL x VCC2 X fo)
where:
N
=
number of inputs driven by TTL levels
∆ICC=
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
output capacitance load
dc
CL
fo
=
=
=
switching frequency of an output
When no read or writes are occurring on the IDT723632, the power dissipated by a single clock (CLKA or CLKB) input
running at frequency fs is calculated by:
PT = VCC x fs x 0.184 mA/MHz
5.22
24
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5 V
Ω
1.1 k
From Output
Under Test
30 pF(1)
Ω
680
PROPAGATION DELAY
LOAD CIRCUIT
GND
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
1.5 V
1.5 V
GND
GND
t
S
t
h
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
GND
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
GND
≈
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
V
OL
tPD
tPZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
tPHZ
OL
≈
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3022 drw 20
NOTE:
1. Includes probe and jig capacitance.
Figure 18. Load Circuit and Voltage Waveforms.
5.22
25
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
PF
PQF
Thin Quad Flat Pack
Plastic Quad Flat Pack
15
20
30
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
L
Low Power
723622 256 x 36 Synchronous BiFIFO
723632 512 x 36 Synchronous BiFIFO
723642 1024 x 36 Synchronous BiFIFO
3022 drw 22
5.22
26
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