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IDT723646L12PFG [IDT]

FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128;
IDT723646L12PFG
型号： IDT723646L12PFG
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128

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CMOS TRIPLE BUS SyncFIFOTM  
WITH BUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2  
1,024 x 36 x 2  
IDT723626  
IDT723636  
IDT723646  
• Serial or parallel programming of partial flags  
FEATURES:  
• Big- or Little-Endian format for word and byte bus sizes  
• Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
• Memory storage capacity:  
IDT723626 – 256 x 36 x 2  
IDT723636 – 512 x 36 x 2  
IDT723646 – 1,024 x 36 x 2  
• Mailbox bypass registers for each FIFO  
• Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
• Auto power down minimizes power dissipation  
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
• Clock frequencies up to 83 MHz (8ns access time)  
• Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
•
Industrial temperature range (–40°C to +85°C) is available  
• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
• Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
DESCRIPTION:  
The IDT723626/723636/723646 is a monolithic, high-speed, low-  
power, CMOS Triple Bus synchronous (clocked) FIFO memory which  
supportsclockfrequenciesupto83MHzandhasreadaccesstimesasfastas  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
W/RA  
Control  
18  
B0-B17  
ENA  
MBA  
RAM ARRAY  
256 x 36  
36  
36  
Logic  
512 x 36  
1,024 x 36  
CLKB  
RENB  
CSB  
MBB  
SIZEB  
FIFO1,  
Mail1  
Reset  
Logic  
Port-B  
Control  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
FFA/IRA  
AEB  
AFA  
FIFO1  
FIFO2  
Common  
Port  
SPM  
FS0/SD  
Programmable Flag  
Offset Registers  
Control  
Logic  
BE  
Timing  
Mode  
FS1/SEN  
(B and C)  
A0-A35  
10  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RAM ARRAY  
256 x 36  
18  
36  
36  
C0-C17  
512 x 36  
1,024 x 36  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
SIZEC  
Mail 2  
Register  
MBF2  
3271 drw01  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIALTEMPERATURERANGE  
AUGUST 2001  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3271/4  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
These devices are a synchronous (clocked) FIFO, meaning each port  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
each port are independent of one another and can be asynchronous or  
coincident. The enables for each port are arranged to provide a simple  
DESCRIPTION(CONTINUED)  
8ns.Twoindependent256/512/1,024x36dual-portSRAMFIFOsonboard  
each chip buffer data between a bidirectional 36-bit bus (Port A) and two  
unidirectional18-bitbuses(PortBtransmitsdata,PortCreceivesdata.)FIFO  
datacanbereadoutofPortBandwrittenintoPortCusingeither18-bitor9-  
bitformatswithachoiceofBig-orLittle-Endianconfigurations.  
PIN CONFIGURATION  
INDEX  
1
2
3
4
5
6
7
8
CLKB  
PRS2  
Vcc  
C17  
C16  
W/RA  
ENA  
CLKA  
GND  
A35  
A34  
A33  
A32  
Vcc  
A31  
A30  
GND  
A29  
A28  
A27  
A26  
A25  
A24  
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
C15  
C14  
GND  
MBC  
C13  
C12  
C11  
C10  
C9  
C8  
Vcc  
C7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
C6  
SIZEB  
GND  
C5  
C4  
C3  
C2  
C1  
C0  
GND  
B17  
B16  
SIZEC  
Vcc  
B15  
B14  
B13  
B12  
GND  
B11  
B10  
A23  
BE/FWFT  
GND  
A22  
Vcc  
A21  
A20  
A19  
A18  
GND  
A17  
A16  
A15  
A14  
A13  
Vcc  
A12  
GND  
A11  
A10  
3271 drw02  
TQFP (PK128-1, order code: PF)  
TOP VIEW  
2
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- mode. IR indicates whether or not the FIFO has available memory locations.  
nouscontrol.  
ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe  
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox presence of valid data on the outputs.  
registers.Themailboxregisters'widthmatchestheselectedbuswidthofports  
BandC. Eachmailboxregisterhas a flag(MBF1 andMBF2)tosignalwhen aprogrammableAlmost-Fullflag(AFAandAFC).AEAandAEBindicatewhen  
newmailhas beenstored.  
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial whenthe FIFOcontains more thana selectednumberofwords.  
Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation  
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and  
aselectednumberofwordsremainintheFIFOmemory.AFAandAFCindicate  
FFA/IRA,FFC/IRC,AFAandAFCaretwo-stagesynchronizedtothePort  
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- Clockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEA,andAEBare  
ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO two-stage synchronized to the Port Clock that reads data from its array.  
has its own, independent Master Reset pin, MRS1 andMRS2.  
ProgrammableoffsetsforAEA,AEB,AFA,AFCareloadedinparallelusingPort  
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe AorinserialviatheSDinput.TheSerialProgrammingModepin(SPM)makes  
memory. UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., thisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEB  
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset thresholdcanbesetat8,16or64locationsfromtheemptyboundaryandthe  
is useful since it permits flushing of the FIFO memory without changing any AFAandAFCthresholdcanbesetat8,16or64locationsfromthefullboundary.  
configurationsettings. EachFIFOhasitsown,independentPartialResetpin, AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.  
PRS1 and PRS2.  
Twoormore FIFOs maybe usedinparalleltocreate widerdata paths.  
These devices have two modes of operation: In the IDT Standard Suchawidthexpansionrequiresnoadditional,externalcomponents.Further-  
mode, the first word written to an empty FIFO is deposited into the memory more,twoIDT723626/723636/723646FIFOscanbecombinedwithunidirec-  
array. A read operation is required to access that word (along with all other tionalFIFOscapableofFirstWordFallThroughtiming(i.e.theSuperSyncFIFO  
words residing in memory). In the First Word Fall Through mode (FWFT), family)toformadepthexpansion.  
the first word written to an empty FIFO appears automatically on the  
If, at any time, the FIFO is not actively performing a function, the chip  
outputs, no read operation required (Nevertheless, accessing subsequent willautomaticallypowerdown. Duringthe powerdownstate, supplycurrent  
wordsdoesnecessitateaformalreadrequest). ThestateoftheBE/FWFTpin consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol  
duringMasterResetdeterminesthemodeinuse.  
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.  
The IDT723626/723636/723646s are characterized for operation from  
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and  
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). 0°Cto70°C. Industrialtemperature range (–40°Cto+85°C)is available by  
TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS  
whether or not the FIFO memory is empty. FF shows whether the memory is technology.  
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough  
3
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
PINDESCRIPTIONS  
Symbol  
Name  
PortAData  
I/O  
Description  
A0-A35  
I/O 36-bitbidirectionaldataportforsideA.  
AEA  
PortAAlmost-Empty  
Flag  
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2is  
lessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.  
AEB  
PortBAlmost-Empty  
Flag  
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsinFIFO1is  
lessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.  
AFA  
PortAAlmost-Full  
Flag  
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsin  
FIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.  
AFC  
PortCAlmost-Full  
Flag  
ProgrammableAlmost-FullflagsynchronizedtoCLKC.ItisLOWwhenthenumberofemptylocationsin  
FIFO2is less thanorequaltothevalueintheAlmost-FullCOffsetregister,Y2.  
B0-B17  
PortBData  
O
I
18-bitoutputdataportforsideB.  
BE/FWFT Big-Endian/  
FirstWord  
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this  
case, dependingonthe bus size, the most significantbyte orwordonPortAis readfromPortBfirst(A-to-B  
dataflow)oriswrittentoPortCfirst(C-to-Adataflow).ALOWonBEwillselectLittle-Endianoperation.  
In this case, the least significantbyte orwordonPortAis readfromPortBfirst(A-to-Bdata flow)oris  
writtentoPortCfirst(C-to-Adataflow).  
Fall Through  
Select  
AfterMasterReset,thispinselectsthetimingmode.AHIGHonFWFTselectsIDTStandardmode, aLOW  
selectsFirstWordFallThroughmode.Oncethetimingmodehasbeenselected,thelevelonFWFTmust  
bestaticthroughoutdeviceoperation.  
C0-C17  
CLKA  
PortC Data  
PortAClock  
I
I
18-bitinputdataportforsideC.  
CLKAis a continuous clockthatsynchronizes alldata transfers throughPortAandcanbe asynchronous or  
coincidenttoCLKB. FFA/IRA, EFA/ORA, AFA, andAEA are allsynchronizedtothe LOW-to-HIGH  
transitionofCLKA.  
CLKB  
CLKC  
CSA  
PortBClock  
I
I
CLKBis a continuous clockthatsynchronizes alldata transfers throughPortBandcanbe asynchronous or  
coincidenttoCLKA.EFB/ORBandAEBaresynchronizedtotheLOW-to-HIGHtransitionofCLKB.  
PortCClock  
CLKCis acontinuous clockthatsynchronizes alldatatransfers throughPortCandcanbeasynchronous  
orcoincidenttoCLKA. FFC/IRCandAFC are synchronizedtothe LOW-to-HIGHtransitionofCLKC.  
PortAChipSelect  
PortBChipSelect  
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35  
outputsareinthehigh-impedancestatewhenCSAisHIGH.  
CSB  
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB. The B0-B17  
outputsareinthehigh-impedancestatewhenCSBisHIGH.  
EFA/ORA PortAEmpty/  
OutputReadyFlag  
O
This is adualfunctionpin.IntheIDTStandardmode,the EFAfunctionis selected.EFAindicates whether  
ornottheFIFO2memoryisempty.IntheFWFTmode,theORAfunctionisselected.ORAindicatesthe  
presence ofvaliddata onthe A0-A35outputs, available forreading. EFA/ORAis synchronizedtothe  
LOW-to-HIGHtransitionofCLKA.  
EFB/ORB PortBEmpty/  
OutputReadyFlag  
O
This is adualfunctionpin.IntheIDTStandardmode,the EFBfunctionis selected.EFBindicates whether  
ornottheFIFO1memoryisempty.IntheFWFTmode,theORBfunctionisselected.ORBindicatesthe  
presence ofvaliddata onthe B0-B17outputs, available forreading. EFB/ORBis synchronizedtothe  
LOW-to-HIGHtransitionofCLKB.  
ENA  
PortAEnable  
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.  
FFA/IRA  
PortAFull/  
Input Ready Flag  
O
This is adualfunctionpin.IntheIDTStandardmode,the FFAfunctionis selected. FFAindicates whether  
ornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRA  
indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis  
synchronizedtotheLOW-to-HIGHtransitionofCLKA.  
FFC/IRC  
Port C Full/  
Input Ready Flag  
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFC functionis selected. FFC indicates whether  
ornotthe FIFO2memoryis full. Inthe FWFTmode, the IRCfunctionis selected. IRCindicates whetheror  
notthere is space available forwritingtothe FIFO2memory. FFC/IRCis synchronizedtothe  
LOW-to-HIGHtransitionofCLKC.  
4
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
PINDESCRIPTIONS(CONTINUED)  
Symbol  
Name  
I/O  
Description  
FS1/SEN FlagOffset  
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.DuringMasterReset,  
FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.ThreeOffsetregister  
programmingmethods are available:automaticallyloadone ofthree presetvalues (8, 16, or64), parallelload  
from Port A, and serial FS0/SDload.  
Select1/  
SerialEnable,  
FlagOffset  
Select0/  
SerialData  
I
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SENisusedasanenablesynchronousto  
theLOW-to-HIGHtransitionofCLKA.WhenFS1/SEN is LOW,arisingedgeonCLKAloadthebitpresenton  
FS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe Offsetregisters is 32forthe  
IDT723626, 36 for the IDT723636, and 40 for the IDT723646. The first bit write stores the Y-register (Y1) MSB  
andthelastbitwritestores theX-register(X2)LSB.  
MBA  
MBB  
Port A Mailbox  
Select  
I
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs  
are active, a HIGHlevelonMBAselects data fromthe mail2registerforoutputanda LOWlevelselects FIFO2  
output-registerdataforoutput.  
Port B Mailbox  
Select  
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are  
active,aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselectsFIFO1output  
registerdataforoutput.  
MBC  
Port C Mailbox  
Select  
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during  
MasterReset.  
MBF1  
Mail1RegisterFlag O MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.Writestothemail1  
registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-HIGHtransitionofCLKBwhena  
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.  
MBF2  
MRS1  
Mail2RegisterFlag O MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKCthatwritesdatatothemail2register.Writestothemail2  
registerare inhibitedwhile MBF2 is LOW. MBF2is setHIGHbya LOW-to-HIGHtransitionofCLKAwhena Port  
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.  
MasterReset  
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB  
outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialorparallel)  
andoneofthreeprogrammableflagdefaultoffsetsforFIFO1andFIFO2.ItalsoconfiguresportsBandCforbussize  
andendianarrangement.FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB  
mustoccurwhileMRS1isLOW.  
MRS2  
MasterReset  
I
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortAoutput  
registertoallzeroes.ALOW-to-HIGHtransitiononMRS2toggledsimultaneouslywithMRS1,selectstheprogramming  
method(serialorparallel)andoneofthethreeflagdefaultoffsetsforFIFO2.FourLOW-to-HIGHtransitionsofCLKA  
andfourLOW-to-HIGHtransitionsofCLKCmustoccurwhileMRS2isLOW.  
PRS1  
PRS2  
RENB  
PartialReset  
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB  
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,programming  
method(serialorparallel),andprogrammableflagsettingsareallretained.  
PartialReset  
I
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA  
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,programming  
method(serialorparallel),andprogrammableflagsettingsareallretained.  
Port B Read Enable  
I
I
RENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB.  
(1)  
SIZEB  
PortB  
BusSizeSelect  
SIZEBdetermines the bus widthofPortB. AHIGHonthis pinselects byte (9-bit)bus size. ALOWonthis pin  
selects word(18-bit)bus size. SIZEBworks withSIZECandBEtoselectthe bus size andendianarrangementfor  
ports BandC. The levelofSIZEBmustbe staticthroughoutdevice operation.  
(1)  
SIZEC  
Port C  
BusSizeSelect  
I
I
SIZECdetermines the bus widthofPortC. AHIGHonthis pinselects byte (9-bit)bus size. ALOWonthis pin  
selects word(18-bit)bus size. SIZECworks withSIZEBandBEtoselectthe bus size andendianarrangementfor  
ports BandC. The levelofSIZECmustbe staticthroughoutdevice operation.  
(1)  
SPM  
SerialProgramming  
Mode  
ALOWonthispinselectsserialprogrammingofpartialflagoffsets.AHIGHonthispinselectsparallelprogramming  
or defaultoffsets (8, 16, or64).  
WENC  
PortCWriteEnable  
I
I
WENCmustbeHIGHtoenableaLOW-to-HIGHtransitionofCLKCtowritedataonPortC.  
W/RA  
PortAWrite/Read  
Select  
AHIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGHtransitionof  
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.  
NOTE:  
1. SIZEB, SIZEC and SPM are not TTL compatible. These inputs should be tied to GND or VCC.  
5
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR  
TEMPERATURE RANGE (Unless otherwise noted)(1)  
Symbol  
Rating  
Commercial  
–0.5 to 7  
–0.5 to VCC+0.5  
–0.5 to VCC+0.5  
±20  
Unit  
V
VCC  
SupplyVoltageRange  
InputVoltageRange  
OutputVoltageRange  
(2)  
VI  
V
(2)  
VO  
V
IIK  
Input Clamp Current (VI < 0 or VI > VCC)  
Output Clamp Current (VO = < 0 or VO > VCC)  
Continuous Output Current (VO = 0 to VCC)  
Continuous Current Through VCC or GND  
StorageTemperatureRange  
mA  
mA  
mA  
mA  
°C  
IOK  
±50  
IOUT  
ICC  
±50  
±400  
TSTG  
–65 to 150  
NOTES:  
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device  
at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended  
periods may affect device reliability.  
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.  
RECOMMENDEDOPERATINGCONDITIONS  
Symbol  
VCC  
VIH  
Parameter  
Min. Typ. Max. Unit  
SupplyVoltage(Commercial)  
4.5  
2
5.0  
—
—
—
—
—
5.5  
V
V
High-LevelInputVoltage(Commercial)  
Low-LevelInputVoltage(Commercial)  
High-LevelOutputCurrent(Commercial)  
Low-LevelOutputCurrent(Commercial)  
OperatingFree-AirTemperature(Commercial)  
VIL  
—
—
—
0
0.8  
–4  
8
V
IOH  
mA  
mA  
°C  
IOL  
TA  
70  
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-  
AIR TEMPERATURE RANGE (Unless otherwise noted)  
IDT723626  
IDT723636  
IDT723646  
Commercial  
tCLK = 12, 15 ns  
Symbol  
VOH  
Parameter  
OutputLogic"1"Voltage  
Test Conditions  
Min.  
2.4  
—
Typ.(1)  
—
—
—
—
—
—
4
Max.  
—
Unit  
V
VCC = 4.5V,  
IOH = –4 mA  
IOL = 8 mA  
VOL  
OutputLogic"0"Voltage  
VCC = 4.5V,  
VCC = 5.5V,  
VCC = 5.5V,  
0.5  
±10  
±10  
8
V
ILI  
InputLeakageCurrent(AnyInput)  
OutputLeakageCurrent  
VI = VCC or 0  
VO = VCC or 0  
VI = VCC - 0.2V or 0  
VI = VCC - 0.2V or 0  
f = 1 MHz  
—
µ A  
µ A  
mA  
mA  
pF  
ILO  
—
ICC2(2)  
ICC3(2)  
Standby Current (with CLKA, CLKB and CLKC running) VCC = 5.5V,  
—
StandbyCurrent(noclocksrunning)  
InputCapacitance  
VCC = 5.5V,  
VI = 0,  
—
1
(3)  
CIN  
—
—
(3)  
COUT  
OutputCapacitance  
VO = 0,  
f = 1 MHZ  
—
8
—
pF  
NOTES:  
1. All typical values are at VCC = 5V, TA = 25°C.  
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).  
3. Characterized values, not currently tested.  
4. Industrial temperature range product is available by special order.  
6
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION  
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723626/723636/723646 with CLKA,  
CLKBandCLKCsettofS. Alldata inputs anddata outputs change state duringeachclockcycle toconsume the highestsupplycurrent. Data outputs were  
disconnectedtonormalizethegraphtoazerocapacitanceload.Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT723626/723636/  
723646 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.  
CALCULATING POWER DISSIPATION  
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthese FIFOs maybe calculatedby:  
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC X fo)  
N
where:  
N
∆ICC  
dc  
CL  
fo  
=
=
=
=
=
number of inputs driven by TTL levels  
increase in power supply current for each input at a TTL HIGH level  
duty cycle of inputs at a TTL HIGH level of 3.4V  
output capacitance load  
switchingfrequencyofanoutput  
300  
250  
f
data = 1/2 fS  
T
A
= 25°C  
C
L
= 0 pF  
VCC = 5.5V  
VCC = 5.0V  
200  
150  
100  
VCC = 4.5V  
50  
0
0
10  
20  
30  
40  
Clock Frequency  
50  
60  
70  
80  
90  
3271 drw02a  
fS  
MHz  
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)  
7
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
TIMINGREQUIREMENTSOVERRECOMMENDEDRANGESOFSUPPLYVOLT-  
AGEANDOPERATINGFREE-AIRTEMPERATURE  
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C)  
Commercial  
IDT723626L12  
IDT723636L12  
IDT723646L12  
IDT723626L15  
IDT723636L15  
IDT723646L15  
Symbol  
fS  
Parameter  
Min.  
—
12  
5
Max.  
83  
Min.  
—
15  
6
Max.  
Unit  
MHz  
ns  
Clock Frequency, CLKA, CLKB, or CLKC  
66.7  
—
—
—
—
—
—
tCLK  
tCLKH  
tCLKL  
tDS  
Clock Cycle Time, CLKA, CLKB, or CLKC  
—
—
—
—
—
—
Pulse Duration, CLKA, CLKB, or CLKC HIGH  
Pulse Duration, CLKA, CLKB, ORCLKCLOW  
Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑  
SetupTime, CSA andW/RAbeforeCLKA↑;CSB beforeCLKB↑  
ns  
5
6
ns  
3
4
ns  
tENS1  
tENS2  
4
4.5  
4.5  
ns  
Setup Time, ENA and MBA before CLKA↑; RENB and MBB before CLKB↑ ;  
WENCandMBCbefore CLKC↑  
3
ns  
(2)  
tRSTS  
tFSS  
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑or CLKB↑  
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH  
SetupTime, BE/FWFT beforeMRS1 andMRS2 HIGH  
Setup Time, SPM before MRS1 and MRS2 HIGH  
SetupTime,FS0/SDbeforeCLKA↑  
5
7.5  
7.5  
7.5  
3
—
—
—
—
—
—
—
—
—
5
7.5  
7.5  
7.5  
4
—
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tBES  
tSPMS  
tSDS  
tSENS  
tFWS  
tDH  
SetupTime,FS1/SENbeforeCLKA↑  
3
4
SetupTime,BE/FWFTbeforeCLKA↑  
0
0
HoldTime, A0-A35afterCLKA↑ andC0-C17afterCLKC↑  
0.5  
0.5  
1
tENH  
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB  
afterCLKB↑;WENCandMBCafterCLKC↑  
1
(2)  
tRSTH  
tFSH  
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑  
4
2
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH  
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH  
Hold Time, SPM after MRS1 and MRS2 HIGH  
HoldTime,FS0/SDafterCLKA↑  
tBEH  
2
2
tSPMH  
tSDH  
2
2
0.5  
0.5  
2
1
tSENH  
tSPH  
HoldTime,FS1/SENHIGHafterCLKA↑  
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH  
2
(3)  
tSKEW1  
SkewTime, betweenCLKA↑and CLKB↑for EFB/ORBand FFA/IRA; between  
CLKA↑ and CLKC↑ for EFA/ORA and FFC/IRC  
5
7.5  
(3,4)  
tSKEW2  
SkewTime,betweenCLKA↑andCLKB↑forAEB andAFA;betweenCLKA↑ and  
CLKC↑ for AEA and AFC  
12  
—
12  
—
ns  
NOTES:  
1. Industrial temperature range product is available by special order.  
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.  
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.  
4. Design simulated, not tested (typical values).  
8
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY  
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF  
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C)  
Commercial  
IDT723626L12  
IDT723636L12  
IDT723646L12  
IDT723626L15  
IDT723636L15  
IDT723646L15  
Symbol  
tA  
Parameter  
Min.  
2
Max.  
Min.  
2
Max.  
10  
8
Unit  
ns  
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B17  
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to FFC/IRC  
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑toEFB/ORB  
PropagationDelayTime,CLKA↑toAEAandCLKB↑toAEB  
Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC  
8
8
8
8
8
8
tWFF  
tREF  
tPAE  
tPAF  
2
2
ns  
1
1
8
ns  
1
1
8
ns  
1
1
8
ns  
tPMF  
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH, CLKB↑ to MBF1  
HIGH, andCLKC↑ toMBF2 LOW  
0
0
8
ns  
tPMR  
tMDV  
tRSF  
Propagation Delay Time, CLKA↑to B0-B17(2) and CLKC↑toA0-A35(3)  
2
2
1
8
8
2
2
1
10  
10  
15  
ns  
ns  
ns  
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B17 valid  
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and  
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH  
10  
tEN  
tDIS  
Enable Time, CSA orW/RALOWtoA0-A35Active andCSB LOWtoB0-B17Active  
2
1
6
6
2
1
10  
8
ns  
ns  
Disable Time, CSA or W/RA HIGH to A0-A35 at HIGH impedance and CSB HIGH  
toB0-B17atHIGHimpedance  
NOTES:  
1. Industrial temperature range product is available by special order.  
2. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.  
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.  
9
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming  
aFIFOfollowingaMasterResetwouldbeinconvenient.SeeFigure6and7  
forPartialResettimingdiagrams.  
SIGNALDESCRIPTION  
MASTER RESET (MRS1, MRS2)  
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding  
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1  
memory of the IDT723626/723636/723646 undergoes a complete reset by  
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)  
takingitsassociatedMasterReset(MRS1)inputLOWforatleastfourPortAClock  
(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.TheFIFO2  
memory undergoes a complete reset by taking its associated Master Reset  
(MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock  
(CLKC)LOW-to-HIGHtransitions.TheMasterResetinputscanswitchasyn-  
chronouslytotheclocks.AMasterResetinitializestheassociatedreadandwrite  
pointerstothefirstlocationofthememoryandforcestheFull/InputReadyflag  
(FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/  
ORB)LOW,theAlmost-Emptyflag(AEA,AEB)LOW,andtheAlmost-Fullflag  
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag  
(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraMasterReset,the  
FIFO’sFull/InputReadyflagissetHIGHaftertwoWriteclockcycles.Thenthe  
FIFO is ready to be written to.  
ALOW-to-HIGHtransitiononaFlFO1MasterReset(MRS1,MRS2)input  
latchesthevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhich  
bytesaretransferredthroughportsBandC.ItalsolatchesthevaluesoftheFlag  
Select(FS0,FS1)andSerialProgrammingMode(SPM)inputsforchoosing  
theAlmost-FullandAlmost-Emptyoffsetprogrammingmode.  
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearstheflag  
offsetregistersofFIFO2(X2,Y2).ALOW-to-HIGHtransitionontheFIFO2Master  
Resetinput(MRS2)latchesthevalueoftheBig-Endian(BE)inputforPortsBand  
CandalsolatchesthevaluesoftheFlagSelect(FS0,FS1)andSerialProgramming  
Mode(SPM)inputsforchoosingtheAlmost-FullandAlmost-Emptyoffsetprogram-  
mingmethod(fordetailsseeTable1,FlagProgramming,andAlmost-Emptyand  
Almost-FullFlagOffsetProgrammingsection).TherelevantMasterResettiming  
diagrams can be found in Figure 4 and 5.  
ENDIAN SELECTION  
This is a dual purpose pin. At the time of Master Reset, the BE select  
function is active, permitting a choice of Big- or Little-Endian byte arrange-  
mentfordatawrittentoPortCorreadfromPortB.Thisselectiondetermines  
the order by which bytes (or words) of data are transferred through those  
ports.Forthefollowingillustrations,notethatbothportsBandCareconfigured  
to have a byte (or a word) bus size.  
AHIGHontheBE/FWFTinputwhentheMasterReset(MRS1,MRS2)inputs  
go from LOW to HIGH will select a Big-Endian arrangement. When data is  
movinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)of  
thelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
data is moving in the direction from Port C to Port A, the byte (word) written to  
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong  
word; the byte (word) written to Port C last will be read from Port A as the least  
significant byte (word) of the long word.  
ALOWontheBE/FWFTinputwhentheMasterReset(MRS1,MRS2)inputs  
go from LOW to HIGH will select a Little-Endian arrangement. When data is  
movinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)of  
thelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
data is moving in the direction from Port C to Port A, the byte (word) written to  
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong  
word; the byte (word) written to Port C last will be read from Port A as the most  
significantbyte(word)ofthelongword.RefertoFigures2and3forillustrations  
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master  
Reset) for Endian Select timing diagrams.  
NotethatMBCmustbeHIGHduringMasterReset(untilFFA/IRAandFFC/  
IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master Reset.  
TIMING MODE SELECTION  
PARTIAL RESET (PRS1, PRS2)  
After Master Reset, the FWFT select function is available, permitting a  
choice between two possible timing modes: IDT Standard mode or First  
Word Fall Through (FWFT) mode. Once the Master Reset (MRS1, MRS2)  
inputis HIGH,aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGH  
transitionofCLKA(forFIFO1)andCLKC(forFIFO2)willselectIDTStandard  
mode.ThismodeusestheEmptyFlagfunction(EFA,EFB)toindicatewhether  
ornotthereareanywords presentintheFIFOmemory.Ituses theFullFlag  
function(FFA,FFC)toindicatewhetherornottheFIFOmemoryhasanyfree  
space for writing. In IDT Standard mode, every word read from the FIFO,  
includingthefirst,mustberequestedusingaformalreadoperation.  
OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/  
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and  
CLKC(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady  
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata  
outputs(A0-A35orB0-B17).ItalsousestheInputReadyfunction(IRA,IRC)  
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In  
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata  
TheFIFO1memoryofthesedevicesundergoesalimitedresetbytaking  
its associated Partial Reset (PRS1) input LOW for at least four Port A Clock  
(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.TheFIFO2  
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(PRS2)  
inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock(CLKC)  
LOW-to-HIGHtransitions.ThePartialResetinputscanswitchasynchronously  
totheclocks.APartialResetinitializestheinternalreadandwritepointersand  
forcestheFull/InputReadyflag(FFA/IRA,FFC/IRC)LOW,theEmpty/Output  
Readyflag(EFA/ORA,EFB/ORB)LOW,theAlmost-Emptyflag(AEA,AEB)  
LOW,andtheAlmost-Fullflag(AFA,AFC)HIGH.APartialResetalsoforces  
theMailboxFlag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.Aftera  
PartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteclock  
cycles.  
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming  
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial  
Resetisinitiated,thosesettingswillremainunchangeduponcompletionofthe  
NOTE:  
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with  
unused inputs) must not be left open, rather they must be either HIGH or LOW.  
10  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby complete,thefirstfourwritestoFIFO1donotstoredatainRAMbutloadtheOffset  
performingaformalreadoperation.RefertoFigure4(FIFO1MasterReset) registersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedbytheOffset  
andFigure5(FIFO2MasterReset)forFirstWordFallThroughselecttiming registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723626, IDT723636,  
diagrams.  
orIDT723646,respectively.Thehighestnumberedinputisusedasthemost  
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose significantbitofthebinarynumberineachcase.Validprogrammingvaluesfor  
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation.  
theregistersrangefrom1to252fortheIDT723626;1to508fortheIDT723636;  
and1to1,020fortheIDT723646.AfteralltheOffsetregistersareprogrammed  
fromPortA,thePortCFull/InputReadyflag(FFC/IRC)issetHIGH,andboth  
FIFOsbeginnormaloperation.  
RefertoFigure8foratimingdiagramillustrationforparallelprogramming  
oftheflagoffsetvalues.  
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS  
Four registers in these FIFOs are used to hold the offset values for the  
Almost-EmptyandAlmost-Fullflags.ThePortBAlmost-Emptyflag(AEB)Offset  
registerislabeledX1andthePortAAlmost-Emptyflag(AEA)Offsetregisteris  
labeledX2.ThePortAAlmost-Fullflag(AFA)OffsetregisterislabeledY1and  
thePortCAlmost-Fullflag(AFC)OffsetregisterislabeledY2.Theindexofeach  
register name corresponds to its FIFO number. The Offset registers can be  
loadedwithpresetvaluesduringtheresetofaFIFO,programmedinparallel  
usingtheFIFO’sPortAdatainputs,orprogrammedinserialusingtheSerial  
Data (SD) input (see Table 1).  
SERIAL LOAD  
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master  
ResetwithSPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-  
HIGHtransitionofMRS1andMRS2.Afterthisresetiscomplete,theXandY  
registervaluesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-  
to-HIGHtransitionofCLKAthattheFS1/SENinputisLOW.Thereare32-,36-  
, or 40-bit writes needed to complete the programming for the IDT723626,  
IDT723636,orIDT723646,respectively.Thefourregistersarewritteninthe  
orderY1,X1,Y2andfinally,X2.Thefirst-bitwritestoresthemostsignificantbit  
oftheY1registerandthelast-bitwritestorestheleastsignificantbitoftheX2  
register.Eachregistervaluecanbeprogrammedfrom1to252(IDT723626),  
1 to 508 (IDT723636), or 1 to 1,020 (IDT723646).  
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard  
andFWFTmodes.  
PRESET VALUES  
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers  
with one of the three preset values listed in Table 1, the Serial Program Mode  
(SPM) and at least one of the flag-select inputs must be HIGH during the LOW-  
to-HIGHtransitionofitsMasterReset(MRS1andMRS2)input.Forexample,to  
load the preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH  
when FlFO1 reset (MRS1) returns HIGH. Flag Offset registers associated with  
FIFO2 are loaded with one of the preset values in the same way with FIFO2  
MasterReset(MRS2)toggledsimultaneouslywithFIFO1MasterReset(MRS1).  
For relevant Preset value loading timing diagrams, see Figure 4 and 5.  
WhentheoptiontoprogramtheOffsetregistersseriallyischosen,thePort  
AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.  
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit  
isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFC/  
IRC)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until  
allregisterbitsarewritten.FFC/IRCissetHIGHbytheLOW-to-HIGHtransition  
ofCLKCafterthelastbitis loadedtoallownormalFIFO2operation.  
SeeFigure9timingdiagram,SerialProgrammingoftheAlmost-FullFlag  
andAlmost-EmptyFlagOffsetValuesafterReset(IDTStandardandFWFT  
Modes).  
PARALLEL LOAD FROM PORT A  
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster  
ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW  
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is  
TABLE 1 — FLAG PROGRAMMING  
SPM  
FS1/SEN  
FS0/SD  
MRS1  
MRS2  
X1 AND Y1 REGlSTERS(1)  
X2 AND Y2 REGlSTERS(2)  
H
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
↑
64  
X
H
64  
64  
H
X
↑
16  
X
H
16  
16  
H
X
↑
8
X
H
8
ParallelprogrammingviaPortA  
SerialprogrammingviaSD  
Reserved  
8
ParallelprogrammingviaPortA  
SerialprogrammingviaSD  
Reserved  
H
↑
L
↑
L
L
↑
↑
Reserved  
Reserved  
L
↑
Reserved  
Reserved  
NOTES:  
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.  
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.  
11  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
FIFO WRITE/READ OPERATION  
ThesetupandholdtimeconstraintsforCSAandW/RAwithregardtoCLKA  
as well as CSB with regard to CLKB are only for enabling write and read  
operationsandarenotrelatedtohigh-impedancecontrolofthedataoutputs.  
IfENAis LOWduringa clockcycle, eitherCSA orW/RAmaychange states  
duringthe setupandholdtime windowofthe cycle. This is alsotrue forCSB  
whenRENBis LOW.  
When operating the FIFO in FWFT mode and the Output Ready flag is  
LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregister  
bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag  
HIGH.WhentheOutputReadyflagisHIGH,subsequentdataisclockedtothe  
outputregistersonlywhenareadisselectedusingCSA,W/RA,ENAandMBA  
at Port A or using CSB, RENB and MBB at Port B.  
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause  
the Empty Flag to change state on the second LOW-to-HIGH transition of  
thereadclock.Thedatawordwillnotbeautomaticallysenttotheoutputregister.  
Instead, data residing in the FIFO’s memory array is clocked to the output  
registeronlywhenareadisselectedusingCSAW/RAENAandMBAatPort  
A or using CSB, RENB and MBB at Port B. Relevant write and read timing  
diagramsforPortAcanbefoundinFigure10and15.Relevantreadandwrite  
timingdiagramsforPortBandPortC,togetherwithBus-MatchingandEndian  
Select operations can be found in Figures 11 to 14.  
ThestateofthePortAdata(A0-A35)outputsiscontrolledbyPortAChip  
Select(CSA)andPortAWrite/ReadSelect(W/RA).TheA0-A35outputsare  
intheHigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35  
outputs are active whenbothCSA andW/RAare LOW.  
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH  
transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis  
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs  
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA  
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand  
writesonPortAareindependentofanyconcurrentPortBandPortCoperation.  
ThestateofthePortBdata(B0-B17)outputsiscontrolledbythePortBChip  
Select(CSB).TheB0-B17outputsareinthehigh-impedancestatewhenCSB  
is HIGH. The B0-B17 outputs are active when CSB is LOW.  
DataisreadfromFIFO1totheB0-B17outputsbyaLOW-to-HIGHtransition  
of CLKB when CSB is LOW, RENB is HIGH, MBB is LOW and EFB/ORB is  
HIGH(seeTable3).FIFOreadsonPortBareindependentofanyconcurrent  
Port A and Port C operations.  
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH  
transition of CLKC when WENB is HIGH, MBC is LOW, and FFC/IRC is HIGH  
(see Table 4). FIFOwrites onPortCare independentofanyconcurrentPortA  
and Port B operation.  
TABLE 2 — PORT A ENABLE FUNCTION TABLE  
CSA  
W/RA  
ENA  
MBA  
CLKA  
DATAA(A0-A35)I/O  
PORT FUNCTION  
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
High-Impedance  
Input  
None  
None  
H
H
L
Input  
FIFO1 write  
Mail1write  
H
L
↑
Input  
X
↑
Output  
Output  
Output  
Output  
None  
L
H
L
L
FIFO2read  
None  
L
H
H
X
↑
L
H
Mail2 read (set MBF2 HIGH)  
TABLE 3 — PORT B ENABLE FUNCTION TABLE  
CSB  
RENB  
MBB  
CLKB  
DATA B (B0-B17) OUTPUTS  
PORT FUNCTION  
H
L
L
L
L
X
L
X
L
X
X
↑
High-Impedance  
Output  
None  
None  
H
L
L
Output  
FIFO1read  
H
H
X
↑
Output  
None  
H
Output  
Mail1 read (set MBF1 HIGH)  
TABLE 4 — PORT C ENABLE FUNCTION TABLE  
WENC  
MBC  
CLKC  
DATA C (C0-C17) INPUTS  
PORT FUNCTION  
H
H
L
L
L
H
L
↑
Input  
Input  
Input  
Input  
FIFO2 write  
Mail2write  
None  
↑
X
X
H
None  
12  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
SYNCHRONIZED FIFO FLAGS  
pointer and read pointer comparator that indicates when the FIFO memory  
status is empty, empty+1, or empty+2.  
Each FIFO is synchronized to its port clock through at least two flip-flop  
stages. This is done to improve flag signal reliability by reducing the probability  
of metastable events when CLKA operates asynchronously with respect to  
eitherCLKBorCLKC. EFA/ORA,AEA, FFA/IRA, andAFA are synchronizedto  
CLKA. EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC are  
synchronized to CLKC. Tables 5 and 6 show the relationship of each port flag  
to FIFO1 and FIFO2.  
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted  
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag  
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in  
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles  
oftheportclockthatreadsdatafromtheFIFOhavenotelapsedsincethetime  
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthe  
thirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simultaneously  
forcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFOoutput  
register.  
In IDT Standard mode, from the time a word is written to a FIFO, the  
Empty Flag will indicate the presence of data available for reading in a  
minimum of two cycles of the Empty Flag synchronizing clock. Therefore,  
anEmptyFlagisLOWifawordinmemoryisthenextdatatobesenttotheFlFO  
outputregisterandtwocyclesoftheportClockthatreadsdatafromtheFIFO  
havenotelapsedsincethetimethewordwaswritten.TheEmptyFlagofthe  
FIFOremainsLOWuntilthesecondLOW-to-HIGHtransitionofthesynchro-  
nizing clock occurs, forcing the Empty Flag HIGH; only then can data be read.  
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing  
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs  
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle  
can be the first synchronization cycle (see Figures 16, 17, 18 and 19).  
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)  
Thesearedualpurposeflags.IntheFWFTmode,theOutputReady(ORA,  
ORB)functionisselected.WhentheOutputReadyflagisHIGH,newdatais  
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the  
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO  
reads are ignored.  
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.  
Whenthe EmptyFlagis HIGH, data is available inthe FIFO’s RAMmemory  
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious  
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare  
ignored.  
The Empty/Output Ready flag of a FIFO is synchronized to the port clock  
thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,the  
FIFOreadpointeris incrementedeachtimeanewwordis clockedtoits output  
register.ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite  
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
to CLKB  
Synchronized  
to CLKA  
Number of Words in FIFO Memory(1,2)  
IDT723626(3)  
IDT723636(3)  
IDT723646(3)  
EFB/ORB  
AEB  
AFA  
H
FFA/IRA  
0
1toX1  
0
1toX1  
0
1toX1  
L
H
H
H
H
L
L
H
H
H
H
L
H
(X1+1)to[256-(Y1+1)]  
(256-Y1)to255  
256  
(X1+1)to[512-(Y1+1)]  
(512-Y1)to511  
512  
(X1+1)to[1,024-(Y1+1)]  
(1,024-Y1)to1,023  
1,024  
H
H
H
H
L
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register  
(no read operation necessary), it is not included in the FIFO memory count.  
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.  
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.  
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
to CLKA  
Synchronized  
to CLKC  
Number of Words in FIFO Memory(1,2)  
IDT723626(3)  
IDT723636(3)  
IDT723646(3)  
EFA/ORA  
AEA  
AFC  
H
FFC/IRC  
0
1toX2  
0
1toX2  
0
1toX2  
L
H
H
H
H
L
L
H
H
H
H
L
H
(X2+1)to[256-(Y2+1)]  
(256-Y2)to255  
256  
(X2+1)to[512-(Y2+1)]  
(512-Y2)to511  
512  
(X2+1)to[1,024-(Y2+1)]  
(1,024-Y2)to1,023  
1,024  
H
H
H
H
L
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation  
necessary), it is not included in the FIFO memory count.  
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.  
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.  
13  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)  
programmedfromPortA,orprogrammedserially(seeAlmost-Emptyflagand  
Almost-Fullflagoffsetprogrammingsection).AnAlmost-FullflagisLOWwhen  
the number of words in its FIFO is greater than or equal to (256-Y), (512-Y),  
or (1,024-Y) for the IDT723626, IDT723636, or IDT723646 respectively. An  
Almost-Full flag is HIGH when the number of words in its FIFO is less than or  
equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723626,  
IDT723636, or IDT723646 respectively. Note that a data word present in the  
FIFO output register has been read from memory.  
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare  
requiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewleveloffill.  
Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]or  
lesswordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed  
sincethereadthatreducedthenumberofwordsinmemoryto[256/512/1,024-  
(Y+1)].AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGHtransition  
ofitssynchronizingclockaftertheFIFOreadthatreducesthenumberofwords  
inmemoryto[256/512/1,024-(Y+1)].ALOW-to-HIGHtransitionofanAlmost-  
Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccursat  
time tSKEW2 or greater after the read that reduces the number of words in  
memoryto[256/512/1,024-(Y+1)].Otherwise,thesubsequentsynchronizing  
clockcycle maybe the firstsynchronizationcycle (see Figures 26and27).  
These are dualpurpose flags. InFWFTmode, the InputReady(IRAand  
IRC)functionisselected.InIDTStandardmode,theFullFlag(FFAandFFC)  
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis  
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory  
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites  
to the FIFO are ignored.  
The Full/Input Ready flag of a FlFO is synchronized to the port clock that  
writes data to its array. For both FWFT and IDT Standard modes, each time a  
wordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachinethat  
controls a Full/Input Ready flag monitors a write pointer and read pointer  
comparator that indicates when the FlFO memory status is full, full-1, or full-2.  
Fromthetimeawordis readfromaFIFO, its previous memorylocationis ready  
to be written to in a minimum of two cycles of the Full/Input Ready flag  
synchronizingclock.Therefore,anFull/InputReadyflagis LOWifless thantwo  
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the  
nextmemorywritelocationhasbeenread.ThesecondLOW-to-HIGHtransition  
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input  
Ready flag HIGH.  
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing  
clock begins the first synchronization cycle of a read if the clock transition  
occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent  
clock cycle can be the first synchronization cycle (see Figures 20, 21, 22,  
and 23).  
MAILBOX REGISTERS  
Each FIFO has an 18-bit bypass register allowing the passage of  
commandandcontrolinformationfromPortAtoPortBorfromPortCtoPort  
Awithoutputtingitinqueue.TheMailboxSelect(MBA,MBBandMBC)inputs  
choosebetweenamailregisterandaFIFOforaportdatatransferoperation.  
TheusablewidthofboththeMail1andMail2registersmatchestheselectedbus  
size for ports B and C.  
When sending data from Port A to Port B via the Mail1 Register, the  
followingisthecase:ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1  
Registerwhena PortAwrite is selectedbyCSA, W/RA, andENAwithMBA  
HIGH.IftheselectedPortBbussizeis18bits,thentheusablewidthoftheMail1  
Register employs data lines A0-A17. (In this case, A18-A35 are don’t care  
inputs.)IftheselectedPortBbussizeis9bits,thentheusablewidthoftheMail1  
RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’tcareinputs.)  
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing  
isthecase:ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register  
whenaPortCwriteisselectedbyWENCwithMBCHIGH.IftheselectedPort  
Cbussizeis18bits,thentheusablewidthoftheMail2Registeremploysdata  
linesC0-C17.IftheselectedPortCbussizeis9bits,thentheusablewidthof  
theMail2RegisteremploysdatalinesC0-C8.(Inthiscase,C9-C17aredon’t  
careinputs.)  
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)  
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.  
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe  
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe  
mailregisterwhentheportmailboxselectinputisHIGH.  
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition  
onCLKBwhenaPortBreadisselectedbyCSB,andRENBwithMBBHIGH.  
Foran18-bitbus size,18bits ofmailboxdataareplacedonB0-B17.Forthe  
9-bitbussize,9bitsofmailboxdataareplacedonB0-B8.(Inthiscase,B9-B17  
areindeterminate.)  
ALMOST-EMPTYFLAGS(AEA,AEB)  
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads  
data from its array. The state machine that controls an Almost-Empty flag  
monitors a write pointer and read pointer comparator that indicates when the  
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.  
The almost-empty state is defined by the contents of register X1 for AEB and  
registerX2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFO  
reset,programmedfromPortA,orprogrammedserially(seeAlmost-Emptyflag  
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW  
when its FIFO contains X or less words and is HIGH when its FIFO contains  
(X+1)ormorewords.AdatawordpresentintheFIFOoutputregisterhasbeen  
read from memory.  
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing  
clock are required after a FIFO write for its Almost-Empty flag to reflect the  
newleveloffill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)  
ormorewordsremainsLOWiftwocyclesofitssynchronizingclockhavenot  
elapsedsincethewritethatfilledthememorytothe(X+1)level.AnAlmost-Empty  
flagissetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock  
aftertheFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition  
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization  
cycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)  
words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst  
synchronization cycle. (See Figures 24 and 25).  
ALMOST-FULL FLAGS (AFA, AFC)  
The Almost-Full flag of a FIFO is synchronized to the port clock that  
writes data to its array. The state machine that controls an Almost-Full flag  
monitors a write pointer and read pointer comparator that indicates when  
the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The  
almost-fullstateisdefinedbythecontentsofregisterY1forAFAandregisterY2  
for AFC. These registers are loaded with preset values during a FlFO reset,  
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition  
onCLKAwhena PortAreadis selectedbyCSA, W/RA, andENAwithMBA  
HIGH.Thedatainamailregisterremainsintactafteritisreadandchangesonly  
whennewdataiswrittentotheregister.Foran18-bitbussize,18bitsofmailbox  
14  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
data appearonA18-A35. (Inthis case, A0-A17are indeterminate.)Fora 9- The Endian Select operations are not available when transferring data via  
bitbussize,9bitsofmailboxdataappearonA18-A26.(Inthiscase,A0-A17 mailboxregisters.Furthermore,boththeword-andbyte-sizebusselectionslimit  
andA27-A35areindeterminate.)  
thewidthofthedatabusthatcanbeusedformailregisteroperations.Inthiscase,  
Thedatainamailregisterremainsintactafteritisreadandchangesonly onlythosebytelanesbelongingtotheselectedword-orbyte-sizebuscancarry  
whennewdataiswrittentotheregister.TheEndianSelectfeaturehasnoeffect mailboxdata.Theremainingdataoutputswillbeindeterminate.Theremaining  
onmailboxdata.  
data inputs will be don’t care inputs. For example, when a word-size bus is  
NotethatMBCmustbeHIGHduringMasterReset(untilFFA/IRAandFFC/ selectedonPortB,thenmailboxdatacanbetransmittedonlyfromA0-A17to  
IRCgoHIGH.MBAandMBBaredon'tcareinputsduringMasterReset.For B0-B17.Whenabyte-sizebusisselectedonPortB,thenmailboxdatacanbe  
mailregistersandmailregisterflagtimingdiagrams,seeFigure28and29. transmitted only from A0-A8 to B0-B8. Similarly, when a word-size bus is  
selectedonPortC,thenmailboxdatacanbetransmittedonlyfromC0-C17to  
BUS SIZING  
A18-A35.Whenabyte-sizebusisselectedonPortC,thenmailboxdatacan  
be transmitted only from C0-C8 to A18-A26. (See Figures 28 and 29).  
Port B may be configured in either an 18-bit word or a 9-bit byte format  
fordata readfromFIFO1. PortCmaybe configuredineitheran18-bitword  
ora9-bitbyteformatfordatawrittentoFIFO2.Thebussizecanbeselected  
independentlyforPorts BandC. The levelappliedtothe PortBSize Select  
BUS-MATCHING FIFO1 READS  
Data is read from the FIFO1 RAM in 36-bit long word increments. Since  
(SIZEB) input determines the Port B bus size and the level applied to the Port B can have a byte or word size, only the first one or two bytes appear  
Port C Size Select (SIZEC) input determines the Port C bus size. These onthe selectedportionofthe FIFO1outputregister, withthe restofthe long  
levels shouldbestaticthroughoutFIFOoperation.Bothbus sizeselections word stored in auxiliary registers. In this case, subsequent FIFO1 reads  
are implemented at the completion of Master Reset, by the time the Full/ output the rest of the long word to the FIFO1 output register in the order  
Input Ready flag is set HIGH, as shown in Figures 2 and 3.  
shown by Figure 2.  
Two different methods for sequencing data transfer are available for  
When reading data from FIFO1 in byte format, the unused B9-B17  
Ports BandCregardless ofwhetherthe bus size selectionis byte-orword- outputs are indeterminate.  
size. They are referred to as Big-Endian (most significant byte first) and  
Little-Endian (least significant byte first). The level applied to the Big- BUS-MATCHING FIFO2 WRITES  
Endian Select (BE) input during the LOW-to-HIGH transition of MRS1 and  
MRS2selectstheendianmethodthatwillbeactiveduringFIFOoperation.This  
selectionappliestobothportsBandC.Theendianmethodisimplementedat  
thecompletionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH,  
as shown in Figures 2 and 3 (see Endian Selection section).  
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories  
onthesedevices.Bus-matchingoperationsaredoneafterdataisreadfromthe  
FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port C).  
Data is written to the FIFO2 RAM in 36-bit long word increments. Data  
writtentoFIFO2witha byte orwordbus size stores the initialbytes orwords  
inauxiliaryregisters. The CLKCrisingedge thatwrites the fourthbyte orthe  
second word of long word to FIFO2 also stores the entire long word in the  
FIFO2 memory. The bytes are arranged in the manner shown in Figure 3.  
When writing data to FIFO2 in byte format, the unused C9-C17 inputs  
are don't care inputs.  
15  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
A35A27  
A26A18  
A17A9  
A8A0  
BYTE ORDER ON PORT A:  
D
A
B
C
Write to FIFO1  
BYTE ORDER ON PORT B:  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
H
SIZEB  
L
A
B
B17B9  
B8B0  
C
D
(b) WORD SIZE  
BIG ENDIAN  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
L
SIZEB  
L
C
D
B17B9  
B8B0  
A
B
(c) WORD SIZE  
LITTLE ENDIAN  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
H
SIZEB  
H
A
B17B9  
B17B9  
B8B0  
B
B8B0  
3rd: Read from FIFO1  
4th: Read from FIFO1  
C
B17B9  
B8B0  
D
(d) BYTE SIZE  
BIG ENDIAN  
B17B9  
B8B0  
BE SIZEB  
1st: Read from FIFO1  
2nd: Read from FIFO1  
D
L
H
B17B9  
B8B0  
C
B17B9  
B17B9  
B8B0  
3rd: Read from FIFO1  
B
B8B0  
4th: Read from FIFO1  
A
(e) BYTE SIZE  
LITTLE ENDIAN  
3271 drw03  
Figure 2. Port B Bus Sizing  
16  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
A35A27  
A26A18  
A17A9  
A8A0  
BYTE ORDER ON PORT A:  
D
A
B
C
Write to FIFO1  
BYTE ORDER ON PORT B:  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
H
SIZEB  
L
A
B
B17B9  
B8B0  
C
D
(b) WORD SIZE  
BIG ENDIAN  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
L
SIZEB  
L
C
D
B17B9  
B8B0  
A
B
(c) WORD SIZE  
LITTLE ENDIAN  
B17B9  
B8B0  
1st: Read from FIFO1  
2nd: Read from FIFO1  
BE  
H
SIZEB  
H
A
B17B9  
B17B9  
B8B0  
B
B8B0  
3rd: Read from FIFO1  
4th: Read from FIFO1  
C
B17B9  
B8B0  
D
(d) BYTE SIZE  
BIG ENDIAN  
B17B9  
B8B0  
BE SIZEB  
1st: Read from FIFO1  
2nd: Read from FIFO1  
D
L
H
B17B9  
B8B0  
C
B17B9  
B17B9  
B8B0  
3rd: Read from FIFO1  
B
B8B0  
4th: Read from FIFO1  
A
(e) BYTE SIZE  
LITTLE ENDIAN  
3271 drw03  
Figure 3. Port C Bus Sizing  
17  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKA  
CLKB  
1
2
tRSTH  
t
RSTS  
MRS1  
tBEH  
t
BES  
tFWS  
BE/FWFT  
BE  
0,1  
FWFT  
t
SPMS  
t
SPMH  
SPM  
FS1,FS0  
FFA/IRA  
t
FSS  
tFSH  
t
WFF  
t
WFF  
(2)  
t
REF  
EFB/ORB  
t
RSF  
AEB  
t
RSF  
AFA  
t
RSF  
MBF1  
3271 drw05  
NOTES:  
1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.  
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.  
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)  
1
2
CLKC  
CLKA  
tRSTH  
t
RSTS  
MRS2(3)  
t
BES  
tBEH  
tFWS  
BE  
BE/FWFT  
FWFT  
t
SPMS  
t
SPMH  
SPM  
FS1,FS0  
FFC/IRC  
EFA/ORA  
t
FSS  
t
FSH  
0,1  
t
WFF  
tWFF  
(2)  
REF  
t
t
RSF  
RSF  
AEA  
AFC  
t
t
RSF  
MBF2  
3271 drw06  
NOTES:  
1. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.  
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.  
3. MRS2 must toggle simultaneously with MRS1.  
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)  
18  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
1
2
CLKA  
CLKB  
t
RSTS  
tRSTH  
PRS1  
t
WFF  
t
WFF  
FFA/IRA  
(2)  
REF  
t
EFB/ORB  
AEB  
t
t
RSF  
RSF  
AFA  
t
RSF  
MBF1  
3271 drw07  
NOTES:  
1. MRS1 must be HIGH during Partial Reset.  
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.  
Figure 6. FIFO1 Partial Reset (IDT Standard and FWFT Modes)  
CLKC  
CLKA  
tRSTH  
t
RSTS  
PRS2  
t
WFF  
t
WFF  
FFC/IRC  
(2)  
REF  
t
EFA/ORA  
t
RSF  
AEA  
t
RSF  
AFC  
t
RSF  
MBF1  
3271 drw08  
NOTES:  
1. MRS2 must be HIGH during Partial Reset.  
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.  
Figure 7. FIFO2 Partial Reset (IDT Standard and FWFT Modes)  
19  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKA  
4
MRS1,  
MRS2  
tFSS  
tFSS  
tFSH  
tFSH  
SPM  
0,0  
FS1,FS0  
tWFF  
FFA/IRA  
(1)  
tSKEW1  
tENS2  
tDH  
tENH  
ENA  
tDS  
A0-A35  
AEA Offset  
AFA Offset  
AEB Offset  
(X1)  
AFC Offset  
(Y2)  
First Word to FIFO1  
(X2)  
(Y1)  
CLKC  
1
2
tWFF  
FFC/IRC  
3271 drw09  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA  
and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.  
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.  
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)  
CLKA  
4
MRS1,  
MRS2  
t
FSH  
t
FSS  
SPM  
t
WFF  
(1)  
tSKEW  
FFA/IRA  
tSENS  
tSENH  
t
FSS  
tSENS  
tSENH  
tSPH  
FS1/SEN  
tSDS  
tSDH  
tSDS  
tSDH  
FS0/SD(3)  
AFA Offset  
(Y1) MSB  
AEA Offset  
(X2) LSB  
CLKC  
4
t
WFF  
FFC/IRC  
3271 drw10  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA  
and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.  
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.  
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).  
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)  
20  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
FFA/IRA HIGH  
t
ENS1  
t
ENH  
ENH  
CSA  
tENS1  
t
W/RA  
tENS2  
tENH  
MBA  
ENA  
tENS2  
tENS2  
tENS2  
tENH  
tENH  
tENH  
tDH  
tDS  
A0-A35  
W1(1)  
W2(1)  
No Operation  
3271 drw11  
NOTE:  
1. Written to FIFO1.  
Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
CLKC  
FFC/IRC  
HIGH  
t
ENS2  
t
ENS2  
ENS2  
t
ENH  
t
ENH  
MBC  
t
ENS2  
t
t
ENH  
tENH  
WENC  
tDH  
tDS  
C0-C17  
3271 drw12  
DATA SIZE TABLE FOR WORD WRITES TO FIFO2  
SIZE MODE(1)  
WRITE  
NO.  
DATA WRITTEN  
TO FIFO2  
DATA READ FROM FIFO2  
SIZEC  
BE  
C17-C9  
C8-C0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
L
H
1
2
A
C
B
D
A
B
C
D
L
L
1
2
C
A
D
B
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.  
Figure 11. Port C Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
21  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKC  
FFC/IRC HIGH  
t
ENS2  
t
ENH  
ENH  
t
ENH  
MBC  
tENS2  
t
t
ENS2  
t
ENH  
WENC  
C0-C8  
tDS  
tDH  
3271 drw13  
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2  
SIZE MODE(1)  
WRITE  
NO.  
DATA WRITTEN  
TO FIFO2  
DATA READ FROM FIFO2  
SIZEC  
H
BE  
H
C8-C0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
D
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
A
A
B
B
C
C
H
L
D
NOTE:  
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.  
Figure 12. Port C Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
CLKB  
EFB/ORB HIGH  
CSB  
MBB  
tENS2  
tENH  
RENB  
No Operation  
Read 2  
tDIS  
t
A
t
MDV  
t
A
t
EN  
B0-B17  
Previous Data  
Read 1  
Read 2  
(Standard Mode)  
OR  
tDIS  
t
MDV  
t
A
t
A
tEN  
B0-B17  
(FWFT Mode)  
Read 1  
Read 3  
3271 drw14  
DATA SIZE TABLE FOR WORD READS FROM FIFO1  
SIZE MODE(1)  
DATA WRITTEN TO FIFO1  
READ  
NO.  
DATA READ FROM FIFO1  
SIZEB  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B17-B9  
B8-B0  
B
H
H
A
B
C
D
1
2
1
2
A
C
C
A
D
H
L
A
B
C
D
D
B
NOTE:  
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.  
Figure 13. Port B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
22  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKB  
EFB/ORB HIGH  
CSB  
MBB  
tENS2  
tENH  
RENB  
No Operation  
t
DIS  
DIS  
t
MDV  
t
A
t
A
t
A
tA  
t
EN  
B0-B8  
Previous Data  
Read 2  
Read 3  
Read 4  
Read 5  
Read 1  
(Standard Mode)  
t
t
MDV  
tA  
tA  
t
A
t
A
OR  
t
EN  
B0-B8  
Read 1  
Read 2  
Read 3  
Read 4  
(FWFT Mode)  
3271 drw15  
NOTE:  
1. Unused bytes B9-B17 are indeterminate for byte-size reads.  
DATA SIZE TABLE FOR BYTE READS FROM FIFO1  
SIZE MODE(1)  
DATA WRITTEN TO FIFO1  
READ  
A8-A0  
DATA READ FROM FIFO1  
B8-B0  
SIZEB  
BE  
A35-A27  
A26-A18  
A17-A9  
NO.  
1
2
3
4
A
B
C
D
H
H
A
B
C
C
D
D
1
2
3
4
D
C
B
A
H
L
A
B
NOTE:  
1. BE is selected at Master Reset; SIZEB must be static throughout device operation.  
Figure 14. Port B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
tCLK  
tCLKH  
tCLKL  
CLKA  
HIGH  
EFA/ORA  
CSA  
W/RA  
MBA  
tENS2  
tENS2  
tENH  
tENH  
tENH  
tENS2  
ENA  
No Operation  
W2(1)  
t
MDV  
t
DIS  
t
A
tA  
t
EN  
A0-A35  
W1(1)  
W2(1)  
Previous Data  
(
Standard Mode)  
t
DIS  
t
MDV  
OR  
tA  
t
A
t
EN  
A0-A35  
(FWFT Mode)  
W3(1)  
W1(1)  
3271 drw16  
NOTE:  
1. Read From FIFO2.  
Figure 15. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
23  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
t
CLK  
t
CLKL  
t
CLKH  
CLKA  
LOW  
HIGH  
CSA  
WRA  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
IRA  
HIGH  
tDS  
tDH  
A0-A35  
W1  
t
CLKtCLKL  
(1)  
SKEW1  
t
CLKH  
t
CLKB  
3
1
2
t
REF  
t
REF  
FIFO1 Empty  
LOW  
ORB  
CSB  
MBB  
LOW  
tENS2  
tENH  
RENB  
tA  
tA  
Read 1  
Read 2  
B0-B17  
3271 drw17  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB  
cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may  
occur one CLKB cycle later than shown.  
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).  
Figure 16. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)  
24  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
t
CLK  
t
CLKL  
t
CLKH  
CLKA  
LOW  
HIGH  
CSA  
WRA  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
FFA  
HIGH  
tDS  
tDH  
A0-A35  
W1  
t
CLK  
(1)  
SKEW1  
t
CLKH  
tCLKL  
t
CLKB  
1
2
t
REF  
t
REF  
EFB  
CSB  
MBB  
FIFO1 Empty  
LOW  
LOW  
tENS2  
tENH  
RENB  
B0-B17  
NOTES:  
tA  
tA  
Read 1  
Read 2  
3271 drw18  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.  
2. If Port B size is word or byte, ERB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).  
Figure 17. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)  
25  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
t
CLK  
CLKH  
tCLKL  
t
CLKC  
t
ENS2  
ENS2  
t
ENH  
MBC  
t
t
ENH  
WENC  
IRC  
HIGH  
tDH  
tDS  
tDH  
t
DS  
Write 1  
Write 2  
C0-C17  
t
CLK  
(1)  
SKEW1  
t
CLKH  
t
tCLKL  
CLKA  
1
2
3
t
REF  
t
REF  
ORA  
CSA  
FIFO2 Empty  
LOW  
LOW  
W/RA  
MBA  
LOW  
tENS2  
tENH  
ENA  
A0-A35  
NOTES:  
tA  
Old Data in FIFO2 Output Register  
W1  
3271 drw19  
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.  
If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA  
cycle later than shown.  
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.  
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)  
26  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
t
CLK  
CLKH  
tCLKL  
t
CLKC  
t
ENS2  
ENS2  
t
ENH  
MBC  
t
t
ENH  
WENC  
FFC  
HIGH  
tDS  
tDH  
t
DS  
tDH  
Write 1  
Write 2  
C0-C17  
t
CLK  
(1)  
SKEW1  
t
CLKH  
tCLKL  
t
1
2
CLKA  
t
REF  
t
REF  
EFA  
CSA  
FIFO2 Empty  
LOW  
LOW  
LOW  
W/RA  
MBA  
tENS2  
tENH  
ENA  
tA  
A0-A35  
W1  
3271 drw20  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge  
and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.  
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.  
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)  
27  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
tCLK  
tCLKH  
tCLKL  
CLKB  
CSB LOW  
LOW  
MBB  
tENS  
tENH  
RENB  
ORB  
HIGH  
tA  
tA  
Read 1  
Read 2  
B0-B17  
Previous Word in  
FIFO1 Output Register  
(1)  
tSKEW1  
t
CLK tCLKL  
tCLKH  
CLKA  
IRA  
1
2
t
WFF  
t
WFF  
FIFO1 Full  
CSA LOW  
W/RA HIGH  
tENH  
tENS  
MBA  
tENS  
tENH  
ENA  
tDS  
tDH  
Write  
A0-A35  
3271 drw21  
NOTE:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and  
rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).  
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)  
28  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
tCLK  
tCLKH  
tCLKL  
CLKB  
CSB  
LOW  
LOW  
MBB  
tENS2  
tENH  
RENB  
EFB  
HIGH  
tA  
tA  
Read 1  
Read 2  
B0-B17  
Previous Word in  
FIFO1 Output Register  
(1)  
tSKEW1  
t
t
CLKH CLK tCLKL  
CLKA  
1
2
t
WFF  
t
WFF  
FFA  
FIFO1 Full  
CSA LOW  
W/RA  
HIGH  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
tDS  
tDH  
Write  
A0-A35  
3271 drw22  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge  
and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively (the word-size case is shown).  
Figure 21. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)  
29  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
CSA  
LOW  
LOW  
W/RA  
LOW  
MBA  
ENA  
tENS2  
tENH  
ORA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
SKEW1  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
t
tCLKL  
tCLKH  
CLKC  
IRC  
1
2
t
WFF  
t
WFF  
FIFO2 Full  
t
ENS2  
ENS2  
t
ENH  
MBC  
WENC  
C0-C17  
t
t
ENH  
tDS  
tDS  
tDH  
tDH  
Write  
3271 drw 23  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge  
and rising CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.  
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).  
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)  
30  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
tCLK  
tCLKH  
tCLKL  
CLKA  
CSA  
LOW  
LOW  
W/RA  
LOW  
MBA  
ENA  
tENS2  
tENH  
EFA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
CLKC  
1
2
t
WFF  
tWFF  
FFC FIFO2 Full  
tENS2  
tENH  
MBC  
ENC  
tENS2  
tENH  
tDH  
tDS  
tDS  
tDH  
Write  
C0-C17  
3271 drw24  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge  
and rising CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.  
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).  
Figure 23. FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)  
CLKA  
tENS2  
tENH  
ENA  
(1)  
tSKEW2  
CLKB  
1
2
t
PAE  
t
PAE  
AEB  
X1 Word in FIFO1  
(X1+1) Words in FIFO1  
ENS2  
t
tENH  
RENB  
3271 drw25  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 24. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)  
31  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKC  
tENH  
t
ENS2  
t
ENS2  
WENC  
CLKA  
(1)  
tSKEW2  
1
2
t
PAE  
t
PAE  
AEA  
X2 Words in FIFO2  
(X2+1) Words in FIFO2  
ENS2  
t
tENH  
ENA  
3271 drw26  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge  
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.  
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.  
Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)  
(1)  
tSKEW2  
1
2
CLKA  
ENA  
tENS2  
tENH  
t
PAF  
tPAF  
(D-Y1) Words in FIFO1  
ENH  
[D-(Y1+1)] Words in FIFO1  
AFA  
CLKB  
t
tENS2  
RENB  
3271 drw27  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT723626, 512 for the IDT723636, 1,024 for the IDT723646.  
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.  
Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)  
(1)  
tSKEW2  
1
2
CLKC  
tENH  
tENS2  
WENC  
AFC  
t
PAF  
t
PAF  
(D-Y2) Words in FIFO2  
[D-(Y2+1)] Words in FIFO2  
CLKA  
tENS2  
tENH  
ENA  
3271 drw28  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge  
and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.  
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT723626, 512 for the IDT723636, 1,024 for the IDT723646.  
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.  
Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)  
32  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
CLKA  
tENS1  
tENH  
CSA  
W/RA  
MBA  
ENA  
t
ENS1  
t
ENH  
tENS2  
t
ENH  
ENH  
tENS2  
t
tDH  
t
DS  
W1  
A0-A35  
CLKB  
MBF1  
t
PMF  
t
PMF  
CSB  
tENS2  
MBB  
tENH  
RENB  
t
PMR  
tDIS  
tEN  
t
MDV  
B0-B17  
W1 (Remains valid in Mail1 Register after read)  
FIFO1 Output Register  
3271 drw29  
NOTE:  
1. IfPortBis configuredforwordsize, data canbe writtentothe Mail1registerusingA0-A17(A18-A35are don'tcare inputs). Inthis firstcase B0-B17willhave validdata. IfPortBis configured  
for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will be indeterminate).  
Figure 28. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)  
CLKC  
tENS2  
tENH  
MBC  
ENC  
tENS2  
tENH  
tDH  
tDS  
C0-C17  
CLKA  
W1  
t
PMF  
t
PMF  
MBF2  
CSA  
W/RA  
MBA  
ENA  
tENS2  
tENH  
t
PMR  
tEN  
tDIS  
t
MDV  
A0-A35  
W1 (Remains valid in Mail2 Register after read)  
FIFO2 Output Register  
3271 drw30  
NOTE:  
1. IfPortCis configuredforwordsize, data canbe writtentothe Mail2registerusingC0-C17. Inthis firstcase, A18-A35willhave validdata (A0-A17willbe indeterminate). IfPortCis configured  
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be  
indeterminate).  
Figure 29. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)  
33  
IDT723626/723636/723646CMOSTRIPLEBUSSyncFIFO™  
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2  
COMMERCIAL TEMPERATURE RANGE  
PARAMETER MEASUREMENT INFORMATION  
5V  
1.1 kΩ  
From Output  
Under Test  
30 pF(1)  
680Ω  
PROPAGATION DELAY  
LOAD CIRCUIT  
3V  
3V  
Timing  
Input  
1.5V  
High-Level  
1.5V  
1.5V  
Input  
GND  
1.5V  
1.5V  
GND  
3V  
t
S
th  
t
W
3V  
Data,  
Enable  
Input  
1.5V  
1.5V  
Low-Level  
GND  
Input  
GND  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
VOLTAGE WAVEFORMS  
PULSE DURATIONS  
3V  
Output  
Enable  
1.5V  
1.5V  
t
PZL  
GND  
t
PLZ  
3V  
GND  
≈
3V  
Input  
1.5V  
1.5V  
1.5V  
Low-Level  
Output  
V
OL  
t
PD  
t
PZH  
tPD  
V
OH  
V
OH  
In-Phase  
Output  
1.5V  
1.5V  
High-Level  
Output  
1.5V  
V
t
PHZ  
OL  
≈ OV  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
3271 drw31  
NOTE:  
1. Includes probe and jig capacitance.  
Figure 30. Load Circuit and Voltage Waveforms  
34  
ORDERINGINFORMATION  
IDT  
XXXXXX  
X
XX  
XX  
X
Device Type Power  
Speed  
Package  
Process/  
Temperature  
Range  
BLANK  
PF  
Commercial (0°C to +70°C)  
Thin Quad Flat Pack (TQFP, PK128-1)  
12  
15  
Clock Cycle Time (tCLK  
)
Commercial Only  
Low Power  
Speed in Nanoseconds  
L
723626 256 x 36 x 2 Triple Bus SyncFIFO with Bus-Matching  
723636 512 x 36 x 2 Triple Bus SyncFIFO with Bus-Matching  
723646 1,024 x 36 x 2 Triple Bus SyncFIFO with Bus-Matching  
3271 drw32  
NOTE:  
1. Industrial temperature range is available by special order.  
DATASHEETDOCUMENTHISTORY  
10/06/2000  
12/12/2000  
03/22/2001  
08/14/2001  
pgs. 1, 2, 6, 8, 9, 12, 14, and 35.  
pg. 21.  
pgs. 6 and 7.  
pgs. 1, 6, 8, 9 and 35.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
408-360-1753  
email:FIFOhelp@idt.com  
www.idt.com  
35  

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