IDT723663L20PF [IDT]
FIFO, 4KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128;
| 型号： | IDT723663L20PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总29页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncFIFOTM
WITH BUS-MATCHING
2,048 x 36, 4,096 x 36,
8,192 x 36
PRELIMINARY
IDT723653
IDT723663
IDT723673
• Big- or Little-Endian format for word and byte bus sizes
• Retransmit Capability
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
FEATURES:
• Memory storage capacity:
IDT723653
IDT723663
IDT723673
–
–
–
2,048 x 36
4,096 x 36
8,192 x 36
• Clock frequencies up to 83 MHz (8 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible with the lower density parts, IDT723623/723633/
723643
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
ENA
Logic
MBA
36
RAM ARRAY
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
2,048 x 36
4,096 x 36
8,192 x 36
RS1
RS2
PRS
36
RT
RTM
FIFO
Retransmit
Logic
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
FS2
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
13
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
5610 drw01
MBF2
TheSyncFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MARCH 2001
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc.
DSC-5610/2
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
DESCRIPTION:
TheIDT723653/723663/723673isamonolithic,high-speed,low-power,
CMOSunidirectionalSynchronous (clocked)FIFOmemorywhichsupports
clockfrequenciesupto83MHzandhasreadaccesstimesasfastas8ns.The
2,048/4,096/8,192x36dual-portSRAMFIFObuffersdatafromPortAtoPort
B.FIFOdataonPortBcanoutputin36-bit,18-bit,or9-bitformatswithachoice
ofBig-orLittle-Endianconfigurations.
PIN CONFIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A28
A27
A26
A25
A24
A23
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
B15
B14
B13
B12
GND
B11
B10
A14
A13
Vcc
A12
GND
A11
A10
5610 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata
registers.Themailboxregisters'widthmatchestheselectedPortBbuswidth. availableforreadingornot.Itmarksthepresenceofvaliddataontheoutputs.
Eachmailboxregisterhas a flag(MBF1andMBF2)tosignalwhennewmail
TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram-
mableAlmost-Fullflag(AF).AE indicates whenaselectednumberofwords
has beenstored.
TwokindsofresetareavailableontheseFIFOs:ResetandPartialReset. remainintheFIFOmemory.AFindicateswhentheFIFOcontainsmorethan
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray aselectednumberofwords.
andselectsserialflagprogramming,parallelflagprogramming,oroneoffive
possibledefaultflagoffsetsettings,8,16,64,256or1,024.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
intoitsarray.EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe readsdatafromitsarray.ProgrammableoffsetsforAEandAFareloadedin
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e., parallelusingPortAorinserialviatheSDinput.Fivedefaultoffsetsettingsare
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset alsoprovided.TheAEthresholdcanbesetat8,16,64,256or1,024locations
is useful since it permits flushing of the FIFO memory without changing any fromtheemptyboundaryandtheAFthresholdcanbesetat8,16,64,256or
configurationsettings.
1,024locationsfromthefullboundary.AllthesechoicesaremadeusingtheFS0,
TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfour FS1 and FS2 inputs during Reset.
clockcyclesofCLKAandCLKB,bytakingtheRetransmitpin,RTLOWwhile
InterspersedParityisavailableandcanbeselectedduringaMasterReset
theRetransmitModepin, RTMisHIGH.WhenaRetransmitisperformedthe oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming
readpointerisresettothefirstmemorylocation.
oftheflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, Parityis selectedthendatalineA8willbecomeavalidbit.
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray.A
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
read operation is required to access that word (along with all other words InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstword seriestocreategreaterworddepths.Theadditionofexternalcomponentsis
written to an empty FIFO appears automatically on the outputs, no read unnecessary.
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces-
sitate a formal read request). The state of the BE/FWFT pin during Reset automatically power down. During the power down state, supply current
determinesthemodeinuse. consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a inputs)willimmediatelytakethedeviceoutofthePowerDownstate.
combinedFull/InputReadyFlag(FF/IR).TheEFandFFfunctionsareselected TheIDT723653/723663/723673arecharacterizedforoperationfrom0°C
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
in the IDT Standard mode. EF indicates whether or not the FIFO memory is to70°C.Industrialtemperaturerange(-40°Cto+85°C)isavailablebyspecial
empty.FFshowswhetherthememoryisfullornot.TheIRandORfunctions order.TheyarefabricatedusingIDT’shighspeed,submicronCMOStechnol-
areselectedintheFirstWordFallThroughmode.IRindicateswhetherornot ogy.
3
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/O
O
36-bitbidirectionaldataportforsideA.
AE
Almost-EmptyFlag
(Port B)
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsinthe
FIFOis less thanorequaltothevalueintheAlmost-EmptyBoffsetregister,X.
AF
Almost-FullFlag
(Port A)
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
locations intheFIFOis less thanorequaltothevalueintheAlmost-FullAoffsetregister,Y.
B0-B35
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In
this case,dependingonthebus size,themostsignificantbyteorwordwrittentoPortAis readfrom
PortBfirst.ALOWonBEwillselectLittle-Endianoperation.Inthiscase,theleastsignificantbyteor
wordwrittentoPortAisreadfromPortBfirst.AfterMasterReset,thispinselectsthetimingmode.A
HIGHonFWFT selects IDTStandardmode, a LOWselects FirstWordFallThroughmode. Once
thetimingmodehasbeenselected,thelevelonFWFTmustbestaticthroughoutdeviceoperation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. ALOWselects longwordoperation. BMworks withSIZEandBEtoselectthe bus size and
endianarrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.
Fall Through
(1)
BM
Bus-MatchSelect
(Port B)
I
I
I
CLKA
CLKB
PortAClock
PortBClock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbe
asynchronous orcoincidenttoCLKA.EF/ORandAE are synchronizedtothe LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA.The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF/OR
Empty/Output
Ready Flag
(Port B)
O
This is adualfunctionpin.IntheIDTStandardmode,theEFfunctionis selected. EFindicates
whetherornottheFIFOmemoryisempty.IntheFWFTmode,theORfunctionisselected.ORindicates
thepresenceofvaliddataontheB0-B35outputs,availableforreading.EF/ORissynchronizedtothe
LOW-to-HIGHtransitionofCLKB.
ENA
ENB
FF/IR
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
Full/Input
Ready Flag
(Port A)
O
This is adualfunctionpin.IntheIDTStandardmode,the FF functionis selected. FF indicates
whetherornottheFIFOmemoryis full.IntheFWFTmode,theIRfunctionis selected.IRindicates
whether or not there is space available for writing to the FIFO memory. FF/IR is synchronized to the
LOW-to-HIGHtransitionofCLKA.
FS0/SD
FlagOffsetSelect0/
SerialData,
I
FS1/SEN andFS0/SDaredual-purposeinputs usedforflagoffsetregisterprogramming.During
Reset,FS1/SENandFS0/SD,togetherwithFS2selecttheflagoffsetprogrammingmethod. Three
offsetregisterprogrammingmethodsareavailable:automaticallyloadoneoffivepresetvalues(8,
16, 64, 256 or 1,024), parallel load from Port A, and serial load.
FS1/SEN
FlagOffsetSelect1/
SerialEnable
I
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenable
synchronous totheLOW-to-HIGHtransitionofCLKA.WhenFS1/SENis LOW,arisingedgeon
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
to program the offset registers is 22 for theIDT723653, 24 for the IDT723663, and 26 for the IDT723673.
ThefirstbitwritestorestheY-registerMSBandthelastbitwritestorestheX-registerLSB.
FS2(1)
FlagOffsetSelect2
MBA
MBB
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputand
aLOWlevelselectsFIFOdataforoutput.
4
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBF1
Mail1RegisterFlag
O
MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.
Writes tothemail1registerareinhibitedwhileMBF1is LOW.MBF1is setHIGHbyaLOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
followingeithera Reset(RS1)or Partial Reset (PRS).
MBF2
Mail2RegisterFlag
Resets
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.
Writes tothemail2registerareinhibitedwhileMBF2is LOW.MBF2is setHIGHbyaLOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
followingeithera Reset(RS2)or Partial Reset (PRS).
RS1, RS2
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes.ALOW-to-HIGHtransitiononRS1selectstheprogramming
method(serialorparallel)andoneoffiveprogrammableflagdefaultoffsets. ItalsoconfiguresPort
Bforbus sizeandendianarrangement.FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-
HIGHtransitions ofCLKBmustoccurwhile RS1 is LOW.
PRS/
RT
PartialReset/
Retransmit
I
ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM
pin.IfRTMisLOW,thenaLOWonthispininitializestheFIFOreadandwritepointerstothefirstlocation
ofmemoryandsetsthePortBoutputregistertoallzeroes.DuringPartialReset, thecurrently
selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammable
flagsettingsareallretained.IfRTMisHIGH,thenaLOWonthispinperformsaRetransmitandinitializes
thereadpointeronly,tothefirstmemorylocation.
RTM
RetransmitMode
I
I
ThispinisusedinconjunctionwiththeRTpin.WhenRTMisHIGHaRetransmitisperformedwhen
RT is taken HIGH.
(1)
SIZE
BusSizeSelect
(Port B)
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
whenBMis HIGHselects word(18-bit)bus size. SIZEworks withBMandBEtoselectthe bus size
andendianarrangementforPortB.ThelevelofSIZEmustbestaticthroughoutdeviceoperation.
W/RA
PortAWrite/
ReadSelect
I
I
AHIGHselectsawriteoperationandaLOWselectsareadoperationonPortAforaLOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGH impedancestatewhenW/RAisHIGH.
ALOWselectsawriteoperationandaHIGHselectsareadoperationonPortBforaLOW-to-HIGH
transitionofCLKB.TheB0-B35outputs areintheHIGHimpedancestatewhenW/RBis LOW.
W/RB
PortBWrite/
ReadSelect
NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5to+7.0
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device
at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Max.
5.5
—
0.8
–4
Unit
SupplyVoltage
V
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
V
VIL
—
—
—
0
V
IOH
mA
mA
°C
IOL
8
TA
70
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATINGFREE-
AIR TEMPERATURERANGE(Unlessotherwisenoted)
IDT723653
IDT723663
IDT723673
Commercial
tCLK = 12, 15, 20 ns
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
Test Conditions
IOH = –4 mA
Min.
2.4
—
—
—
—
—
—
—
Typ.(1)
—
—
—
—
—
—
4
Max.
—
0.5
±10
±10
1
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
VCC = 5.5V,
OutputLogic"0"Voltage
IOL = 8 mA
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
µ A
µ A
mA
mA
pF
ILO
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
ICC1(2)
ICC2(2)
StandbyCurrent(noclocksrunning)
Standby Current (with CLKA & CLKB running) VCC = 5.5V,
8
(3)
CIN
InputCapacitance
OutputCapacitance
VI = 0,
—
—
(3)
COUT
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterized values, not currently tested.
6
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723653/723663/723673 with CLKA
andCLKBsettofS.Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnected
tonormalizethegraphtoazerocapacitanceload.Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT723653/723663/723673inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
WithICC(f) takenfromFigure1,themaximumpowerdissipation(PT)oftheseFIFOs maybecalculatedby:
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC X fo)
where:
N
∆ICC
dc
CL
fo
=
=
=
=
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
outputcapacitanceload
switchingfrequencyofanoutput
300
fdata = 1/2 fS
TA
= 25oC
CL = 0 pF
250
200
150
VCC = 5.5V
VCC = 5.0V
VCC = 4.5V
100
50
0
0
10
20
30
40
50
60
70
80
90
5610 drw03
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT723653L12
IDT723663L12
IDT723673L12
IDT723653L15
IDT723663L15
IDT723673L15
IDT723653L20
IDT723663L20
IDT723673L20
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Min.
—
12
5
Max.
83
Min.
—
15
6
Max.
66.7
—
Min.
—
20
8
Max.
50
Unit
MHz
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
—
—
Pulse Duration, CLKA or CLKB HIGH
—
—
—
ns
Pulse Duration, CLKAandCLKBLOW
5
—
6
—
8
—
ns
SetupTime, A0-A35before CLKA↑ andB0-B35before CLKB↑
3
—
4
—
5
—
ns
tENS1
SetupTime,CSAandW/RAbeforeCLKA↑;CSBand
W/RB before CLKB↑
4
—
4.5
—
5
—
ns
tENS2
Setup Time, ENA, and MBA before CLKA↑; ENB and
MBBbeforeCLKB↑
3
—
4.5
—
5
—
ns
tRSTS
tFSS
SetupTime, RS1 orPRS LOWbefore CLKA↑ orCLKB↑(1)
Setup Time, FS0, FS1 and FS2 before RS1 HIGH
SetupTime,BE/FWFT beforeRS1 HIGH
5
7.5
7.5
3
—
—
—
—
—
—
—
—
—
5
7.5
7.5
4
—
—
—
—
—
—
—
—
—
6
8.5
8.5
5
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBES
tSDS
SetupTime,FS0/SDbeforeCLKA↑
tSENS
tFWS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
5
SetupTime,FWFTbeforeCLKA↑
0
0
0
HoldTime,A0-A35afterCLKA↑ andB0-B35afterCLKB↑
Setup Time, RTM before RT1; RTM before RT2
0.5
5
1
1
tRTMS
tENH
5
5
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;CSB,
W/RB, ENB, and MBB after CLKB↑
0.5
1
1
tRSTH
tFSH
HoldTime, RS1 orPRSLOWafterCLKA↑ orCLKB↑(1)
Hold Time, FS0, FS1 and FS2 after RS1 HIGH
Hold Time, BE/FWFT afterRS1 HIGH
4
2
—
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
—
4
3
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBEH
2
2
3
tSDH
HoldTime,FS0/SDafterCLKA↑
0.5
0.5
2
1
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
1
HoldTime, FS1/SEN HIGH afterRS1 HIGH
Hold Time, RTM after RT1; RTM after RT2
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
2
3
tRTMH
tSKEW1(2)
5
5
5
5
7.5
12
9
tSKEW2(2,3) Skew Time between CLKA↑ and CLKB↑ for AE and AF
12
16
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
8
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT723653L12
IDT723663L12
IDT723673L12
IDT723653L15
IDT723663L15
IDT723673L15
IDT723653L20
IDT723663L20
IDT723673L20
Symbol
tA
Parameter
Min.
2
Max.
Min.
2
Max.
10
8
Min.
2
Max.
12
Unit
ns
Access Time,CLKA↑ toA0-A35andCLKB↑ toB0-B35
PropagationDelayTime, CLKA↑ toFF/IR
PropagationDelayTime,CLKB↑ toEF/OR
PropagationDelayTime,CLKB↑ toAE
PropagationDelayTime,CLKA↑ toAF
8
8
8
8
8
8
tWFF
tREF
tPAE
tPAF
tPMF
2
2
2
10
ns
1
1
8
2
10
ns
1
1
8
1
10
ns
1
1
8
1
10
ns
PropagationDelayTime, CLKA↑ toMBF1 LOWorMBF2
and CLKB↑ to MBF2 LOW or MBF1 HIGH
0
0
8
0
10
ns
tPMR
tMDV
tRSF
tEN
PropagationDelayTime, CLKA↑ toB0-B35(1) andCLKB↑ to
2
2
1
2
1
8
8
2
2
1
2
1
10
10
15
10
8
2
2
1
2
1
12
12
20
12
10
ns
ns
ns
ns
ns
A0-A35(2)
Propagation Delay Time, MBA to A0-A35 valid and MBB to
B0-B35Valid
Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF
HIGH, MBF1 HIGH and MBF2 HIGH
10
6
Enable Time, CSAandW/RALOWtoA0-A35ActiveandCSB
LOW and W/RB HIGH to B0-B35 Active
tDIS
Disable Time, CSA orW/RAHIGHtoA0-A35athigh
impedance and CSB HIGH or W/RB LOW to B0-B35 at high
impedance
6
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
SIGNALDESCRIPTION
RESET (RS1, RS2)
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
Thisisadualpurposepin.AtthetimeofReset,theBEselectfunctionis
active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread
fromPortB.Thisselectiondeterminestheorderbywhichbytes(orwords)of
dataaretransferredthroughthisport.Forthefollowingillustrations,assumethat
a byte (orword)bus size has beenselectedforPortB. (Note thatwhenPort
Bisconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication
pulse toRS1 andRS2 simultaneously. Afterwards, the FIFOmemoryofthe
IDT723653/723663/723673undergoesacompleteresetbytakingitsReset
(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfourPort
B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output
Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Fullflag(AF)HIGH.AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe
parallelmailboxregisterHIGH,andatthesametimetheRS2andMBF2operate
likewise.AfteraReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwo
writeclockcyclestobeginnormaloperation.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferredthroughPortB.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe
valuesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag
Programming, and Almost-Empty and Almost-Full flag offset programming
section). The relevantResettimingdiagramcanbe foundinFigure 3.
1
and the BE input is a “don’t care” .)
AHIGHonthe BE/FWFT inputwhenthe Reset(RS1)inputgoes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort
Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe
readfromPortBlast.
ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement.Inthiscase,theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBfirst;the
mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom
PortBlast.RefertoFigure2foranillustrationoftheBEfunction.SeeFigure
3(Reset)foranEndianselecttimingdiagram.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT)mode.OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT
Standard mode. This mode uses the Empty Flag function (EF) to indicate
whetherornotthere are anywords presentinthe FIFOmemory. Ituses the
FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
includingthefirst,mustberequestedusingaformalreadoperation.
OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring
thenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectFWFTmode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(B0-B35).ItalsousestheInputReadyfunction
(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
PARTIAL RESET (PRS)
The FIFO memory of the IDT723653/723663/723673 undergoes a
limitedresetbytakingitsPartialReset(PRS)inputLOWforatleastfourPortA
clock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.TheRTM
pinmustbeLOWduringthetimeofPartialReset.ThePartialResetinputcan
switchasynchronouslytotheclocks.APartialResetinitializestheinternalread
andwritepointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/
OutputReadyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andthe
Almost-Fullflag(AF)HIGH.APartialResetalsoforcestheMailboxflag(MBF1,
MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,theFIFO’s
Full/InputReadyflagissetHIGHaftertwoWriteClockcyclestobeginnormal
operation. See Figure 4, PartialReset(IDTStandardandFWFTModes)for
therelevanttimingdiagram.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogramminga FIFOfollowinga Resetwouldbe inconvenient.
FollowingReset, the levelappliedtothe BE/FWFT inputtochoose the
desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto
Figure 3(Reset)fora FirstWordFallThroughselecttimingdiagram.
RETRANSMIT (RT)
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
Two registers in the IDT723653/723663/723673 are used to hold the
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags.TheAlmost-Emptyflag
(AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled
Y.Theoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofthe
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).FS2FS0/
SD, and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
The FIFO memory of these devices undergoes a Retransmit by taking its
associatedRetransmit(RT)inputLOWforatleastfourPortAClock(CLKA)and
fourPortBClock(CLKB)LOW-to-HIGHtransitions.TheRetransmitinitializes
thereadpointerofFIFOtothefirstmemorylocation.
TheRTMpinmustbeHIGHduringthetimeofRetransmit.NotethattheRT
inputismuxedwiththePRSinput,thestateoftheRTMpindeterminingwhether
thispinperformsaRetransmitoraPartialReset.SeeFigure19forRetransmit
(Standard IDT mode) and Figure 20 for Retransmit (FWFT mode) timing
diagrams.
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 1 FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
H
H
H
L
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
H
L
L
L
↑
↑
↑
↑
↑
↑
↑
↑
64
16
8
256
1,024
SerialprogrammingviaSD
(2,4)
ParallelprogrammingviaPortA
IP Mode(3,4)
NOTES:
1. X register holds the offset for AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
values.IfInterspersedParityisselectedthenduringparallelprogrammingof
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters theflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
withoneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbe ParityisselectedthendatalineA8willbecomeavalidbit.IfInterspersedParity
HIGHorLOWduringareset.Forexample,toloadthepresetvalueof64into isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
XandY,FS0,FS1andFS2mustbeHIGHwhenRS1returns HIGH.Forthe programmingcanbedone.
relevantpresetvalue loadingtimingdiagram, see Figure 3.
— SERIAL LOAD
— PARALLEL LOAD FROM PORT A
ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,
ToprogramtheXandYregistersfromPortA,performaResetwithFS2 FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
HIGHorLOWandFS0andFS1LOWduringtheLOW-to-HIGHtransitionof After this reset is complete, the X and Y register values are loaded bit-wise
RS1.ThestateofFS2atthispointofresetwilldeterminewhethertheparallel throughtheFS0/SDinputoneachLOW-to-HIGHtransitionofCLKAthatthe
programming method has Interspersed Parity or Non-Interspersed Parity. FS1/SENinputisLOW.Thereare22-,24-or26-bitwritesneededtocomplete
RefertoTable1forFlagProgrammingFlagOffsetsetup.Itisimportanttonote theprogrammingfortheIDT723653,IDT723663ortheIDT723673,respec-
thatonceparallelprogramminghasbeenselectedduringaMasterResetby tively.ThetworegistersarewrittenintheorderY,X.Eachregistervaluecan
holding both FS0 & FS1 LOW, these inputs must remain LOW during all be programmed from 1 to 2,044 (IDT723653), 1 to 4,092 (IDT723663) or 1
subsequent FIFO operation. They can only be toggled HIGH when future to 8,188 (IDT723673).
MasterResetsareperformedandotherprogrammingmethodsaredesired.
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredata InputReady(FF/IR)flagremainsLOWuntilallregisterbitsarewritten.FF/IR
inRAM.ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X.On issetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded
thethirdwritecycletheFIFOisreadytobeloadedwithadataword.SeeFigure toallownormalFIFOoperation.
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
See Figure 6, SerialProgrammingofthe Almost-FullFlagandAlmost-
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused
bytheOffsetregistersare(A10-A0),(A11-A0),or(A12-A0)fortheIDT723653, FIFO WRITE/READ OPERATION
IDT723663, or IDT723673, respectively. For Interspersed Parity mode the
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
PortAdatainputsusedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9, (CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
A7-A0), or(A13-A9, A7-A0)forthe IDT723653, IDT723663, orIDT723673, impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35linesareactive
respectively.Thehighestnumberedinputisusedasthemostsignificantbitof outputs whenbothCSA andW/RAareLOW.
thebinarynumberineachcase.Validprogrammingvalues fortheregisters
DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH
range from1to2,044forthe IDT723653;1to4,092forthe IDT723663;and transitionofCLKAwhenCSA is LOW, W/RAis HIGH, ENAis HIGH, MBAis
1to8,188fortheIDT723673.Afteralltheoffsetregistersareprogrammedfrom LOW,andFF/IRisHIGH(seeTable2).FIFOwritesonPortAareindependent
PortA, the FIFObegins normaloperation.
of any concurrent reads on Port B.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read
INTERSPERSED PARITY
InterspersedParityis selectedduringaMasterResetoftheFIFO.Refer select(W/RA).ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
toTable1fortheset-upconfigurationofInterspersedParity.TheInterspersed PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB).TheB0-B35
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword linesareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBisLOW.
loaded into the parallel port (A0-An) during programming of the flag offset The B0-B35 lines are active outputs whenCSB is LOW and W/RB is HIGH.
11
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 2 PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Functions
X
X
X
X
X
↑
None
H
L
X
None
L
H
H
L
Input
FIFOWrite
L
H
H
H
↑
Input
Mail1Write
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
None
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 Read (Set MBF2 HIGH)
TABLE 3 PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
Port Functions
X
X
X
X
X
↑
None
L
L
X
None
L
L
H
L
Input
None
Mail2Write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO read
L
H
L
H
X
↑
Output
None
L
H
H
H
Output
Mail1 Read (Set MBF1 HIGH)
TABLE 4 FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Synchronized
(1,2)
Number of Words in FIFO
to CLKB
to CLKA
(3)
(3)
(3)
IDT723653
IDT723663
IDT723673
EF/OR
AE
AF
H
H
H
L
FF/IR
H
0
1 to X
0
1 to X
0
1 to X
L
H
H
H
H
L
L
H
(X+1)to[2,048-(Y+1)]
(2,048-Y)to2,047
2,048
(X+1)to[4,096-(Y+1)]
(4,096-Y)to4,095
4,096
(X+1)to[8,192-(Y+1)]
(8,192-Y)to8,191
8,192
H
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output
register (no read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
transitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,MBBis HIGH.WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are arrayis clockedtotheoutputregisteronlywhenareadis selectedusingthe
independentofanyconcurrentwrites onPortA.
port’sChipSelect,Write/Readselect,Enable,andMailboxselect.
WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether
The setupandholdtime constraints tothe portclocks forthe portChip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis
andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable clocked to the output register only when a read is selected using the port’s
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write
changestatesduringthesetupandholdtimewindowofthecycle.
timing diagram can be found in Figure 7. Relevant Port B Read timing
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagis diagrams together with Bus-Matching and Endian select can be found in
LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregister Figure 8, 9 and 10.
12
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthantwo
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe
next memory write location has been read. The second LOW-to-HIGH
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
theFull/InputReadyflagHIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 13 and 14).
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop
stages.Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
ofmetastableevents whenCLKAandCLKBoperateasynchronouslytoone
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronizedtoCLKB.Table4showstherelationshipofeachportflagtothe
numberofwords storedinmemory.
EMPTY/OUTPUTREADYFLAGS(EF/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready
(OR)functionis selected. Whenthe Output-Readyflagis HIGH, newdata is
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected.When
theEmptyFlagisHIGH,dataisavailableintheFIFO’smemoryforreadingto
the output register. When the Empty Flag is LOW, the previous data word is
presentinthe FIFOoutputregisterandattemptedFIFOreads are ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock
that reads data from its array (CLKB). For both the FWFT and IDT Standard
modes,theFIFOreadpointerisincrementedeachtimeanewwordisclocked
to its output register. The state machine that controls an Output Ready flag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe
FIFOmemorystatusisempty,empty+1,orempty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizingclock.Therefore,anOutputReadyflagisLOWifawordinmemory
isthenextdatatobesenttotheFlFOoutputregisterandthreecyclesoftheport
ClockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword
waswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthethirdLOW-
to-HIGHtransitionofthesynchronizingclockoccurs,simultaneouslyforcingthe
OutputReadyflagHIGHandshiftingthewordtotheFIFOoutputregister.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
ifawordinmemoryis thenextdatatobesenttotheFlFOoutputregisterand
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
thetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOWuntil
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
the Empty Flag HIGH; only then can data be read.
ALMOST-EMPTYFLAG(AE)
The Almost-Emptyflagofa FIFOis synchronizedtothe portclockthat
readsdatafromitsarray(CLKB).ThestatemachinethatcontrolsanAlmost-
Emptyflagmonitorsawritepointerandreadpointercomparatorthatindicates
whentheFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-
empty+2.TheAlmost-EmptystateisdefinedbythecontentsofregisterX.These
registersareloadedwithpresetvaluesduringaFIFOreset,programmedfrom
PortA,orprogrammedserially(seeAlmost-EmptyflagandAlmost-Fullflag
offset programming section). An Almost-Empty flag is LOW when its FIFO
contains Xorless words andis HIGHwhenits FIFOcontains (X+1)ormore
words.NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
frommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock
aftertheFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization
cycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)
words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst
synchronization cycle. (See Figure 15).
ALMOST-FULL FLAG (AF)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2.TheAlmost-Fullstate
isdefinedbythecontentsofregisterY.Theseregistersareloadedwithpreset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section).AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOis
greaterthanorequalto(2,048-Y),(4,096-Y),or(8,192-Y)fortheIDT723653,
IDT723663,orIDT723673respectively.AnAlmost-FullflagisHIGHwhenthe
numberofwordsinitsFIFOislessthanorequalto[2,048-(Y+1)],[4,096-(Y+1)],
or[8,192-(Y+1)]fortheIDT723653,IDT723663,orIDT723673respectively.
NotethatadatawordpresentintheFIFOoutputregisterhasbeenreadfrom
memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are requiredaftera FIFOreadforits Almost-Fullflagtoreflectthe newlevel
offill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (FF/IR)
Thisisadualpurposeflag.InFWFTmode,theInputReady(IR)function
isselected.InIDTStandardmode,theFullFlag(FF)functionisselected.For
bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation
isfreeintheFIFOtoreceivenewdata.Nomemorylocationsarefreewhenthe
Full/InputReadyflagis LOWandattemptedwrites totheFIFOareignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat
writesdatatoitsarray(CLKA).ForbothFWFTandIDTStandardmodes,each
timeawordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
13
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe placedonA0-A8. (Inthis case, A9-A35are indeterminate.)
firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
Thedatainamailregisterremainsintactafteritisreadandchangesonly
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro- onmailboxdata.Formailregisterandmailregisterflagtimingdiagrams,see
nization cycle (see Figure 16).
Figure 17 and 18.
MAILBOX REGISTERS
BUS SIZING
Two36-bitbypass registers are onthe IDT723653/723663/723673to
The PortBbus canbe configuredina 36-bitlongword, 18-bitword, or
pass command and control information between Port A and Port B without 9-bitbyteformatfordatareadfromtheFIFO.ThelevelsappliedtothePortB
puttingitinqueue.TheMailboxselect(MBA,MBB)inputschoosebetweena BusSizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbus
mailregisterandaFIFOforaportdatatransferoperation.Theusablewidth size.TheselevelsshouldbestaticthroughoutFIFOoperation.Bothbussize
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB. selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen Ready flag is set HIGH, as shown in Figure 2.
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
TwodifferentmethodsforsequencingdatatransferareavailableforPort
selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys B when the bus size selection is either byte-or word-size. They are referred
datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant
oftheMail1RegisteremploysdatalinesA0-A17.(Inthiscase,A18-A35are bytefirst).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-
don’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusablewidth to-HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduring
oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t FIFOoperation.BEisadon’tcareinputwhenthebussizeselectedforPortB
careinputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2 the time the Full/InputReadyflagis setHIGH, as showninFigure 2.
RegisterwhenaPortBwriteis selectedbyCSB,W/RB,andENBwithMBB Only36-bitlongworddataiswrittentoorreadfromtheFIFOmemoryon
islongword.TheendianmethodisimplementedatthecompletionofReset,by
HIGH.IftheselectedPortBbus sizeis 36bits,theusablewidthoftheMail2 theIDT723653/723663/723673.Bus-matchingoperationsaredoneafterdata
employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,thenthe isreadfromtheFIFORAM.Thesebus-matchingoperationsarenotavailable
usablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthiscase,B18- whentransferringdataviamailboxregisters.Furthermore,boththeword-and
B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusable byte-sizebusselectionslimitthewidthofthedatabusthatcanbeusedformail
widthoftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35are registeroperations.Inthiscase,onlythosebytelanesbelongingtotheselected
don’tcareinputs.)
word-orbyte-sizebuscancarrymailboxdata.Theremainingdataoutputswill
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2) be indeterminate. The remaining data inputs will be don’t care inputs. For
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW. example,whenaword-sizebusisselected,thenmailboxdatacanbetransmitted
Whendataoutputsofaportareactive,thedataonthebuscomesfrom only between A0-A17 and B0-B17. When a byte-size bus is selected, then
theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom mailboxdatacanbetransmittedonlybetweenA0-A8andB0-B8.(SeeFigures
themailregisterwhentheportMailboxselectinputisHIGH.
17 and 18).
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadis selectedbyCSB,W/RB,andENBwithMBB BUS-MATCHING FIFO READS
HIGH.Fora36-bitbussize,36bitsofmailboxdataareplacedonB0-B35.For
DataisreadfromtheFIFORAMin36-bitlongwordincrements.Ifalong
an18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthiscase, wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are outputregister.IfbyteorwordsizeisimplementedonPortB,onlythefirstone
placedonB0-B8. (Inthis case, B9-B35are indeterminate.)
ortwobytesappearontheselectedportionoftheFIFOoutputregister,withthe
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition restofthelongwordstoredinauxiliaryregisters.Inthiscase,subsequentFIFO
onCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENAwithMBA reads outputtherestofthelongwordtotheFIFOoutputregisterintheorder
HIGH.
Fora36-bitbussize,36bitsofmailboxdataareplacedonA0-A35.For
shown by Figure 2.
WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase, outputsareindeterminate.
14
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
BYTE ORDER ON PORT A:
A35
A27
A26
A18
A17
A9
B9
A8
B8
A0
B0
Write to FIFO
A
A
B
C
D
D
B35
B27
B26
B18
B17
BYTE ORDER ON PORT B:
BE BM SIZE
B
C
Read from FIFO
X
L
X
(a) LONG WORD SIZE
B35
B35
B27
B27
B26
B26
B18
B18
B17
B9
B9
B8
B8
B0
B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
A
B
D
H
H
L
B17
C
(b) WORD SIZE
BIG-ENDIAN
B35
B35
B27
B27
B26
B18
B17
B9
B8
B0
B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
C
D
L
H
L
B26
B18
B17
B9
B8
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35
B35
B35
B35
B27
B27
B27
B27
B26
B26
B26
B26
B18
B17
B17
B17
B17
B9
B9
B9
B9
B8
B8
B8
B8
B0
B0
B0
B0
BE BM SIZE
A
B
C
D
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B18
B18
B18
3rd: Read from FIFO
4th: Read from FIFO
(d) BYTE SIZE
BIG-ENDIAN
B35
B35
B35
B35
B27 B26
B27 B26
B27 B26
B27 B26
B18
B18
B18
B18
B17
B17
B17
B17
B9
B8
B8
B8
B8
B0
B0
B0
B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B9
B9
B9
C
B
2nd: Read from FIFO
3rd: Read from FIFO
A
4th: Read from FIFO
5610 drw 04
(e) BYTE SIZE
LITTLE-ENDIAN
Figure 2. Bus sizing
15
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
tRSTS
tRSTH
RS1, RS2
BE/FWFT
tBEH
tBES
tFWS
BE
FWFT
tFSH
tFSS
FS2,
FS1,FS0
0,1
tWFF
tWFF
FF/IR
(2)
tREF
EF/OR
tRSF
AE
tRSF
AF
tRSF
MBF1,
MBF2
RTM
LOW
5610 drw05
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS
t
WFF
t
WFF
FF/IR
(2)
REF
t
EF/OR
AE
t
RSF
t
RSF
AF
t
RSF
MBF1,
MBF2
RTM LOW
5610 drw 06
NOTES:
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
2
1
4
RS1
t
FSS
t
FSH
FS2
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FF/IR
tENS2
tENH
ENA
tDH
tDS
A0-A35
5610 drw 07
AE Offset
First Word to FIFO1
AF Offset
(Y)
(X)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
CLKA
RS1
FS2
4
tFSS
tFSS
tFSH
tWFF
FF/IR
tSENS
tSDS
tSENH
tSDH
tSENS
tSDS
tSENH
tSDH
tSPH
FS1/SEN
FS0/SD(2)
5610 drw 08
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
17
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
FF/IRA HIGH
tENS1
tENH
CSA
tENS1
t
ENH
ENH
ENH
W/RA
t
ENS2
t
MBA
ENA
tENS2
tENH
t
tENS2
tENS2
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0-A35
5610 drw09
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR HIGH
CSB
W/RB
MBB
ENB
t
ENS2
tENS2
tENH
t
ENH
tENH
t
ENS2
No Operation
W2(1)
tDIS
t
MDV
tA
t
A
tEN
(1)
B0-B35
Previous Data
W1
(Standard Mode)
t
MDV
t
DIS
OR
tA
tA
W1(1)
tEN
B0-B35
W2 (1)
W3 (1)
(FWFT Mode)
5610 drw10
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
FF/OR HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
Read 2
t
DIS
t
MDV
t
A
t
A
B0-B17
t
EN
(Standard Mode)
Previous Data
Read 1
Read 2
t
DIS
OR
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
5610 drw11
NOTE:
1. Unused word B18-B35 are indeterminate.
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
DATA WRITTEN TO FIFO 1
READ
NO.
DATA READ FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
EF/OR HIGH
CSB
W/RB
MBB
t
ENS2
t
ENH
A
ENB
No Operation
t
MDV
tDIS
t
A
tA
t
t
A
t
EN
B0-B8
(Standard Mode)
Read 1
Read 4
Read 5
Previous Data
Read 2
Read 3
tDIS
OR
tA
t
MDV
tA
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
5610 drw12
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
READ
NO.
DATA READ
FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B8-B0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
D
1
2
3
4
D
C
B
A
H
H
L
A
B
C
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
t
IR HIGH
A0-A35
tDS
tDH
W1
t
tSKEW1
CLKtCLKL
(1)
tCLKH
CLKB
1
2
3
t
REF
tREF
FIFO Empty
LOW
OR
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
B0-B35
NOTES:
tA
Old Data in FIFO Output Register
W1
5610 drw13
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB
cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may
occur one CLKB cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
W/RA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
FF HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
t
REF
t
REF
EF
FIFO Empty
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0-B35
W1
5610 drw14
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENH
tENS2
ENB
OR HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
CLKA
tCLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
t
WFF
t
WFF
IR
FIFO Full
LOW
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
To FIFO
5610 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
SKEW1
Next Word From FIFO
B0-B35
(1)
t
tCLK
tCLKH
tCLKL
CLKA
1
2
WFF
ENH
WFF
t
t
FIFO Full
LOW
FF
CSA
HIGH
W/RA
t
t
ENS2
ENS2
MBA
t
tENH
ENA
tDS
tDH
A0-A35
5610 drw16
To FIFO
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Words in FIFO
(X+1) Words in FIFO
ENS2
t
tENH
ENB
5610 drw17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
1
2
(1)
tENH
tENS2
tSKEW2
ENA
AF
t
PAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
CLKB
tENH
tENS2
ENB
5610 drw18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723653, 4,096 for the IDT723663, 8,192 for the IDT723673.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENS1
tENH
CSA
W/RA
MBA
t
ENH
t
ENS1
t
ENS2
ENS2
t
ENH
t
tENH
ENA
tDH
tDS
W1
A0-A35
CLKB
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENS2
tENH
t
MDV
tEN
tDIS
t
PMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
5610 drw19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-
B35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENH
tENS1
CSB
tENH
tENS1
W/RB
t
ENH
t
ENS2
ENS2
MBB
ENB
tENH
t
tDH
tDS
W1
B0-B35
CLKA
MBF2
t
PMF
t
PMF
CSA
W/RA
MBA
ENA
tENH
tENS2
t
EN
tPMR
t
DIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
5610 drw20
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-
A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8
will have valid data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
26
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
tENS2
tENH
ENB
tRSTH
t
RSTS
RT
t
RTMS
t
RTMH
RTM
(2)
REF
(2)
REF
t
t
EF
B0-Bn
NOTES:
tA
Wx
W1
5610 drw21
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT723653, IDT723663 and IDT723673 respectively.
Figure 19. Retransmit Timing (IDT Standard Mode)
CLKA
CLKB
4
1
2
3
2
3
4
1
ENB LOW
tRSTH
t
RSTS
RT
t
RTMS
t
RTMH
RTM
(2)
REF
(2)
REF
t
t
OR
tA
B0-Bn
Wx
W1
5610 drw22
NOTES:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after OR returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT723653, IDT723663 and IDT723673 respectively.
Figure 20. Retransmit Timing (FWFT Mode)
27
IDT723653/723663/723673CMOSSyncFIFOTM WITHBUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TRANSFER CLOCK
WRITE
READ
READ CLOCK (CLKB)
CHIP SELECT (CSB)
EMPTY FLAG/
OUTPUT READY (EF/OR)
CLKB
CLKA
WRITE CLOCK (CLKA)
CHIP SELECT (CSA)
EF/OR
ENA
V
CC
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
FF/IR
ENB
READ ENABLE (ENB)
V
CC
CSB
CSA
READ SELECT (W/RB)
IDT
IDT
723653
723663
723673
723653
723663
723673
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A
0
-A35
n
B
0
-B35
B0-B35
n
FULL FLAG/
INPUT READY (FF/IR)
DATA OUT (Qn)
Qn
Dn
V
CC
V
CC
W/RA
MBA
W/RB
MBB
5610 drw23
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 21. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
PARAMETER MEASUREMENT INFORMATION
5.0 V
1.1KΩ
From Output
Under Test
30 pF (1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
Input
1.5 V
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
S
th
tW
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈ 3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
OL
t
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
5610 drw24
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms.
28
ORDERING INFORMATION
IDT
X
XX
X
X
XXXXXX
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
PF
Thin Quad Flat Pack (TQFP, PK128-1)
12
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
2,048 x 36
4,096 x 36
8,192 x 36
SyncFIFO with Bus-Matching
SyncFIFO with Bus-Matching
SyncFIFO with Bus-Matching
5610 drw25
723653
723663
723673
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
12/20/2000
03/21/2001
pgs. 12 and 28.
pgs. 6 and 7.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for TECH SUPPORT:
408-330-1753
e-mail:FIFOhelp@idt.com
www.idt.com
PF Pkg: www.idt.com/docs/PSC4045.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
29
相关型号：
©2020 ICPDF网 联系我们和版权申明