IDT723666L12PFG8 [IDT]
FIFO, 4KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128;
| 型号： | IDT723666L12PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片 |
| 文件： | 总39页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT723656
IDT723666
IDT723676
five default offsets (8, 16, 64, 256 and 1024)
FEATURES
• Serial or parallel programming of partial flags
• Big- or Little-Endian format for word and byte bus sizes
• Loopback mode on Port A
• Retransmit Capability
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Memory storage capacity:
IDT723656
IDT723666
IDT723676
–
–
–
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
• Clock frequencies up to 83 MHz (8ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Mailbox bypass registers for each FIFO
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT723626/3636/3646
• Industrial temperature range (–40°C to +85°C) is available
• Programmable Almost-Empty and Almost-Full flags; each has
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
CLKA
CSA
W/RA
ENA
MBA
LOOP
Register
Port-A
Control
Logic
18
B0-B17
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
36
36
CLKB
RENB
CSB
Port-B
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
PRS1
MBB
Read
Pointer
Write
Pointer
SIZEB
36
Status Flag
Logic
FFA/IRA
EFB/ORB
AFA
AEB
FIFO1
FIFO2
Common
Port
FS2
FS0/SD
Control
Logic
Programmable Flag
Offset Registers
Timing
Mode
BE
FS1/SEN
(B and C)
A0-A35
13
FWFT
FFC/IRC
AFC
Status Flag
Logic
EFA/ORA
AEA
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
36
RT1
RTM
RT2
FIFO1 and
FIFO2
Retransmit
Logic
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
18
36
36
C0-C17
CLKC
WENC
MBC
Port-C
Control
Logic
Mail 2
Register
SIZEC
5611 drw01
MBF2
IDTandtheIDTlogoareregisteredtrademarkofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
NOVEMBER 2003
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5611/4
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
18-bitbuses(PortBtransmitsdata,PortCreceivesdata.) FIFOdatacanbe
readoutofPortBandwrittenintoPortCusingeither18-bitor9-bitformatswith
achoiceofBig-orLittle-Endianconfigurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface. Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
DESCRIPTION
The IDT723656/723666/723676 is a monolithic, high-speed, low-power,
CMOSTripleBussynchronous(clocked)FIFOmemorywhichsupportsclock
frequencies up to 83 MHz and has read access times as fast as 8ns. Two
independent2,048/4,096/8,192x36dual-portSRAMFIFOs onboardeach
chipbufferdatabetweenabidirectional36-bitbus(PortA)andtwounidirectional
PIN CONFIGURATION
INDEX
1
2
3
4
5
6
7
8
CLKB
PRS2/RT2
LOOP
C17
C16
C15
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C14
RTM
MBC
C13
C12
C11
C10
C9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C8
VCC
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
C0
GND
B17
B16
SIZEC
VCC
B15
B14
B13
B12
GND
B11
B10
5611 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or aselectednumberofwordsremainintheFIFOmemory. AFAandAFCindicate
coincident. The enables for each port are arranged to provide a simple whenthe FIFOcontains more thana selectednumberofwords.
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
FFA/IRA,FFC/IRC,AFAand AFCaretwo-stagesynchronizedtothePort
Clockthatwritesdataintoitsarray. EFA/ORA,EFB/ORB,AEA,andAEBare
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox two-stage synchronized to the Port Clock that reads data from its array.
registers. Themailboxregisters'widthmatchestheselectedbuswidthofports Programmableoffsets forAEA, AEB,AFA,AFCareloaded inparallelusing
BandC. Eachmailboxregisterhas aflag(MBF1and MBF2)tosignalwhen PortAorinserialviatheSDinput. Fivedefaultoffsetsettingsarealsoprovided.
newmailhas beenstored.
TheAEAandAEBthresholdcanbesetat8,16, 64,256,and1,024locations
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial fromtheemptyboundaryandtheAFAandAFCthresholdcanbesetat8,16,
Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation 64,256or1,024locationsfromthefullboundary. Allthesechoicesaremade
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- using the FS0, FS1 and FS2 inputs during Master Reset.
ming,or oneoffivepossibledefaultflagoffsetsettings,8,16,64,256or1,024.
InterspersedParitycanalsobeselectedduringaMasterResetoftheFIFO.
Each FIFO has its own, independent Master Reset pin, MRS1 and MRS2. IfInterspersedParityisselectedthenduringparallelprogrammingoftheflag
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe offsetvalues,thedevicewillignoredatalineA8. IfNon-InterspersedParityis
memory. UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., selectedthendatalineA8willbecomeavalidbit.
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
ALoopbackfunctionisprovidedonPortA. WhentheLoopfeatureisselected
is useful since it permits flushing of the FIFO memory without changing any viatheLOOPpin,thedataoutputfromFIFO2willbedirectedtothedatainput
configurationsettings. EachFIFOhasitsown,independentPartialResetpin, ofFIFO1. IfLoopisselectedandPortAisset-upforwriteoperationviaW/RA
PRS1andPRS2. NotethattheRetransmitMode,RTMpinmustbeLOWatthe pin,thendataoutputfromFIFO2willbewrittentoFIFO1,butwillnotbeplaced
pointapartialresetisperformed.
ontheoutputPortA(A0-A35). IfPortAisset-upforreadoperationviaW/RA
BothFIFO'shaveRetransmitcapability,whenaRetransmitisperformedon thendataoutputfromFIFO2willbewrittenintoFIFO1andplacedontoPortA
arespectiveFIFOonlythereadpointerisresettothefirstmemorylocation. A (A0-A35). TheLoopwillcontinuetohappenprovidedthatFIFO1isnotfulland
RetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction FIFO2isnotempty. IfduringaLoopsequenceFIFO1becomesfullthenany
withtheRetransmitpinsRT1orRT2,foreachrespectiveFIFO. Notethatthe datathatcontinues tobereadoutfromFIFO2willonlybeplacedonthePort
twoRetransmitpins RT1andRT2 are muxedwiththe PartialResetpins.
A (A0-A35) lines, provided that Port A is set-up for read operation. If during
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,the aLoopsequencetheFIFO2becomesempty,thenthelastwordfromFIFO2
firstwordwrittentoanemptyFIFOisdepositedintothememoryarray. Aread willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntiltheLoop
operationisrequiredtoaccessthatword(alongwithallotherwordsresiding functionisstopped. TheLoopfeaturecanbeusefulwhenperformingsystem
inmemory). IntheFirstWordFallThroughmode(FWFT),thefirstwordwritten debuggingandremoteloopbacks.
to an empty FIFO appears automatically on the outputs, no read operation
TwoormoreFIFOsmaybeusedinparalleltocreatewiderdatapaths. Such
required (Nevertheless, accessing subsequent words does necessitate a awidthexpansionrequiresnoadditional,externalcomponents. Furthermore,
formal read request). The state of the BE/FWFT pin during Master Reset twoIDT723656/723666/723676FIFOscanbecombinedwithunidirectional
determinesthemodeinuse.
FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
EachFIFOhasacombinedEmpty/OutputReadyFlag(EFA/ORAandEFB/ family)toformadepthexpansion.
ORB)anda combinedFull/InputReadyFlag(FFA/IRAand FFC/IRC). The
If, at any time, the FIFO is not actively performing a function, the chip will
EF and FF functions are selected in the IDT Standard mode. EF indicates automatically power down. During the power down state, supply current
whetherornottheFIFOmemoryisempty. FFshowswhetherthememoryis consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
fullornot. TheIRandORfunctionsareselectedintheFirstWordFallThrough inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
mode. IRindicateswhetherornottheFIFOhasavailablememorylocations.
ORshowswhethertheFIFOhasdataavailableforreadingornot. Itmarksthe to70°C. Industrialtemperaturerange(-40°Cto+85°C)isavailablebyspecial
presenceofvaliddataontheoutputs. order. They are fabricated using IDT’s high speed, submicron CMOS
TheIDT723656/723666/723676arecharacterizedforoperationfrom0°C
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)anda technology.
programmableAlmost-Fullflag(AFAandAFC). AEAandAEB indicatewhen
3
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
PortAData
I/O
Description
A0-A35
I/O 36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
EmptyFlag
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA. ItisLOWwhenthenumberofwordsinFIFO2
islessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
AEB
AFA
AFC
PortBAlmost-
EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenthenumberofwordsinFIFO1
islessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
PortAAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocations
inFIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
PortCAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKC.ItisLOWwhenthenumberofemptylocations
inFIFO2is less thanorequaltothe value inthe Almost-FullCOffsetregister, Y2.
B0-B17
PortBData
O
I
18-bitoutputdataportforsideB.
BE/FWFT
Big-Endian/
FirstWordFall
ThroughSelect
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
In this case, depending on the bus size, themost significant byte or word on Port A is read from
PortBfirst(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow). ALOWonBEwillselect
Little-Endianoperation.Inthis case,theleastsignificantbyteorwordonPortAis readfromPortBfirst
(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow).
AfterMasterReset,thispinselectsthetimingmode.AHIGHonFWFTselectsIDTStandardmode,a
LOWselectsFirstWordFallThroughmode.Oncethetimingmodehasbeenselected,thelevelon
FWFTmustbestaticthroughoutdeviceoperation.
C0-C17
CLKA
PortC Data
PortAClock
I
I
18-bitinputdataportforsideC.
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to
theLOW-to-HIGHtransitionofCLKA.
CLKB
CLKC
CSA
PortBClock
PortCClock
I
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbeasynchronous
orcoincidenttoCLKA. EFB/ORBandAEBaresynchronizedtotheLOW-to-HIGHtransitionofCLKB.
CLKCis acontinuous clockthatsynchronizes alldatatransfers throughPortCandcanbeasynchronous
or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGHtransitionof CLKC.
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35
outputsareinthehigh-impedancestatewhenCSAisHIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB. The B0-B17
outputsareinthehigh-impedancestatewhenCSBisHIGH.
EFA/ORA
PortAEmpty/
OutputReady
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFA functionis selected. EFA indicates
whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORA
indicates the presence ofvaliddata onthe A0-A35outputs, available forreading. EFA/ORAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
EFB/ORB
PortBEmpty/
OutputReadyFlag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFB functionis selected. EFB indicates
whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB
indicatesthepresenceofvaliddataontheB0-B17outputs,availableforreading. EFB/ORBissynchronized
totheLOW-to-HIGHtransitionofCLKB.
ENA
PortAEnable
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
FFA/IRA
PortAFull/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whetherornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRA
indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FFC/IRC
Port C Full/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFCfunctionis selected. FFC indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC
indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRCis
synchronizedtotheLOW-to-HIGHtransitionofCLKC.
4
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
FS0/SD
FlagOffsetSelect0/
SerialData
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.DuringMasterReset,
FS1/SENandFS0/SD,togetherwithFS2,selecttheflagoffsetprogrammingmethod. ThreeOffsetregister
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
parallelloadfromPortA, andserialload.
FS1/SEN FlagOffsetSelect1/
I
I
SerialEnable
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SEN isusedasanenablesynchronousto
the LOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW, a risingedge onCLKAloadthe bitpresenton
FS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe Offsetregisters is 44forthe
IDT723656, 48 for the IDT723666, and 52 for the IDT723676. The first bit write stores the Y-register (Y1) MSB
andthelastbitwritestores theX-register(X2)LSB.
FS2(1)
FlagOffsetSelect2
LOOP
LoopbackSelect
I
I
This pinselects theloopbackfeatureforPortA.DuringLoopbackdatafromFIFO2willbedirectedtotheinputof
FIFO1. toinitiate a Loopthe LOOP pinmustbe heldLOWandthe ENApinmustbe HIGH.
MBA
Port A Mailbox
Select
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputsareactive,aHIGHlevelonMBAselectsdatafromthemail2registerforoutputandaLOWlevelselects
FIFO2output-registerdataforoutput.
MBB
Port B Mailbox
Select
I
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active,aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselectsFIFO1output
registerdataforoutput.
MBC
Port C Mailbox
Select
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
MasterReset.
MBF1
Mail1Register
Flag
O MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.Writestothemail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
MRS1
Mail2Register
Flag
O MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKCthatwritesdatatothemail2register.Writestothemail2
registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-HIGHtransitionofCLKAwhena
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MasterReset
I
ALOWonthis pin initializes theFIFO1readandwritepointers tothefirstlocationofmemoryandsets thePortB
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialor
parallel)andone offive programmable flagdefaultoffsets forFIFO1andFIFO2. Italsoconfigures ports Band
Cforbus size andendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-HIGH
transitionsofCLKBmustoccurwhileMRS1isLOW.
MRS2
MasterReset
I ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywithMRS1,selects
theprogrammingmethod(serialorparallel)andoneof thefiveflagdefaultoffsetsforFIFO2.FourLOW-to-HIGH
transitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKCmustoccurwhileMRS2isLOW.
PRS1/
RT1
PartialReset/
RetransmitFIFO1
I
ThispinismuxedforbothPartialReset andRetransmitoperations,itisusedinconjunctionwiththeRTMpin. IfRTM
isinaLOWcondition,aLOWonthispinperformsaPartialResetonFIFO1andinitializestheFIFO1readandwrite
pointerstothefirstlocationofmemoryandsetsthePortBoutputregistertoallzeroes.DuringPartialReset,thecurrently
selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsare
allretained. IfRTMis HIGH, a LOWonthis pinperforms a Retransmitandinitializes the FIFO1readpointeronlyto
thefirstmemorylocation.
PRS2/
PartialReset/
I ThispinismuxedforbothPartialReset andRetransmitoperations,itisusedinconjunctionwiththeRTMpin. IfRTM
RT2
RetransmitFIFO2
isinaLOWcondition,aLOWonthispinperformsaPartialResetonFIFO2andinitializestheFIFO2readandwrite
selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsare
allretained. IfRTMis HIGH, a LOWonthis pinperforms a Retransmitandinitializes the FIFO2readpointeronlyto
thefirstmemorylocation.
RENB
RTM
Port B Read Enable
RetransmitMode
I
RENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB.
I
Thispinisusedinconjunctionwiththe RT1andRT2pins.WhenRTMisHIGHaRetransmitisperformedonFIFO1
or FIFO2 respectively.
5
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
PortB
I/O
Description
(1)
SIZEB
I
SIZEBdetermines the bus widthofPortB. AHIGHonthis pinselects byte (9-bit)bus size. ALOWonthis pin
selects word(18-bit)bus size. SIZEBworks withSIZECandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZEBmustbe staticthroughoutdevice operation.
BusSizeSelect
(1)
SIZEC
Port C
BusSizeSelect
I
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word(18-bit)bus size. SIZECworks withSIZEBandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZECmustbe staticthroughoutdevice operation.
WENC
W/RA
PortCWriteEnable
PortAWrite/
ReadSelect
I
I
WENCmustbeHIGHtoenableaLOW-to-HIGHtransitionofCLKCtowritedataonPortC.
AHIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGHtransitionof
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
NOTE:
1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or VCC.
6
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+7.0
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
SupplyVoltage
Min.
4.5
2
Max.
5.5
—
0.8
–4
Unit
V
HIGH Level Input Voltage
LOW-LevelInputVoltage
HIGH-Level Output Current
LOW-Level Output Current
OperatingFree-airTemperature
V
VIL
—
—
—
0
V
IOH
mA
mA
°C
IOL
8
TA
70
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATINGFREE-
AIR TEMPERATURE RANGE(Unless otherwise noted)
IDT723656
IDT723666
IDT723676
Commercial
tCLK = 12, 15ns
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
Test Conditions
IOH = –4 mA
Min.
2.4
—
—
—
—
—
—
—
Typ.(1)
—
—
—
—
—
—
4
Max.
—
0.5
±10
±10
8
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
OutputLogic"0"Voltage
IOL = 8 mA
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
µ A
µ A
mA
mA
pF
ILO
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
ICC2(2)
ICC3(2)
Standby Current (with CLKA, CLKB and CLKC running) VCC = 5.5V,
StandbyCurrent(noclocksrunning)
InputCapacitance
VCC = 5.5V,
VI = 0,
1
(3)
CIN
—
—
(3)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterized values, not currently tested.
4. Industrial temperature range is available by special order.
7
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723656/723666/723676 with CLKA,
CLKBandCLKCsettofS. Alldata inputs anddata outputs change state duringeachclockcycle toconsume the highestsupplycurrent. Data outputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice'sinputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthese FIFOs maybe calculatedby:
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC X fo)
N
where:
N
∆ICC
dc
CL
fo
=
=
=
=
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4V
outputcapacitanceload
switchingfrequencyofanoutput
300
250
200
150
f
data = 1/2 fS
T
A
= 25oC
L = 0 pF
C
V
CC = 5.5V
VCC = 5.0V
V
CC = 4.5V
100
50
0
0
10
20
30
40
50
60
70
80
90
5611 drw02a
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
8
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723656L12 IDT723656L15
IDT723666L12 IDT723666L15
IDT723676L12 IDT723676L15
Symbol
fS
Parameter
Min.
—
12
5
Max.
83
Min.
—
15
6
Max.
66.7
—
Unit
MHz
ns
Clock Frequency, CLKA, CLKB, or CLKC
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA, CLKB, or CLKC
—
—
—
—
—
—
Pulse Duration, CLKA, CLKB, or CLKC HIGH
Pulse Duration, CLKA, CLKB, ORCLKCLOW
Setup Time, A0-A35 before CLKA↑ andC0-C17before CLKC↑
SetupTime, CSA andW/RAbefore CLKA↑; CSB before CLKB↑
—
ns
5
6
—
ns
3
4
—
ns
tENS1
tENS2
4
4.5
4.5
—
ns
Setup Time, ENA, and MBA before CLKA↑; RENB and MBB before CLKB↑;
WENC and MBC before CLKC↑
3
—
ns
(1)
tRSTS
tFSS
Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW before CLKA↑ or CLKB↑
Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH
SetupTime, BE/FWFT beforeMRS1 andMRS2 HIGH
SetupTime,FS0/SDbeforeCLKA↑
5
7.5
7.5
3
—
—
—
—
—
—
—
—
—
5
7.5
7.5
4
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBES
tSDS
tSENS
tFWS
tRTMS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
SetupTime,BE/FWFTbeforeCLKA↑
0
0
Setup Time, RTM before RT1; RTM before RT2
HoldTime, A0-A35afterCLKA↑ andC0-C17afterCLKC↑
5
5
0.5
0.5
1
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB after
CLKB↑;WENCandMBCafterCLKC↑
1
(1)
tRSTH
tFSH
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after CLKA↑ or CLKB↑
4
2
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
HoldTime, FS0/SDafterCLKA↑
tBEH
2
2
tSDH
0.5
0.5
2
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Hold Time, RTM after RT1; RTM after RT2
2
tRTMH
5
5
(2)
tSKEW1
SkewTime, betweenCLKA↑andCLKB↑for EFB/ORBand FFA/IRA;betweenCLKA↑
and CLKC↑ for EFA/ORA and FFC/IRC
5
7.5
(2,3)
tSKEW2
SkewTime,betweenCLKA↑andCLKB↑forAEBandAFA;betweenCLKA↑ and
CLKC↑ for AEA and AFC
12
—
12
—
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
3. Design simulated, not tested.
4. Industrial temperature range is available by special order.
9
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723656L12 IDT723656L15
IDT723666L12 IDT723666L15
IDT723676L12 IDT723676L15
Symbol
tA
Parameter
Min.
2
Max.
Min.
2
Max.
10
8
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B17
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to FFC/IRC
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑toEFB/ORB
PropagationDelayTime,CLKA↑toAEAandCLKB↑toAEB
Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC
8
8
8
8
8
8
tWFF
tREF
tPAE
tPAF
tPMF
2
2
ns
1
1
8
ns
1
1
8
ns
1
1
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH, CLKB↑ to MBF1
HIGH, andCLKC↑toMBF2 LOW
0
0
8
ns
tPMR
tMDV
tRSF
Propagation Delay Time, CLKA↑ to B0-B17(1) and CLKC↑ to A0-A35(2)
2
2
1
8
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B17 valid
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and MBF1
HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH
10
tEN
tDIS
Enable Time, CSA orW/RALOWtoA0-A35Active andCSB LOWtoB0-B17Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH
toB0-B17atHIGHimpedance
NOTES:
1. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Industrial temperature range is available by special order.
10
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
RETRANSMIT ( RT1, RT2 )
SIGNALDESCRIPTION
TheFIFO1memoryofthesedevicesundergoesaRetransmitbytakingits
associatedRetransmit (RT1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializesthereadpointerofFIFO1tothefirstmemorylocation.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit(RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions. TheRetransmitinitializestheread
pointerofFIFO1tothefirstmemorylocation.
TheRTMpinmustbeHIGHduringthetimeofRetransmit. Notethatthe RT1
inputismuxedwiththePRS1input,thestateoftheRTMpindeterminingwhether
thispinperformsaRetransmitorPartialReset. Also,theRT2inputismuxed
with the PRS2 input, the state of the RTM pin determining whether this pin
performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmittimingdiagrams.
MASTER RESET ( MRS1, MRS2 )
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723656/723666/723676 undergoes a complete reset by
takingitsassociatedMasterReset(MRS1)inputLOWforatleastfourPortAClock
(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions. TheFIFO2
memory undergoes a complete reset by taking its associated Master Reset
(MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag(FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB)LOW,theAlmost-Emptyflag(AEA,AEB)LOWandtheAlmost-Fullflag
(AFA,AFC)HIGH. AMasterResetalsoforces the associatedMailboxFlag
(MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraMasterReset,the
FIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles. Thenthe
FIFO is ready to be written to.
BIG-ENDIAN/FIRST WORD FALL THROUGH ( BE/FWFT )
— ENDIAN SELECTION
Thisisadualpurposepin. AtthetimeofMasterReset,theBEselectfunction
isactive,permittingachoiceofBig-orLittle-Endianbytearrangementfordata
writtentoPortCorreadfromPortB. This selectiondetermines theorderby
which bytes (or words) of data are transferred through those ports. For the
followingillustrations,notethatbothportsB andCareconfiguredtohaveabyte
(or a word) bus size.
AHIGHontheBE/FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
movinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)of
thelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAastheleast
significantbyte(word)ofthelongword.
ALOWontheBE/FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
gofromLOWtoHIGHwillselectaLittle-Endianarrangement. Whendatais
movinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)of
thelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast. When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAasthemost
significantbyte(word)ofthelongword. RefertoFigure2and3forillustrations
oftheBEfunction. SeeFigure4(FIFO1MasterReset)and5(FIFO2Master
Reset)forEndianSelecttimingdiagrams.
ALOW-to-HIGHtransitionontheFIFO1MasterReset(MRS1)inputlatches
thevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytes
aretransferredthroughPortsBandC. ItalsolatchesthevaluesoftheFlagSelect
(FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-Empty
offsetsandprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearstheflag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetsandprogrammingmethod(fordetailsseeTable
1,FlagProgramming,andAlmost-EmptyandAlmost-Fullflagoffsetprogram-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
Note thatMBCmustbe HIGHduringMasterReset(untilFFA/IRAand
FFC/IRCgoHIGH). MBAandMBBare "don'tcare"inputs1 duringMaster
Reset.
PARTIAL RESET (PRS1, PRS2)
TheFIFO1memoryofthesedevicesundergoesalimitedresetbytakingits
associatedPartialReset(PRS1)inputLOWforatleastfourPortAClock(CLKA)
andfourPortBClock(CLKB)LOW-to-HIGHtransitions. TheFIFO2memory
undergoesalimitedresetbytakingitsassociatedPartialReset(PRS2)input
LOWforatleastfourPortAClock(CLKA)andfourPortCClock(CLKC)LOW-
to-HIGHtransitions.TheRTMpinmustbeLOWduringthetimeofpartialreset.
ThePartialResetinputscanswitchasynchronouslytotheclocks. APartialReset
initializestheinternalreadandwritepointersandforcestheFull/InputReady
flag(FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB)LOW,theAlmost-Emptyflag(AEA,AEB)LOW,andtheAlmost-Fullflag
(AFA,AFC)HIGH. APartialResetalsoforcestheMailboxFlag(MBF1,MBF2)
oftheparallelmailboxregisterHIGH. AfteraPartialReset,theFIFO’sFull/Input
ReadyflagissetHIGHaftertwoWriteClockcycles.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation. APartialResetmaybeusefulinthecasewherereprogramming
aFIFOfollowingaMasterResetwouldbeinconvenient. SeeFigure6and7
forPartialResettimingdiagrams.
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through(FWFT)mode. OncetheMasterReset(MRS1, MRS2)inputisHIGH,
aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(forFIFO1)andCLKC(forFIFO2)willselectIDTStandardmode. Thismode
usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare
anywords presentinthe FIFOmemory. Ituses the FullFlagfunction(FFA,
FFC)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requestedusinga formalreadoperation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
11
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/ simultaneouslywithFIFO1MasterReset(MRS1). ForrelevantPresetvalue
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and loadingtimingdiagrams, see Figure 4and5.
CLKC(forFIFO2)willselectFWFTmode. ThismodeusestheOutputReady
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata — PARALLEL LOAD FROM PORT A
outputs(A0-A35orB0-B17). ItalsousestheInputReadyfunction(IRA,IRC)
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting. In ResetonbothFlFOs simultaneouslywithFS2HIGHorLOW, FS0andFS1
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata LOWduringtheLOW-to-HIGHtransitionofMRS1andMRS2. ThestateofFS2
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby atthispointofresetwilldeterminewhethertheparallelprogrammingmethodhas
performingaformalreadoperation.
Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose Programming Flag Offset setup . It is important to note that once parallel
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation. Refer programminghasbeenselectedduringaMasterResetbyholdingbothFS0
toFigure4(FIFO1MasterReset)andFigure5(FIFO2MasterReset)forFirst & FS1 LOW, these inputs must remain LOW during all subsequent FIFO
WordFallThroughselecttimingdiagrams.
operation. They can only be toggled HIGH when future Master Resets are
performedandotherprogrammingmethodsaredesired.
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
Afterthisresetiscomplete,thefirstfourwritestoFIFO1donotstoredatain
FourregistersintheseFIFOsareusedtoholdtheoffsetvaluesfortheAlmost- RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
EmptyandAlmost-Fullflags. ThePortBAlmost-Emptyflag(AEB)Offsetregister InterspersedParitymodethePortAdatainputsusedbytheOffsetregistersare
islabeledX1andthePortAAlmost-Emptyflag(AEA)Offsetregisterislabeled (A10-A0), (A11-A0), or (A12-A0) for the IDT723656, IDT723666, or
X2. ThePortAAlmost-Fullflag(AFA)OffsetregisterislabeledY1andthePort IDT723676,respectively. ForInterspersedParitymodethePortAdatainputs
CAlmost-Fullflag(AFC)OffsetregisterislabeledY2. Theindexofeachregister usedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9,A7-A0),or(A13-
namecorrespondstoitsFIFOnumber. TheOffsetregisterscanbeloadedwith A9,A7-A0)fortheIDT723656,IDT723666,orIDT723676,respectively. The
preset values during the reset of a FIFO, programmed in parallel using the highestnumberedinputisusedasthemostsignificantbitofthebinarynumber
FIFO’sPortAdatainputs,orprogrammedinserialusingtheSerialData(SD) ineachcase. Validprogrammingvaluesfortheregistersrangefrom1to2,044
input (see Table 1).
for the IDT723656; 1 to 4,092 for the IDT723666; and 1 to 8,188 for the
FS0/SD, FS1/SEN andFS2functionthe same wayinbothIDTStandard IDT723676. AfteralltheOffsetregistersareprogrammedfromPortA,thePort
andFWFTmodes.
CFull/InputReadyflag(FFC/IRC)issetHIGH,andbothFIFOsbeginnormal
operation. Refer to Figure 8 for a timing diagram illustration for parallel
programmingoftheflagoffsetvalues.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH INTERSPERSED PARITY
orLOWduringamasterreset. Forexample,toloadthepresetvalueof64into
InterspersedParityisselectedduringaMasterResetoftheFIFO. Referto
X1andY1,FS0,FS1andFS2mustbeHIGHwhenFlFO1reset(MRS1)returns Table1fortheset-upconfigurationofInterspersedParity. TheInterspersed
HIGH. FlagOffsetregistersassociatedwithFIFO2areloadedwithoneofthe Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword
preset values in the same way with FIFO2 Master Reset (MRS2) toggled loadedintotheparallelport(A0-An)duringprogrammingoftheflagoffsetvalues.
TABLE 1 — FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
L
L
H
H
L
L
H
L
L
H
H
L
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
↑
↑
64
X
X
64
16
X
L
X
16
H
H
H
H
H
H
L
8
X
X
8
256
X
X
256
1,024
X
1,024
X
SerialprogrammingviaSD
SerialprogrammingviaSD
(3,5)
(3,5)
L
ParallelprogrammingviaPortA
ParallelprogrammingviaPortA
IP Mode(4, 5)
L
IP Mode(4, 5)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
12
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
LOOP
Data A(A0-A35) I/O
PORT FUNCTION
H
L
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
↑
X
↑
X
↑
↑
H
H
H
H
H
H
H
H
L
High-Impedance
Input
None
None
H
H
L
Input
FIFO1 write
Mail1write
H
L
Input
Output
Output
Output
Output
Output
None
L
H
L
L
FIFO2read
None
L
H
H
L
L
H
H
Mail2 read (set MBF2 HIGH)
H
LoopthedataoutputofFIFO2toinput
of FIFO1 only
L
L
H
L
↑
L
Output
LoopthedataoutputofFIFO2toinput
of FIFO1 and put data on Port A
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
RENB
MBB
CLKB
Data B (B0-B17) Outputs
PORT FUNCTION
H
L
L
L
L
X
L
X
L
X
X
↑
X
↑
High-Impedance
Output
None
None
H
L
L
Output
FIFO1read
H
H
Output
None
H
Output
Mail1 read (set MBF1 HIGH)
TABLE 4 — PORT C ENABLE FUNCTION TABLE
WENC
MBC
CLKC
Data C (C0-C17) Inputs
PORT FUNCTION
H
H
L
L
L
H
L
↑
↑
X
X
Input
Input
Input
Input
FIFO2 write
Mail2write
None
H
None
IRC)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until
allregisterbitsarewritten. FFC/IRCissetHIGHbytheLOW-to-HIGHtransition
ofCLKCafterthelastbitis loadedtoallownormalFIFO2operation.
SeeFigure9timingdiagram, SerialProgrammingoftheAlmost-FullFlag
andAlmost-EmptyFlagOffsetValuesafterReset(IDTStandardandFWFT
Modes).
IfInterspersedParityisselectedthenduringparallelprogrammingoftheflag
offsetvalues,thedevicewillignoredatalineA8. IfNon-InterspersedParityis
selectedthendatalineA8willbecomeavalidbit. IfInterspersedParityisselected
serialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallelprogram-
ming can be done.
— SERIAL LOAD
FIFO WRITE/READ OPERATION
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
withFS2LOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
transitionofMRS1andMRS2. Afterthisresetiscomplete,theXandYregister
valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH
transitionofCLKAthattheFS1/SENinputisLOW. Thereare44-,48-,or52-
bitwritesneededtocompletetheprogrammingfortheIDT723656,IDT723666,
orIDT723676,respectively. ThefourregistersarewrittenintheorderY1,X1,
Y2andfinally,X2. Thefirst-bitwritestoresthemostsignificantbitoftheY1register
andthelast-bitwritestorestheleastsignificantbitoftheX2register. Eachregister
valuecanbeprogrammedfrom1to2,044(IDT723656),1to4,092(IDT723666),
or 1 to 8,188 (IDT723676).
The state ofthe PortAdata (A0-A35)outputs is controlledbyPortAChip
Select(CSA)andPortAWrite/ReadSelect(W/RA). TheA0-A35outputsare
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH. TheA0-A35
outputs are active whenbothCSA andW/RAare LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis
LOW,andFFA/IRAisHIGH. DataisreadfromFIFO2totheA0-A35outputs
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads
and writes on Port A are independent of any concurrent Port B or Port C
operation.
WhentheoptiontoprogramtheOffsetregistersseriallyischosen,thePort
AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
isloadedtoallownormalFIFO1operation. ThePortBFull/InputReady(FFC/
The state of the Port B data (B0-B17) outputs is controlled by the Port B
Chip Select (CSB). The B0-B17 outputs are in the high-impedance state
when CSB is HIGH. The B0-B17 outputs are active when CSB is LOW.
13
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH dataresidingintheFIFO’smemoryarrayisclockedtotheoutputregisteronly
transitionofCLKBwhenCSBisLOW,RENBisHIGH,MBBisLOWandEFB/ whena readis selectedusing CSA, W/RA, ENAandMBAatPortAorusing
ORB is HIGH (see Table 3). FIFO reads on Port B are independent of any CSB,RENBandMBBatPortB. Relevantwriteandreadtimingdiagramsfor
concurrentPortAandPortCoperations.
Port A can be found in Figure 10 and 15. Relevant read and write timing
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH diagramsforPortBandPortC,togetherwithBus-MatchingandEndianselect
transitionofCLKCwhenWENBisHIGH,MBCisLOW,andFFC/IRCisHIGH operation, can be found in Figure 11 to 14.
(seeTable4). FIFOwritesonPortCareindependentofanyconcurrentPort
A and Port B operation.
LOOPBACK(LOOP)
ThesetupandholdtimeconstraintsforCSAandW/RAwithregardtoCLKA
ALoopbackfunctionisprovidedonPortAandisselectedbysettingtheLOOP
as well as CSB with regard to CLKB are only for enabling write and read pinLOW.WhentheLoopfeatureisselected,thedataoutputfromFIFO2willbe
operationsandarenotrelatedtohigh-impedancecontrolofthedataoutputs. directedtothedatainputofFIFO1. IfLoopisselectedandPortAisset-upfor
IfENAis LOWduringa clockcycle, either CSA orW/RAmaychange states writeoperationviatheW/RApinbeingHIGH,thendataoutputfromFIFO2will
duringthesetupandholdtimewindowofthecycle. This is alsotrueforCSB bewrittentoFIFO1,oneveryLOW-to-HIGHtransitionofCLKA,providedCSA
whenRENBis LOW.
isLOWandENAisHIGH. However,FIFO2dataoutputwillnotbeplacedon
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, theoutputPortA(A0-A35). IfPortAisset-upforreadoperationviatheW/RA
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe pinbeingLOW,thendataoutputfromFIFO2willbewrittenintoFIFO1onevery
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. LOW-to-HIGHtransitionofCLKA,providedCSAisLOWandENAisHIGH. Also
WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput FIFO2datawillbeoutputtoPortA(A0-A35). WhentheLOOPpinisHIGHthen
registersonlywhenareadisselectedusingCSA,W/RA,ENAandMBAatPort PortAoperatesinthenormalmanner. RefertoTable2fortheinputset-upof
A or using CSB, RENB and MBB at Port B.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcausethe
theLoopfeature.
TheLoopoperationwillcontinuetohappenprovidedthatFIFO1isnotfull
EmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionoftheRead andFIFO2isnotempty. IfduringaLoopsequenceFIFO1becomesfullthen
Clock. Thedatawordwillnotbeautomaticallysenttotheoutputregister. Instead, anydata thatcontinues tobe readoutfromFIFO2willonlybe placedonthe
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT723656
IDT723666
IDT723676
EFB/ORB
AEB
L
AFA
H
FFA/IRA
0
1toX1
0
1toX1
0
1toX1
L
H
H
H
H
H
H
H
H
L
L
H
(X1+1)to[2,048-(Y1+1)]
(2,048-Y1)to2,047
2,048
(X1+1)to[4,096-(Y1+1)]
(4,096-Y1)to4,095
4,096
(X1+1)to[8,192-(Y1+1)]
(8,192-Y1)to8,191
8,192
H
H
H
L
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKA
Synchronized
to CLKC
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT723656
IDT723666
IDT723676
EFA/ORA
AEA
AFC
FFC/IRC
0
1toX2
0
1toX2
0
1toX2
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X2+1)to[2,048-(Y2+1)]
(2,048-Y2)to2,047
2,048
(X2+1)to[4,096-(Y2+1)]
(4,096-Y2)to4,095
4,096
(X2+1)to[8,192-(Y2+1)]
(8,192-Y2)to8,191
8,192
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.
14
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
functionisselected. Forbothtimingmodes,whentheFull/InputReadyflagis
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata. Nomemory
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites
to the FIFO are ignored.
Port A (A0-A35) lines, (provided that Port A is set-up for read operation). If
duringaLoopsequencetheFIFO2becomes empty,thenthelastwordfrom
FIFO2willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntil
theLoopfunctionisstopped. TheLoopfeaturecanbeusefulwhenperforming
systemdebuggingandremoteloopbacks. SeeFigures34and35forLoopback
timingdiagrams.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
datatoitsarray. ForbothFWFTandIDTStandardmodes,eachtimeaword
is writtentoa FIFO, its write pointeris incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagis LOWifless than
twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince
the next memory write location has been read. The second LOW-to-HIGH
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
theFull/InputReadyflagHIGH.
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag signal reliability by reducing the probability of
metastableeventswhenCLKAoperatesasynchronouslywithrespecttoeither
CLKB or CLKC. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA. EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC
aresynchronizedtoCLKC. Tables5and6showtherelationshipofeachport
flag to FIFO1 and FIFO2.
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1 orgreateraftertheread.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figure 20, 21, 22, and 23).
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(ORA,
ORB)functionisselected. WhentheOutputReadyflagisHIGH,newdatais
presentintheFIFOoutputregister. WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
ALMOST-EMPTY FLAGS (AEA, AEB)
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.
WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMmemoryfor
readingtotheoutputregister. WhentheEmptyFlagisLOW,thepreviousdata
word is present in the FIFO output register and attempted FIFO reads are
ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclockthat
reads data fromits array. Forboththe FWFTandIDTStandardmodes, the
FIFOreadpointerisincrementedeachtimeanewwordisclockedtoitsoutput
register. ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite
pointer and read pointer comparator that indicates when the FIFO memory
statusisempty,empty+1,orempty+2.
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array. The state machine that controls an Almost-Empty flag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA. TheseregistersareloadedwithpresetvaluesduringaFIFOreset,
programmedfromPortA,orprogrammedserially(seetheAlmost-Emptyflag
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW
whenits FIFOcontains Xorless words andis HIGHwhenits FIFOcontains
(X+1)ormorewords. AdatawordpresentintheFIFOoutputregisterhasbeen
readfrommemory.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshiftedto
theFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportclockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwas written. TheOutputReadyflagoftheFIFOremains LOWuntil
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
outputregister.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
the Empty Flag HIGH; only then can data be read.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill. Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (AFA, AFC)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate
isdefinedbythecontentsofregisterY1forAFAandregisterY2forAFC. These
registersareloadedwithpresetvaluesduringaFlFOreset,programmedfrom
PortA,orprogrammedserially(see Almost-EmptyflagandAlmost-Fullflag
offsetprogrammingsection). AnAlmost-FullflagisLOWwhenthenumberof
words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-
Y)fortheIDT723656,IDT723666,orIDT723676respectively. AnAlmost-Full
flagisHIGHwhenthenumberofwordsinitsFIFOislessthanorequalto[2,048-
(Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT723656, IDT723666, or
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figure 16, 17, 18 and 19).
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC)functionisselected. InIDTStandardmode,theFullFlag(FFAandFFC)
15
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
IDT723676 respectively. Note that a data word present in the FIFO output
registerhas beenreadfrommemory.
NotethatMBCmustbeHIGHduringMasterReset(until FFA/IRAand FFC/
IRCgoHIGH. MBAandMBBaredon'tcareinputsduringMasterReset. For
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare mailregisterandmailregisterflagtimingdiagrams,seeFigure28and29.
requiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewleveloffill.
Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-(Y+1)] BUS SIZING
orless words remains LOWiftwocycles ofits synchronizingclockhave not
elapsedsincethereadthatreducedthenumberofwordsinmemoryto[2,048/
4,096/8,192-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-
HIGHtransitionofitssynchronizingclockaftertheFIFOreadthatreducesthe
numberofwordsinmemoryto[2,048/4,096/8,192-(Y+1)]. ALOW-to-HIGH
transitionofanAlmost-Fullflagsynchronizingclockbeginsthefirstsynchroni-
zationcycleifitoccursattimetSKEW2orgreaterafterthereadthatreducesthe
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequentsynchronizingclockcyclemaybethefirstsynchronizationcycle
(see Figure 26 and 27).
PortBmaybeconfiguredineitheran18-bitwordora9-bitbyteformatfor
data readfromFIFO1. PortCmaybe configuredineitheran18-bitwordor
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independentlyforPorts BandC. ThelevelappliedtothePortBSizeSelect
(SIZEB)inputdeterminesthePortBbussizeandthelevelappliedtothePort
C Size Select (SIZEC) input determines the Port C bus size. These levels
should be static throughout FIFO operation. Both bus size selections are
implementedatthecompletionofMasterReset,bythetimetheFull/InputReady
flag is set HIGH, as shown in Figure 2 and 3.
TwodifferentmethodsforsequencingdatatransferareavailableforPorts
BandCregardlessofwhetherthebussizeselectionisbyte-orword-size. They
arereferredtoasBig-Endian(mostsignificantbytefirst)andLittle-Endian(least
significant byte first). The level applied to the Big-Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1 and MRS2 selects the endian
methodthatwillbeactiveduringFIFOoperation. Thisselectionappliestoboth
portsBandC. TheendianmethodisimplementedatthecompletionofMaster
Reset,bythetimetheFull/InputReadyflagis setHIGH,as showninFigure
2 and 3 (see Endian Selection section).
MAILBOX REGISTERS
EachFIFOhasan18-bitbypassregisterallowingthepassageofcommand
andcontrolinformationfromPortAtoPortBorfromPortCtoPortAwithoutputting
itinqueue. TheMailboxSelect(MBA,MBB andMBC)inputschoosebetween
amailregisterandaFIFOforaportdatatransferoperation. Theusablewidth
ofboththe Mail1andMail2registers matches the selectedbus size forport
B and C.
WhensendingdatafromPortAtoPortBviatheMail1Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Register
whena PortAwrite is selectedbyCSA, W/RA, andENAwithMBAHIGH. If
theselectedPortBbussizeis18bits,thentheusablewidthoftheMail1Register
employs datalines A0-A17. (Inthis case,A18-A35aredon’tcareinputs.) If
theselectedPortBbussizeis9bits,thentheusablewidthoftheMail1Register
employs data lines A0-A8. (Inthis case, A9-A35are don’tcare inputs.)
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
whenaPortCwriteisselectedbyWENCwithMBCHIGH. IftheselectedPort
Cbussizeis18bits,thentheusablewidthoftheMail2Registeremploysdata
linesC0-C17. IftheselectedPortCbussizeis9bits,thentheusablewidthof
theMail2RegisteremploysdatalinesC0-C8. (Inthiscase,C9-C17aredon’t
careinputs.)
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe
mailregisterwhentheportmailboxselectinputisHIGH.
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadisselectedbyCSB,andRENBwithMBBHIGH.
Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17. Forthe
9-bitbus size, 9bits ofmailboxdata are placedonB0-B8. (Inthis case, B9-
B17areindeterminate.)
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
onthesedevices. Bus-Matchingoperationsaredoneafterdataisreadfrom
the FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port
C). TheEndianselectoperationsarenotavailablewhentransferringdatavia
mailboxregisters. Furthermore,boththeword-andbyte-sizebusselections
limitthewidthofthedatabusthatcanbeusedformailregisteroperations. In
thiscase,onlythosebytelanesbelongingtotheselectedword-orbyte-size
buscancarrymailboxdata. Theremainingdataoutputswillbeindeterminate.
Theremainingdatainputswillbedon’tcareinputs. Forexample,whenaword-
sizebusisselectedonPortB,thenmailboxdatacanbetransmittedonlyfrom
A0-A17toB0-B17.Whenabyte-sizebusisselectedonPortB,thenmailbox
data canbe transmittedonlyfromA0-A8toB0-B8. Similarly, whena word-
sizebusisselectedonPortC,thenmailboxdatacanbetransmittedonlyfrom
C0-C17toA18-A35. Whenabyte-sizebusisselectedonPortC,thenmailbox
datacanbetransmittedonlyfromC0-C8toA18-A26.
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements. SincePort
Bcanhave a byte orwordsize, onlythe firstone ortwobytes appearonthe
selectedportionoftheFIFO1outputregister,withtherestofthelongwordstored
inauxiliaryregisters. Inthiscase,subsequentFIFO1readsoutputtherestof
the long word to the FIFO1 output register in the order shown by Figure 2.
WhenreadingdatafromFIFO1inbyteformat,theunusedB9-B17outputs
areindeterminate.
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
onCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENAwithMBA
HIGH. Thedatainamailregisterremains intactafteritis readandchanges
only when new data is written to the register. For an 18-bit bus size, 18 bits
ofmailboxdataappearon A18-A35. (Inthiscase,A0-A17areindeterminate.)
Fora9-bitbussize,9bitsofmailboxdataappearonA18-A26. (Inthiscase,
A0-A17andA27-A35areindeterminate.)
Thedatainamailregisterremains intactafteritis readandchanges only
whennewdataiswrittentotheregister. TheEndianSelectfeaturehasnoeffect
onmailboxdata.
BUS-MATCHING FIFO2 WRITES
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements. Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers. TheCLKCrisingedgethatwritesthefourthbyteorthesecondword
oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.
The bytes are arranged in the manner shown in Figure 3.
WhenwritingdatatoFIFO2inbyteformat,theunusedC9-C17inputsare
don'tcareinputs.
16
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26
A18
A8
A0
A35
A27
A17
A9
BYTE ORDER ON PORT A:
D
A
B
C
Write to FIFO1
B17
B9
B8
B0
BYTE ORDER ON PORT B:
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
L
A
B
B17
B9
B8
B0
C
D
(b) WORD SIZE BIG ENDIAN
B17
B9
B8
B8
B0
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
L
SIZEB
L
C
D
B17
B9
A
B
(c) WORD SIZE LITTLE ENDIAN
B17
B17
B17
B17
B9
B9
B9
B9
B8
B0
B0
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
H
A
B8
B
B8
3rd: Read from FIFO1
4th: Read from FIFO1
C
B8
B0
D
(d) BYTE SIZE BIG ENDIAN
B17
B9
B8
B0
B0
B0
BE SIZEB
1st: Read from FIFO1
2nd: Read from FIFO1
D
L
H
B17
B9
B8
C
B17
B9
B9
B8
B
3rd: Read from FIFO1
B17
B8
B0
A
4th: Read from FIFO1
5611 drw 03
(e) BYTE SIZE LITTLE ENDIAN
Figure 2. Port B Bus Sizing
17
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26
A18
A8
A0
A35
A27
A17
A9
BYTE ORDER ON PORT A:
D
A
B
C
Read from FIFO2
C17
C9
C9
C8
C0
C0
BYTE ORDER ON PORT C:
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
L
A
B
C17
C8
C
D
(b) WORD SIZE BIG ENDIAN
C17
C9
C8
C0
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
L
SIZEC
L
C
D
C17
C9
C8
A
B
(c) WORD SIZE LITTLE ENDIAN
C17
C9
C9
C9
C9
C8
C8
C8
C8
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
H
A
C17
C17
C17
C0
B
C0
C0
3rd: Write to FIFO2
4th: Write to FIFO2
C
D
(d) BYTE SIZE BIG ENDIAN
C17
C17
C17
C17
C9
C9
C9
C9
C8
C0
BE SIZEC
1st: Write to FIFO2
2nd: Write to FIFO2
D
L
H
C8
C8
C0
C0
C
B
3rd: Write to FIFO2
C8
C0
A
4th: Write to FIFO2
5611 drw 04
(e) BYTE SIZE LITTLE ENDIAN
Figure 3. Port C Bus Sizing
18
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
1
2
tRSTH
t
RSTS
MRS1
tBEH
t
BES
tFWS
BE/FWFT
BE
0,1
FWFT
t
FSS
tFSH
FS2,FS1
,FS0
t
WFF
t
WFF
FFA/IRA
(2)
REF
t
EFB/ORB
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
RTM
LOW
HIGH
5611 drw 05
LOOP
NOTES:
1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)
1
2
CLKC
CLKA
tRSTH
t
RSTS
MRS2(3)
t
BES
tBEH
tFWS
BE/FWFT
BE
0,1
FWFT
t
FSS
tFSH
FS2,FS1
,FS0
t
WFF
tWFF
FFC/IRC
EFA/ORA
AEA
(2)
REF
t
t
t
RSF
RSF
AFC
t
RSF
MBF2
RTM
LOW
HIGH
5611 drw 06
LOOP
NOTES:
1. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
3. MRS2 must toggle simultaneously with MRS1.
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)
19
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
tRSTH
tRSTS
PRS1
tWFF
tWFF
FFA/IRA
(2)
tREF
EFB/ORB
AEB
tRSF
tRSF
tRSF
AFA
MBF1
RTM
LOW
5611 drw 07
NOTES:
1. MRS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 6. FIFO1 Partial Reset (IDT Standard and FWFT Modes)
CLKC
CLKA
t
RSTS
tRSTH
PRS2
t
WFF
t
WFF
FFC/IRC
(2)
REF
t
EFA/ORA
t
RSF
AEA
t
RSF
AFC
t
RSF
MBF1
5611 drw 08
NOTES:
1. MRS2 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
Figure 7. FIFO2 Partial Reset (IDT Standard and FWFT Modes)
20
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
4
MRS1,
MRS2
t
FSS
t
FSH
FS2
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FFA/IRA
(1)
tSKEW1
tENS2
tENH
ENA
tDH
tDS
A0-A35
First Word to FIFO1
AEA Offset
AFA Offset
AEB Offset
AFC Offset
(Y2)
(X2)
(Y1)
(X1)
CLKC
1
2
t
WFF
FFC/IRC
5611 drw 09
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
t
FSH
t
FSS
FS2
t
WFF
(1)
SKEW
t
FFA/IRA
FS1/SEN
FS0/SD(3)
t
SENS
t
SENH
t
FSS
t
SENS
tSENH
tSPH
tSDS
t
SDH
tSDS
tSDH
AFA Offset
(Y1) MSB
AEA Offset
(X2) LSB
CLKC
4
t
WFF
5611 drw 10
FFC/IRC
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
21
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA HIGH
t
ENH
ENH
t
ENS1
CSA
t
t
ENS1
W/RA
tENH
tENS2
MBA
ENA
tENH
tENH
tENH
tENS2
tENS2
tENS2
tDH
t
DS
W1(1)
W2(1)
A0-A35
No Operation
5611 drw11
NOTE:
1. Written to FIFO1.
Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKC
FFC/IRC
HIGH
t
ENS2
ENS2
t
ENS2
ENS2
t
ENH
t
ENH
MBC
t
t
t
ENH
tENH
WENC
tDH
tDS
C0-C17
5611 drw12
DATA SIZE TABLE FOR WORD WRITES TO FIFO2
(1)
SIZE MODE
WRITE
NO.
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
SIZEC
BE
C17-C9
C8-C0
A35-A27
A26-A18
A17-A9
A8-A0
L
L
H
1
2
A
C
B
D
A
B
C
D
L
1
2
C
A
D
B
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 11. Port C Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
22
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
FFC/IRC HIGH
t
ENS2
ENS2
t
ENH
ENH
t
ENH
MBC
tENS2
t
t
t
ENH
WENC
tDS
tDH
C0-C8
5611 drw 13
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2
SIZE MODE(1)
WRITE
NO.
DATA WRITTEN
TO FIFO2
C8-C0
DATA READ FROM FIFO2
SIZEC
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
A
B
C
D
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 12. Port C Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
CLKB
EFB/ORB HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
Read 2
t
DIS
DIS
t
A
t
MDV
t
A
t
EN
B0-B17
Read 1
Read 2
Previous Data
(Standard Mode)
OR
t
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
5611 drw 14
DATA SIZE TABLE FOR WORD READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
B
H
H
H
A
B
C
D
1
2
1
2
A
C
C
A
D
L
A
B
C
D
D
B
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 13. Port B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
23
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
EFB/ORB
HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
t
DIS
DIS
t
MDV
t
A
t
A
t
A
tA
t
EN
B0-B8
Previous Data
Read 2
Read 3
Read 4
Read 5
Read 1
(Standard Mode)
t
t
MDV
OR
tA
tA
t
A
t
A
t
EN
B0-B8
Read 1
Read 2
Read 3
Read 4
(FWFT Mode)
5611 drw 15
NOTE:
1. Unused bytes B9-B17 are indeterminate for byte-size reads.
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
B8-B0
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB must be static throughout device operation.
Figure 14. Port B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA
HIGH
CSA
W/RA
MBA
tENH
tENH
tENH
tENS2
tENS2
tENS2
ENA
No Operation
W2(1)
t
MDV
tDIS
t
A
tA
t
EN
A0-A35
W1(1)
W2(1)
Previous Data
(
Standard Mode)
tDIS
t
MDV
OR
tA
t
A
t
EN
A0-A35
(FWFT Mode)
W3(1)
W1(1)
5611 drw16
NOTE:
1. Read From FIFO2.
Figure 15. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
24
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
WRA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDS
tDH
W1
A0-A35
CLKHt
CLKtCLKL
(1)
SKEW1
t
t
CLKB
3
1
2
t
REF
t
REF
FIFO1 Empty
LOW
ORB
CSB
MBB LOW
tENS2
tENH
RENB
tA
tA
Read 1
Read 2
B0-B17
5611 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 16. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
25
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
tCLKL
CLKA
LOW
HIGH
CSA
WRA
tENH
tENS2
MBA
tENS2
tENH
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
CLKHtCLK
tCLKL
(1)
SKEW1
t
t
CLKB
1
2
t
REF
t
REF
EFB
CSB
FIFO1 Empty
LOW
MBB LOW
tENS2
tENH
RENB
tA
tA
B0-B17
Read 1
Read 2
5611 drw18
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 17. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
26
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKC
tENS2
tENS2
tENH
tENH
MBC
WENC
IRC
HIGH
tDS
tDH tDS
tDH
Write 1
Write 2
C0-C17
tCLK
tCLKH tCLKL
(1)
tSKEW1
CLKA
1
2
3
tREF
tREF
ORA FIFO2 Empty
CSA LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
A0-A35
W1
5611 drw19
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
27
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
CLKH
tCLKL
t
CLKC
tENS2
tENH
MBC
tENS2
tENH
WENC
FFC
HIGH
tDS
tDH
t
DS
tDH
Write 1
Write 2
C0-C17
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
t
REF
t
REF
EFA
CSA
FIFO2 Empty
LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
tA
A0-A35
W1
5611 drw20
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
28
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB LOW
LOW
MBB
tENS2
tENH
RENB
ORB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
CLK tCLKL
tCLKH
CLKA
IRA
1
2
t
WFF
t
WFF
FIFO1 Full
CSA LOW
W/RA HIGH
tENH
tENS2
MBA
tENS2
tENH
ENA
tDS
tDH
Write
A0-A35
To FIFO1
5611 drw21
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
29
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
MBB
tENS2
tENH
RENB
EFB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
t
CLKH CLK tCLKL
CLKA
1
2
t
WFF
t
WFF
FFA
FIFO1 Full
CSA LOW
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
Write
A0-A35
5611 drw22
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively (the word-size case is shown).
Figure 21. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
30
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
W/RA
LOW
MBA
tENS2
tENH
ENA
ORA
HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0-A35
(1)
tCLK
t
tCLKH
tCLKL
CLKC
1
2
t
WFF
t
WFF
IRC FIFO2 Full
tENS2
tENH
MBC
WENC
C0-C17
t
ENS2
t
ENH
tDS
tDS
tDH
tDH
Write
5611 drw23
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
31
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
W/RA
LOW
MBA
ENA
tENS2
tENH
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKC
1
2
t
WFF
tWFF
FIFO2 Full
FFC
tENS2
tENH
MBC
ENC
tENS2
tENH
tDH
tDS
tDS
tDH
Write
C0-C17
To FIFO2
5611 drw24
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 23. FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENH
tENS2
ENA
(1)
tSKEW2
CLKB
1
2
t
PAE
t
PAE
AEB
X1 Word in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
RENB
5611 drw 25
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 24. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
32
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
tENH
tENS2
WENC
CLKA
(1)
tSKEW2
1
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
5611 drw 26
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
tPAF
(D-Y1) Words in FIFO1
ENH
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
t
tENS2
RENB
5611 drw 27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723656, 4,096 for the IDT723666, 8,192 for the IDT723676.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKC
tENH
tENS2
WENC
AFC
t
PAF
t
PAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
5611 drw 28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723656, 4,096 for the IDT723666, 8,192 for the IDT723676.
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
33
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
tENS1
tENH
CSA
W/RA
MBA
ENA
t
ENS1
t
ENH
t
ENS2
t
ENH
ENH
tENS2
t
tDH
tDS
W1
A0-A35
CLKB
MBF1
t
PMF
t
PMF
CSB
MBB
tENH
tENS2
RENB
t
PMR
tDIS
tEN
t
MDV
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
B0-B17
5611 drw29
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port
B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will
be indeterminate).
Figure 28. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
CLKC
tENS2
tENH
MBC
ENC
tENS2
tENH
tDH
tDS
C0-C17
CLKA
W1
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENS2
tENH
t
PMR
tEN
t
DIS
t
MDV
A0-A35
W1 (Remains valid in Mail2 Register after read)
FIFO2 Output Register
5611 drw30
NOTE:
1. IfPortCis configuredforwordsize, data canbe writtentothe Mail2registerusingC0-C17. Inthis firstcase, A18-A35willhave validdata (A0-A17willbe indeterminate). IfPortCis configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
Figure 29. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
34
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
tENS2
tENH
RENB
RT1
t
RSTH
t
RSTS
t
RTMS
t
RTMH
RTM
(2)
REF
t
REF(2)
t
EFB
B0-Bn
NOTES:
tA
Wx
W1
5611 drw31
1. CSB = LOW
2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)
CLKC
CLKA
4
1
2
3
2
3
4
1
tENS2
tENH
ENA
RT2
t
RSTH
t
RSTS
t
RTMS
t
RTMH
RTM
EFA
(2)
REF
t
REF(2)
t
tA
A0-An
Wx
W1
5611 drw32
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)
35
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
RENB
RT1
LOW
t
RSTH
t
RSTS
t
RTMS
t
RTMH
RTM
ORB
REF(2)
t
REF(2)
t
tA
B0-Bn
Wx
W1
5611 drw33
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 32. Retransmit Timing for FIFO1 (FWFT Mode)
CLKC
CLKA
4
1
2
3
2
3
4
1
ENA
RT2
RTM
LOW
t
RSTH
t
RSTS
t
RTMS
t
RTMH
REF(2)
t
t
REF(2)
t
ORA
A
A0-An
Wx
W1
5611 drw34
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRC will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 33. Retransmit Timing for FIFO2 (FWFT Mode)
36
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
ENA
t
ENS2
t
ENS2
t
ENH
tENH
t
ENH
t
ENS2
No Operation
Wn+1
t
MDV
tDIS
t
A
tA
tEN
Wn-1(1)
A0-A35
Wn(1)
Write to FIFO 1
5611 drw35
Write to FIFO 1
NOTES:
1. Data is read from FIFO2 and written into FIFO1 & placed on Port A simultaneously. The first data word written into FIFO1 is the Previous Data Word (Wn-1)
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
Figure 34. Loopback Operation (FIFO2 data transfer to FIFO1 and Port A)
tCLK
tCLKH
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
ENA
t
ENS2
t
ENS2
t
ENH
t
ENH
tENH
t
ENS2
No Operation
Wn+1
t
MDV
tDIS
tA
tA
tEN
(4) WRITE
to FIFO 1
Wn(1)
Write to FIFO 1
Wn-1(1)
Write to FIFO 1
A0-A35
HIGH-Z
5611 drw36
NOTES:
1. Data is read from FIFO2 and written into FIFO1 only. The data from FIFO2 is NOT placed on Port A. Port A is held in the high impedance state.
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
4. Write operations to FIFO1 cannot be accessed via Port A.
Figure 35. Loopback Operation (FIFO2 data transfer to FIFO1)
37
IDT723656/723666/723676CMOSTRIPLEBUSSyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
5.0V
1.1KΩ
From Output
Under Test
30 pF (1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
1.5V
Input
GND
1.5V
GND
3V
t
S
th
tW
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
1.5V
1.5V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
tPZL
GND
tPLZ
3V
3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
V
t
PHZ
OL
OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4665 drw 37
NOTE:
1. Includes probe and jig capacitance.
Figure 36. Load Circuit and Voltage Waveforms
38
ORDERING INFORMATION
IDT
XXXXXX
X
XX
XX
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
PF
Thin Quad Flat Pack (TQFP, PK128-1)
Clock Cycle Time (tCLK
)
12
15
Commercial Only
Low Power
Speed in Nanoseconds
L
723656
723666
723676
2,048 x 36 x 2 Triple Bus SyncFIFO
4,096 x 36 x 2 Triple Bus SyncFIFO
8,192 x 36 x 2 Triple Bus SyncFIFO
with Bus-Matching
with Bus-Matching
with Bus-Matching
5611 drw 38
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
12/21/2000
03/21/2001
08/01/2001
11/03/2003
pgs. 13 and 22.
pgs. 7 and 8.
pgs. 7, 9, 10 and 39.
pg. 1.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for TECH SUPPORT:
408-330-1753
e-mail:FIFOhelp@idt.com
www.idt.com
39
相关型号：
IDT723672L12PQFG
Bi-Directional FIFO, 8KX36, 8ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
IDT
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