IDT72404L35DB [IDT]
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT; CMOS并行FIFO 64× 4 -bit和64 ×5位
| 型号： | IDT72404L35DB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT |
| 文件： | 总9页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72401
IDT72402
IDT72403
IDT72404
CMOS PARALLEL FIFO
64 x 4-BIT AND 64 x 5-BIT
Integrated Device Technology, Inc.
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data
at the data input (D0-D3, 4). The stored data stack up on a first-
in/first-out basis.
FEATURES:
• First-ln/First-Out Dual-Port memory
• 64 x 4 organization (IDT72401/03)
• 64 x 5 organization (IDT72402/04)
• IDT72401/02 pin and functionally compatible with
MMI67401/02
• RAM-based FIFO with low falI-through time
• Low-power consumption
— Active: 175mW (typ.)
A Shift Out (SO) signal causes the data at the next to last
word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The
Input Ready signal can also be used to cascade multiple
devices together. The Output Ready (OR) signal is a flag to
indicate that the output remains valid data (OR = HIGH) or to
indicate that the FIFO is empty (OR = LOW). The Output
Readycanalsobeusedtocascademultipledevicestogether.
Width expansion is accomplished by logically ANDing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.
• Maximum shift rate — 45MHz
• High data output drive capability
• Asynchronous and simultaneous read and write
• Fully expandable by bit width
• Fully expandable by word depth
• IDT72403/04 have Output Enable pin to enable output
data
Depth expansion is accomplished by tying the data inputs
of one device to the data outputs of the previous device. The
Input Ready pin of the receiving device is connected to the
Shift Out pin of the sending device and the Output Ready pin
of the sending device is connected to the Shift In pin of the
receiving device.
Reading and writing operations are completely asynchro-
nous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FlFOs ideal for high-speed
communication and controller applications.
• High-speed data communications applications
• High-performance CMOS technology
• Available in CERDIP, plastic DIP and SOIC
• Military product compliant to MlL-STD-883, Class B
• Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-
performance First-ln/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-ln/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
OUTPUT
ENABLE
INPUT
CONTROL
LOGIC
OE (IDT72403 and
IDT72404)
SI
IR
WRITE POINTER
WRITE MULTIPLEXER
D0-3
D4
(IDT72402
and IDT72404)
Q0-3
MEMORY
ARRAY
DATAIN
DATAOUT
Q4
(IDT72402 and
IDT72404)
READ MULTIPLEXER
READ POINTER
MASTER
RESET
SO
OR
MR
OUTPUT
CONTROL
LOGIC
2747 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPTEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1996 Integrated Device Technology, Inc.
DSC-2747/7
5.01
1
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401/IDT72403
(IDT72404 Only)
IDT72402/IDT72404
NC/OE(1)
IR
Vcc
SO
OR
Q0
Q1
Q2
NC/OE(2)
Vcc
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
9
18
17
16
15
1
2
20
19
18
17
16
15
14
13
12
11
OE
NC
IR
SI
D0
D1
D2
D3
D4
Vcc
NC
SO
OR
Q0
Q1
Q2
Q3
Q4
MR
IR
SI
SO
OR
Q0
P16-1, 14
SI
D0
D1
D2
D3
3
D16-1
&
13
12
11
10
9
D0
D1
D2
P18-1,
4
D18-1 14
Q
1
5
S016-1
&
13
12
11
10
Q2
Q3
Q4
MR
6
S018-1
Q3
MR
D3
D4
GND
7
GND
8
9
2747 drw 02
DIP/SOIC
TOP VIEW
2747 drw 03
10
GND
DIP/SOIC
TOP VIEW
2747 drw 04
CERPACK
TOP VIEW
NOTES:
1. Pin 1: NC - No Connection IDT72401, OE - IDT72403
2. Pin 1: NC - No Connection IDT72402,OE - IDT72404
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect
to GND
V
VCC
VCC
GND
VIH
Mil. Supply Voltage
Com'l. Supply Voltage
Supply Voltage
4.5
4.5
0
5.0
5.0
0
5.5
5.5
0
V
V
V
V
TA
Operating Temp.
0 to +70
–55 to +125 °C
Input High Voltage
2.0
—
—
TBIAS
Temperature
Under Bias
–55 to +125 –65 to +135 °C
(1)
VIL
Input High Voltage
—
—
0.8
V
NOTE:
2747 tbl 02
TSTG
IOUT
Storage Temp.
–55 to +125 –65 to +150 °C
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC Output
Current
50
50
mA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTE:
2747 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol
Parameter(1)
Conditions
Max. Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
pF
COUT
Output Capacitance VOUT = 0V
NOTE:
1. This parameter is sampled and not 100% tested.
2747 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Symbol
IIL
Parameter
Test Conditions
VCC = Max., GND ≤ VI ≤ VCC
VCC = Max., GND ≤ VI ≤ VCC
VCC = Min., IOL = 8mA
Min.
–10
—
Max.
—
Unit
Low-Level Input Current
High-Level Input Current
Low-Level Output Voltage
High-Level Output Voltage
Output Short-Circuit Current
Off-State Output Current
(IDT72403 and IDT72404)
Supply Current
µA
µA
V
IIH
10
VOL
VOH
—
0.4
—
VCC = Min., IOH = -4mA
VCC = Max., VO = GND
VCC = Max., VO = 2.4V
VCC = Max., VO = 0.4V
2.4
–20
—
V
(1)
IOS
–110
20
mA
µA
µA
IHZ
ILZ
–20
—
(2,3)
ICC
VCC = Max., f = 10MHz Com'l.
Military
—
—
35
45
mA
mA
NOTES:
2747 tbl 04
1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. ICC measurements are made with outputs open. OE is HIGH for IDT72403/72404.
3
For frequencies greater than 10MHZ, ICC = 35mA + (1.5mA x [f - 10MHz]) commercial, and ICC = 45mA + (1.5mA x [f - 10MHz]) military.
5.01
2
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Commercial
Military and Commercial
IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10
IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10
IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10
IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10
Symbol
Parameters
Shift in HIGH Time
FIgure Min.
Max.
—
Min.
9
Max.
—
Min.
11
24
0
Max.
—
Min.
11
25
0
Max.
—
Min.
11
30
0
Max. Unit
(1)
tSIH
2
2
2
2
5
5
8
8
4
4
7
9
11
0
—
—
—
—
—
—
—
—
—
—
—
ns
ns
tSIL
tIDS
tIDH
Shift in LOW TIme
—
17
0
—
—
—
Input Data Set-up
—
—
—
—
ns
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset Pulse to SI
Data Set-up to IR
13
9
—
15
9
—
20
11
24
25
10
5
—
30
11
25
25
25
5
—
40
11
25
30
35
5
ns
(1)
tSOH
—
—
—
—
ns
tSOL
tMRW
tMRS
tSIR
11
20
10
3
—
17
25
10
3
—
—
—
ns
—
—
—
—
ns
—
—
—
—
ns
—
—
—
—
ns
tHIR
Data Hold from IR
13
0
—
15
0
—
20
0
—
30
0
—
30
0
ns
(4)
tSOR
Data Set-up to OR HIGH
—
—
—
—
ns
2747 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Commercial
Military and Commercial
IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10
IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10
IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10
IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10
Symbol
Parameters
FIgure Min.
Max.
45
18
18
45
18
19
—
Min.
—
—
—
—
—
—
5
Max.
35
18
20
35
18
20
—
Min.
—
—
—
—
—
—
5
Max.
25
21
28
25
19
34
—
Min.
—
—
—
—
—
—
5
Max.
15
35
40
15
35
40
—
Min.
—
—
—
—
—
—
5
Max. Unit
tIN
Shift In Rate
2
2
—
—
—
—
—
—
5
10
40
45
10
40
55
—
MHz
ns
(1)
tIRL
Shift In to Input Ready LOW
Shift In to Input Ready HIGH
Shift Out Rate
(1)
tIRH
2
ns
tOUT
5
MHz
ns
(1)
tORL
Shift Out to Output Ready LOW
Shift Out to Output Ready HIGH
Output Data Hold (Previous Word)
Output Data Shift (Next Word)
Data Throughput or "Fall-Through"
Master Reset to OR LOW
5
(1)
tORH
5
ns
tODH
5
ns
tODS
5
—
—
—
—
19
30
25
25
—
—
—
—
20
34
28
28
—
—
—
—
34
40
35
35
—
—
—
—
40
65
35
35
—
—
—
—
55
65
40
40
ns
tPT
4, 7
8
ns
tMRORL
tMRIRH
ns
Master Reset to IR HIGH
8
ns
tMRQ
Master Reset to Data Output LOW
Output Valid from OE LOW
Output High-Z from OE HIGH
Input Ready Pulse HIGH
8
9
9
4
7
—
—
—
9
20
12
12
—
—
—
—
—
9
20
15
12
—
—
—
—
—
11
11
25
20
15
—
—
—
—
—
11
11
35
30
25
—
—
—
—
—
11
11
40
35
30
—
—
ns
ns
(3)
tOOE
(3,4)
tHZOE
ns
(2,4)
tIPH
ns
(2,4)
tOPH
Ouput Ready Pulse HIGH
9
9
ns
NOTES:
2747 tbl 06
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of
like speed grades.
3. IDT72403 and IDT72404 only.
4. Guaranteed by design but not currently tested.
5.01
3
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
5V
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
560
Ω
1.5V
OUTPUT
30pF*
See Figure 1
1.1K
Ω
2747 tbl 07
2747 drw 06
ALL INPUT PULSES:
or equivalent
circuit
3.0V
GND
90%
10%
90%
10%
Figure 1. AC Test Load
<3ns
<3ns
*Including scope and jig
2747 drw 05
SIGNAL DESCRIPTIONS
OUTPUTS:
DATA OUTPUT (Q0-3, 4)
INPUTS:
Data Output lines. The IDT72401 and IDT72403 have a 4-
bitdataoutput. TheIDT72402andIDT72404havea5-bitdata
output.
DATA INPUT (D0-3, 4)
Data input lines. The IDT72401 and IDT72403 have a 4-bit
data input. The IDT72402 and IDT72404 have a 5-bit data
input.
FUNCTIONAL DESCRIPTION
CONTROLS:
These 64 x 4 and 64 x 5 FIFOs are designed using a dual
port RAM architecture as opposed to the traditional shift
register approach. This FIFO architecture has a write pointer,
a read pointer and control logic, which allow simultaneous
readandwriteoperations. Thewritepointerisincrementedby
the falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When
SI is HIGH, data can be written to the FIFO via the D0-3, 4 lines.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO
is HIGH, data can be read from the FIFO via the Data Output
(Q0-3, 4) lines.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within.
Upon power up, the FIFO should be cleared with a Master
Reset. Master Reset is active LOW.
FIFO Reset
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FlFO to enter an empty
state, signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q0-3,
4) will be LOW.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input
datatobewrittentoit.WhenIRisLOWtheFIFOisunavailable
for new input data. Input Ready is also used to cascade many
FlFOs together, as shown in Figures 10 and 11 in the Applica-
tions section.
Data Input
Data is shifted in on the LOW-to-HlGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes Input Ready to go LOW. On the HlGH-to-
LOWtransitionofShiftIn,thewritepointerismovedtothenext
word position and Input Ready (IR) goes HIGH, indicating the
readiness to accept new data. If the FIFO is full, Input Ready
will remain LOW until a word of data is shifted out.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q0-3, 4) contains
valid data. When OR is LOW, the FIFO is unavailable for new
output data. Output Ready is also used to cascade many
FlFOs together, as shown in Figures 10 and 11.
OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLY)
OutputenableisusedtoreadFIFOdataontoabus. Output
Enable is active LOW.
5.01
4
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Output
Fall-Through Mode
The FIFO operates in a fall-through mode when data gets
Data is shifted out on the HlGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be shifted into an empty FIFO. After a fall-through delay the data
advanced to the next word location. If data is present, valid propagates to the output. When the data reaches the output,
data will appear on the outputs and Output Ready (OR) will the Output Ready (OR) goes HIGH. Fall-through mode also
go HIGH. If data is not present, Output Ready will stay occurs when the FIFO is completely full. When data is shifted
LOW indicating the FIFO is empty. The last valid word read out of the full FIFO, a location is available for new data. After
fromtheFIFOwillremainattheFlFOsoutputwhenitisempty. a fall-through delay, the Input Ready goes HIGH. If Shift In is
When the FIFO is not empty, Output Ready (OR) goes LOW HIGH, the new data can be written to the FIFO.
on the LOW-to-HIGH transition of Shift Out. Previous data Since these FlFOs are based on an internal dual-port RAM
remains on the output until the HIGH-to-LOW transition of architecture with separate read and write pointers, the fall-
Shift Out (SO).
through time (tPT) is one cycle long. A word may be written
intotheFIFOonaclockcycleandcanbeaccessedonthenext
clock cycle.
TIMING DIAGRAMS
1/fIN
1/fIN
t
SIH
tSIL
SHIFT IN
INPUT READY
INPUT DATA
t
IRH
t
IDH
tIRL
2747 drw 07
t
IDS
Figure 2. Input Timing
(7)
(2)
(4)
SHIFT IN
INPUT READY
INPUT DATA
(1)
(5)
(3)
(6)
STABLE DATA
2747 drw 08
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the first word.
3. Input Ready goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
5.01
5
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
(3)
(5)
SHIFT IN
(4)
tIPH
tPT
INPUT READY
INPUT DATA
(1)
tSIR
tHIR
STABLE DATA
2747 drw 09
NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
1/fOUT
1/fOUT
tSOH
tSOL
tODS
(2)
SHIFT OUT
OUTPUT READY
OUTPUT DATA
tORH
tODH
tORL
A-DATA
B-DATA
C-DATA
(1)
2747 drw 10
NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when Shift Out makes a HIGH to LOW transition.
Figure 5. Output TIming
SHIFT OUT(7)
OUTPUT READY
OUTPUT DATA
(2)
(4)
(1)
(5)
(3)
(6)
A-DATA
B-DATA
2747 drw 11
A or B
NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. The read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
5.01
6
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT
tPT
OUTPUT READY
DATA OUTPUT
(1)
t SOR
tOPH
DATA VALID
2747 drw 12
NOTE:
1. FIFO initially empty.
Figure 7. tPT and tOPH Specification
-
tMRW
MASTER RESET
INPUT READY
tMRIRH
tMRORL
tMRS
(1)
(1)
OUTPUT READY
SHIFT IN
tMRQ
DATA OUTPUT
2747 drw 13
NOTE:
1. Worst case, FIFO initially full..
Figure 8. Master Reset Timing
OUTPUT ENABLE
t
HZOE
tOOE
DATA OUT
2747 drw 14
NOTE:
1. High-Z transitions are referenced to the steady-state VOH -500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance
instead of 30pF as shown in Figure 1.
Figure 9. Output Enable Timing, IDT72403 and IDT72404 Only
5.01
7
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
OUTPUT READY
SHIFT OUT
SHIFT IN
INPUT READY
SI
IR
D0
D1
D2
D3
OR
SO
Q0
Q1
Q2
Q3
SI
IR
D0
D1
D2
D3
OR
SO
Q0
Q1
Q2
Q3
DATA OUT
DATA IN
MR
MR
2747 drw 15
MR
NOTE:
1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of
the devices.
Figure 10. 128 x 4 Depth Expansion
SHIFT OUT
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
D
D1
D
D3
0
Q
Q
Q
Q
0
D
D1
D
D3
0
Q
Q
Q
Q
0
D
D1
D2
D3
0
Q
Q
Q
Q
0
1
2
3
1
2
3
1
2
3
2
2
MR
MR
MR
MR
MR
MR
MR
MR
MR
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
COMPOSITE
INPUT
COMPOSITE
OUTPUT
READY
D
0
Q
Q
Q
Q
0
D
0
Q
Q
Q
Q
0
D
0
Q
Q
Q
Q
0
READY
D1
D1
D1
D2
D3
1
2
3
1
2
3
1
2
3
D
2
D
2
D3
D3
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
SHIFT IN
D
0
Q
Q
Q
Q
0
D
0
Q
Q
Q
Q
0
D
0
Q
Q
Q
Q
0
D1
D1
D1
D2
D3
1
2
3
1
2
3
1
2
3
D
2
D
2
D3
D3
MR
2747 drw 16
NOTES:
1. When the memory is empty, the last word will remain on the outputs until the Master Reset is strobed or a new data word falls through to the output.
However, OR will remain LOW, indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays
LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will
go HIGH for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written
into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
4. When the Master Reset is brought Low, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the Master Reset
goes HIGH, the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the
Master Reset is ended, IR will go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH.
5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and
Output Ready flags. This is due to the variation of delays of the FIFOs.
Figure 11. 192 x 12 Depth and Width Expansion
5.01
8
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
X
X
X
X
Device Type Power Speed Package
Process/
Temperature
Range
Blank
Commercial (0°C to+70°C)
B
Military (–55°C to+125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP (300 mils wide)
Ceramic DIP (300 mils wide)
Small Outline IC
P
D
SO
Com’l. Only
45
35
25
15
10
Com'l. and Mil
Shift Frequency (fs)
Com’l. and Mil
Speed in MHz
Com'l. and Mil
Com'l. and Mil
L
Low Power
72401 64 x 4 FIFO
72402 64 x 5 FIFO
72403 64 x 4 FIFO
72404 64 x 5 FIFO
2747 drw 17
5.01
9
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