IDT72420L20TC [IDT]
CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8; CMOS SyncFIFOO 64× 8 256× 8 512× 8,1024 ×8 ， 2048 ×8和4096 ×8
| 型号： | IDT72420L20TC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 |
| 文件： | 总16页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
CMOS SyncFIFO
64 x 8, 256 x 8, 512 x 8,
1024 x 8, 2048 x 8 and 4096 x 8
Integrated Device Technology, Inc.
FEATURES:
• 64 x 8-bit organization (IDT72420)
• 256 x 8-bit organization (IDT72200)
• 512 x 8-bit organization (IDT72210)
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240
SyncFIFO are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72420/72200/72210/72220/72230/72240 have a 64,
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-
tively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
TheseSynchronousFIFOshavetwoend-pointflags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
Thepartial(AE)flagsaresettoEmpty+7andFull-7forAE and
AF respectively.
• 1024 x 8-bit organization (IDT72220)
• 2048 x 8-bit organization (IDT72230)
• 4096 x 8-bit organization (IDT72240)
• 12 ns read/write cycle time (IDT72420/72200/72210)
• 15 ns read/write cycle time (IDT72220/72230/72240)
• Read and write clocks can be asynchronous or
coincidental
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Produced with advanced submicron CMOS technology
• Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
• For surface mount product please see the IDT72421/
72201/72211/72221/72231/72241 data sheet
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40OC to +85OC) is
available, tested to military electrical specifications
The IDT72420/72200/72210/72220/72230/72240 are fabri-
cated using IDT’s high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
D0 - D7
WCLK
WEN
•
INPUT REGISTER
•
EF
AE
AF
FF
FLAG
WRITE CONTROL
LOGIC
LOGIC
•
•
RAM ARRAY
64 x 8
256 x 8
512 x 8
WRITE POINTER
READ POINTER
•
•
READ CONTROL
LOGIC
OUTPUT REGISTER
•
RESET LOGIC
RCLK
RS
REN
OE
2680 drw 01
Q0 - Q7
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOVEMBER 1996
1996 Integrated Device Technology, Inc.
DSC-2680/6
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.12
1
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
D4
D3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D5
1
D6
2
D2
D7
3
D1
RS
4
D0
WEN
WCLK
VCC
Q7
5
AF
6
AE
7
P28-2
C28-1
GND
RCLK
REN
OE
8
9
Q6
10
11
12
13
14
Q5
Q4
EF
Q3
FF
Q2
Q0
Q1
DIP TOP
VIEW
2680 drw 02
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0 - D7
Data Inputs
I
Data inputs for a 8-bit bus.
RS
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM
array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE
after power-up.
WCLK
WEN
Write Clock
I
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
Write Enable
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
Data will not be written into the FIFO if the FF is LOW.
Q0 - Q7
RCLK
REN
Data Outputs
Read Clock
Read Enable
O
I
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
OE
EF
AE
AF
FF
Output Enable
Empty Flag
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
O
O
O
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
Almost-Empty
Flag
When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized
to RCLK.
Almost-Full Flag
When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to
WCLK.
Full Flag
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
One 0 volt ground pin.
2680 tbl 01
GND
Ground
5.12
2
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter
Min. Typ. Max. Unit
VTERM
Terminal Voltage –0.5 to + 7.0 –0.5 to + 7.0
with Respect to
GND
V
VCCM
VCCC
Military Supply Voltage
4.5
4.5
5.0
5.0
5.5
5.5
V
V
Commercial Supply
Voltage
TA
Operating
0 to + 70
–55 to + 125 °C
GND
VIH
Supply Voltage
0
0
0
V
V
Temperature
Temperature
Under Bias
Input High Voltage
Commercial
2.0
—
—
TBIAS
TSTG
IOUT
–55 to + 125 –65 to + 135 °C
–55 to + 125 –65 to + 135 °C
VIH
VIL
Input High Voltage
Military
2.2
—
—
—
—
V
Storage
Temperature
DC Output
Current
Input Low Voltage
Commercial & Military
0.8
V
50
50
mA
2680 tbl 03
2680 tbl 02
NOTE:
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
notimplied. Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
Input Capacitance
VIN = 0V
10
10
pF
(1, 2)
COUT
Output Capacitance VOUT = 0V
pF
2680 tbl 04
NOTES:
1. With output deselected. (OE = HIGH)
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT72420
IDT72200
IDT72420
IDT72200
IDT72210
IDT72210
Commercial
tCLK = 12, 15, 20, 25, 35, 50 ns
Military
tCLK = 20, 25,35, 50 ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
(1)
ILI
Input Leakage Current (any input)
Output Leakage Current
–1
–10
2.4
—
—
—
—
—
—
1
–10
–10
2.4
—
—
—
—
—
—
10
10
µA
µA
V
(2)
ILO
10
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
—
0.4
80
0.4
100
V
(3)
ICC1
—
—
mA
2680 tbl 05
IDT72220
IDT72230
IDT72220
IDT72230
IDT72240
Military
IDT72240
Commercial
tCLK = 15, 20, 25, 35, 50 ns
tCLK = 25, 35, 50 ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
(1)
ILI
Input Leakage Current (any input)
Output Leakage Current
–1
–10
2.4
—
—
—
—
—
—
1
–10
–10
2.4
—
—
—
—
—
—
10
10
µA
µA
V
(2)
ILO
10
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
—
0.4
80
0.4
100
V
(4)
ICC1
—
—
mA
2680 tbl 06
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3 & 4.
Measurements are made with outputs unloaded. Tested at fCLK = 20 MHZ.
(3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA
(4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA
fCLK = 1 / tCLK
CL = external capacitive load (30 pF typical)
5.12
3
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial Comm. & Mil. Comm. Comm/Mil
72200L12 72200L15 72200L20 72200L25 72200L35 72200L50
72210L12 72210L15 72210L20 72210L25 72210L35 72210L50
72420L12 72420L15 72420L20 72420L25 72420L35 72420L50
Symbol
fS
Parameter
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min.Max. Unit
—
2
83.3
8
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
—
2
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
3
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
3
28.6
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
—
3
20 MHz
tA
Data Access Time
25
—
—
—
—
—
—
—
—
—
—
50
—
28
28
30
30
30
30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
12
5
—
—
—
—
—
—
—
—
—
—
12
—
7
15
6
20
8
25
10
10
6
35
14
14
8
50
20
20
10
2
Clock High Time
Clock Low Time
5
6
8
Data Set-up Time
3
4
5
tDH
Data Hold Time
0.5
3
1
1
1
2
tENS
tENH
tRS
Enable Set-up Time
4
5
6
8
10
2
Enable Hold Time
Reset Pulse Width(1)
0.5
12
12
12
—
0
1
1
1
2
15
15
15
—
0
20
20
20
—
0
25
25
25
—
0
35
35
35
—
0
50
50
50
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
3
3
3
3
3
3
tOHZ
tWFF
tREF
tAF
3
7
3
8
3
3
3
3
—
—
—
—
5
8
—
—
—
—
6
10
10
10
10
—
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
—
—
—
—
15
8
8
tAE
8
tSKEW1 Skew time between Read Clock &
Write Clock for Empty Flag & Full Flag
—
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
22
—
28
—
35
—
40
—
42
—
45
—
ns
NOTES:
2680 tbl 07
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5.12
4
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Commercial & Military
Comm.
Comm./Mil.
72220L50
72230L50
72240L50
72220L12
72220L15
72230L15
72240L15
72220L20
72230L20
72240L20
72220L25
72230L25
72240L25
72220L35
72230L35
72240L35
72230L12
72240L12
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fS
Clock Cycle Frequency
—
2
83.3
8
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
—
2
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
3
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
3
28.6
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
—
3
20
25
—
—
—
—
—
—
—
—
—
—
50
—
23
23
30
30
30
30
—
tA
Data Access Time
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
12
5
—
—
—
—
—
—
—
—
—
—
12
—
7
15
6
20
8
25
10
10
6
35
14
14
8
50
20
20
10
2
Clock High Time
Clock Low Time
5
6
8
Data Set-up Time
3
4
5
tDH
Data Hold Time
.5
3
1
1
1
2
tENS
tENH
tRS
Enable Set-up Time
4
5
6
8
10
2
Enable Hold Time
.5
12
12
12
—
0
1
1
1
2
Reset Pulse Width(1)
15
15
15
—
0
20
20
20
—
0
25
25
25
—
0
35
35
35
—
0
50
50
50
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
3
3
3
3
3
3
tOHZ
tWFF
tREF
tAF
3
7
3
8
3
3
3
3
—
—
—
—
5
8
—
—
—
—
6
10
10
10
10
—
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
—
—
—
—
15
8
8
tAE
8
tSKEW1 Skew time between Read Clock
& Write Clock for Empty Flag &
Full Flag
—
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag
& Almost-Full Flag
22
—
28
—
35
—
40
—
42
—
45
—
ns
2680 tbl 08
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
1.1K
Ω
AC TEST CONDITIONS
D.U.T.
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
30pF*
680
Ω
1.5V
See Figure 1
2680 tbl 09
2680 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.12
5
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
When Read Enable (REN) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
SIGNAL DESCRIPTIONS
INPUTS:
When all the data has been read from the FIFO, the Empty
Flag(EF)willgoLOW,inhibitingfurtherreadoperations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
Read Enable (REN) is ignored when the FIFO is empty.
Data In (D0–D7) — Data inputs for 8-bit wide data.
CONTROLS:
Reset ( ) — Reset is accomplished whenever the Reset
RS
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power up before a write operation can take
place. TheFullFlag(FF)andAlmostFullFlag(AF)willbereset
to HIGH after tRSF. The Empty Flag (EF) and Almost Empty
Flag (AE) will be reset to LOW after tRSF. During reset, the
output register is initialized to all zeros.
Output Enable ( ) — When Output Enable (OE) is enabled
OE
(LOW), theparalleloutputbuffersreceivedatafromtheoutput
register. When Output Enable (OE) is disabled (HIGH), the
Q output data bus is in a high-impedance state.
OUTPUTS:
Full Flag ( ) — The Full Flag (FF) will go LOW, inhibiting
FF
Write Clock (WCLK) — A write cycle is initiated on the LOW-
to-HIGH transition of the write clock (WCLK). Data set-up and
hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Almost Full Flag (AF) are synchronized with respect to the
LOW-to-HIGH transition of the write clock (WCLK).
The write and read clocks can be asynchronous or coinci-
dent.
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 64 writes for the IDT72420, 256 writes for the IDT72200,
512 writes for the IDT72210, 1024 writes for the IDT72220,
2048writesfortheIDT72230,and4096writesfortheIDT72240.
The Full Flag (FF) is synchronized with respect to the LOW-
to-HIGH transition of the write clock (WCLK).
Empty Flag ( ) — The Empty Flag (EF) will go LOW,
EF
Write Enable (
) — When Write Enable (WEN) is LOW,
WEN
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
data can be loaded into the input register and RAM array on
the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and indepen-
dently of any on-going read operation.
When Write Enable (WEN) is HIGH, the input register holds
the previous data and no new data is allowed to be loaded into
the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable (WEN) is ignored
when the FIFO is full.
Almost Full Flag ( ) — The Almost Full Flag (AF) will go
AF
LOW when the FIFO reaches the Almost-Full condition. If no
reads are performed after Reset (RS), the Almost Full Flag
(AF) will go LOW after 57 writes for the IDT72420, 249 writes
for the IDT72200, 505 writes for the IDT72210, 1017 writes for
the IDT72220, 2041 writes for the IDT72230 and 4089 writes
for the IDT72240.
The Almost Full Flag (AF) is synchronized with respect to
the LOW-to-HIGH transition of the write clock (WCLK).
ReadClock(RCLK)—Datacanbereadontheoutputsonthe
LOW-to-HIGHtransitionofthereadclock(RCLK). TheEmpty
Flag (EF) and Almost-Empty Flag (AE) are synchronized with
respect to the LOW-to-HIGH transition of the read clock
(RCLK).
Almost Empty Flag ( ) — The Almost Empty Flag (AE) will
AE
go LOW when the FIFO reaches the Almost-Empty condition.
If no reads are performed after Reset (RS), the Almost Empty
Flag (AE) will go HIGH after 8 writes for the IDT72420,
IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240.
The Almost Empty Flag (AE) is synchronized with respect
to the LOW-to-HIGH transition of the read clock (RCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Read Enable (
) — When Read Enable (REN) is LOW,
REN
data is read from the RAM array to the output register on the
LOW-to-HIGH transition of the read clock (RCLK).
Data Outputs (Q0–Q7) — Data outputs for a 8-bit wide data.
5.12
6
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 1: STATUS FLAGS
Number of Words in FIFO
IDT72420
0
IDT72200
0
IDT72210
0
IDT72220
0
IDT72230
0
IDT72240
0
FF
H
H
H
H
L
AF
H
H
H
L
AE
L
EF
L
1 to 7
8 to 56
57 to 63
64
1 to 7
1 to 7
1 to 7
1 to 7
1 to 7
L
H
H
H
8 to 248
249 to 255
256
8 to 504
8 to 1016
8 to 2040
8 to 4088
H
H
H
505 to 511 1017 to 1023 2041 to 2047 4089 to 4095
512 1024 2048 4096
L
H
2680 tbl 10
tRS
RS
tRSS
tRSR
REN
tRSS
tRSR
WEN
tRSF
EF, AE
tRSF
tRSF
FF, AF
(1)
OE = 1
OE = 0
Q0 - Q7
2680 drw 04
NOTE:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
5.12
7
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
D0 - D7
tDS
tDH
DATAIN VALID
tENH
tENS
WEN
FF
NO OPERATION
tWFF
tWFF
(1)
tSKEW1
RCLK
REN
2680 drw 05
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the curent clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
5.12
8
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
NO OPERATION
REN
EF
tREF
tREF
tA
Q0 - Q7
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW1
(1)
WCLK
WEN
2680 drw 06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the curent clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
5.12
9
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
D0 (first valid write)
D1
D2
D3
D0 - D7
WEN
RCLK
EF
tENS
(1)
tFRL
tSKEW1
tREF
REN
tA
tA
Q0 - Q7
D0
D1
tOLZ
tOE
OE
NOTE:
2680 drw 07
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundry (EF = LOW).
Figure 5. First Data Word Latency Timing
5.12
10
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK
tDS
tDS
tSKEW1
tSKEW1
DATA WRITE
D0 - D7
DATA WRITE
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
tA
tA
LOW
OE
Q0 - Q7
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2680 drw 08
Figure 6. Full Flag Timing
5.12
11
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
tDS
DATA WRITE 1
tENH
DAT
tENH
D0 - D7
tENS
tENS
WEN
RCLK
EF
tFRL (1)
tFRL (1)
tSKEW1
tSKEW1
tREF
tREF
tREF
REN
OE
LOW
tA
DATA IN OUTPUT REGISTER
DATA READ
Q0 - Q7
NOTE:
2680 drw 09
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundry (EF = LOW).
Figure 7. Empty Flag Timing
5.12
12
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKL
tCLKH
(2)
WCLK
WEN
tENH
tENS
tAF
Full - 7 words in FIFO
AF
Full - 8 words in FIFO
tAF
(1)
tSKEW2
RCLK
tENH
tENS
REN
2680 drw 10
NOTES:
1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the curent clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
5.12
13
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKL
tCLKH
WCLK
WEN
tENH
tENS
Empty+8
Empty+7
SKEW2(1)
AE
tAE
t
t
AE
(2)
RCLK
tENH
t
ENS
REN
2680 drw 11
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the curent clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
5.12
14
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
application requirements are for 64/256/512/1024/2048/4096
words or less. See Figure 10.
SINGLE DEVICE CONFIGURATION - A single IDT72420/
72200/72210/72220/72230/72240 may be used when the
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
IDT
72420/72200/
OUTPUT ENABLE (OE)
72210/
72220/
72230/
72240
DATA IN (D0-D7)
DATA OUT (Q0- Q7)
FULL FLAG (FF)
EMPTY FLAG (EF)
ALMOST FULL (AF)
ALMOST EMPTY(AE)
2680 drw 12
Figure 10. Block Diagram of Single 64 x 8/256 x 8/512 x 8/1024 x 8/2048 x 8/4096 x 8 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may device. Figure 11 demonstrates a 16-bit word width by using
be increased simply by connecting the corresponding input twoIDT72420/72200/72210/72220/72230/72240s. Anyword
controlsignalsofmultipledevices. Acompositeflagshouldbe width can be attained by adding additional IDT72420/72200/
created for each of the end-point status flags (EFand FF) The 72210/72220/72230/72240s.
partial status flags (AEand AF) can be detected from any one
RESET (RS)
RESET (RS)
DATA IN (D)
16
8
8
READ CLOCK (RCLK)
READ ENABLE (REN)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
ALMOST FULL (AF)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
IDT
IDT
ALMOST EMPTY (AE)
EMPTY FLAG (EF) #1
72420/
72200/
72210/
72220/
72230/
72240
72420/
72200/
72210/
72220/
72230/
72240
EMPTY FLAG (EF) #2
8
8
DATA OUT (Q)
16
2680 drw 13
Figure 11. Block Diagram of 64 x 16/256 x 16/512 x 16/1024 x 16/2048 x 16/4096 x 16 Synchronous FIFO
Used in a Width Expansion Configuration
5.12
15
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT72420/72200/72210/72220/ expansion logic alternate data accesses from one device to
72230/72240 can be adapted to applications when the re- the next in a sequential manner.
quirements are for greater than 64/256/512/1024/2048/4096
Please see the Application Note “DEPTH EXPANSION
words. Depth expansion is possible by using expansion logic IDT'S SYNCHRONOUS FIFOs USING RING COUNTER
to direct the flow of data. A typical application would have the APPROACH” for details of this configuration.
ORDERING INFORMATION
IDT
XXXXX
Device
Type
X
XX
XX
X
Power Speed Package Process /
Temperature
Range
BLANK Commercial (0°C to +70°C)
B
Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B
TP
TC
Plastic THINDIP
Sidebraze THINDIP
12
15
20
25
35
50
Commercial Only
Commercial Only
Commercial and Military
Commercial and Military
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Commercial and Military
Low Power
L
72420
72200
72210
72220
72230
72240
64 x 8 Synchronous FIFO
256 x 8 Synchronous FIFO
512 x 8 Synchronous FIFO
1024 x 8 Synchronous FIFO
2048 x 8 Synchronous FIFO
4098 x 8 Synchronous FIFO
2680 drw 14
5.12
16
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