IDT72423L10SO [IDT]
FIFO, 64X1, 7.5ns, Synchronous, CMOS, PDSO24, 0.300 INCH, 0.050 INCH PITCH, SOIC-24;
| 型号： | IDT72423L10SO |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 64X1, 7.5ns, Synchronous, CMOS, PDSO24, 0.300 INCH, 0.050 INCH PITCH, SOIC-24 时钟 先进先出芯片 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SINGLE BIT SyncFIFO
64 X 1, 256 x 1, 512 x 1
IDT72423
IDT72203
IDT72213
Integrated Device Technology, Inc.
for a wide variety of serial data buffering needs, especially
telecommunicationsapplicationssuchasnetworks,modems,
signal processing, and serial interfaces.
FEATURES:
• 64 x 1-bit organization (IDT72423)
• 256 x 1-bit organization (IDT72203)
Thesesingle-bitFIFOshave1-bitinput(D)andoutputports
(Q).Theinputportiscontrolledbyafree-runningclock(WCLK),
and two write enable pins (WEN1, WEN2). Data is written into
the Synchronous FIFO on every rising clock edge when the
writeenablepinsareasserted. Theoutputportiscontrolledby
another clock pin (RCLK) and a read enable pin (REN). The
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF), are provided for improved system
control. TheprogrammableflagsdefaulttoEmpty+7andFull-
7 for PAE and PAF, respectively. The programmable flag
offset is loaded via the Program Inputs (P0 - P7), on the rising
WCLK when the load pin (LD) is asserted.
• 512 x 1-bit organization (IDT72213)
• 10 ns read/write cycle time (IDT72423/72203/72213)
• Independent read and write clock lines
• Empty and Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can
be programmed to any depth via a dedicated port (Pn).
These flags default to Empty+7 and Full-7, respectively.
• Output enable puts output data bus in high impedance
state
• Available in 24-pin SOIC, 24-pin plastic DIP (300 mil.),
and 24-pin ceramic DIP (300 mil.)
• Military product compliant to MIL-STD-883, Class B
Advanced submicron CMOS technology
DESCRIPTION:
The IDT72423/72203/72213 SyncFIFO are very high-
speed, low-power First-In, First-Out (FIFO) memories with a
word width of 1 and clocked read and write controls. The
IDT72423/72203/72213 have a 64, 256, and 512 x 1-bit
memory arrays, respectively. These FIFOs are appropriate
The IDT72423/72203/72213/ are fabricated using IDT’s
high-speedsubmicronCMOStechnology.Militarygradeprod-
uct is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
D
P0 - P7
LD
WCLK
WEN1
WEN2
INPUT REGISTER
OFFSET REGISTER
EF
FLAG
LOGIC
WRITE CONTROL
LOGIC
PAE
PAF
FF
RAM ARRAY
64 x 1
WRITE POINTER
256 x 1
READ POINTER
512 x 1
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN
RS
OE
3111 drw 01
Q
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1994
1995 Integrated Device Technology, Inc
DSC-2065/-
5.04
1
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
P5
P4
1
24
23
22
21
20
19
18
17
16
15
14
13
P6
2
P7
P3
3
D
P2
4
RS
P1
5
WEN1
WCLK
WEN2/LD
VCC
Q
P24-1
D24-1
SO24-2
P0
6
PAF
PAE
VSS
NC
7
8
9
10
11
12
FF
RCLK
REN
EF
OE
DIP/SOIC
TOP VIEW
3111 drw 02
PIN DESCRIPTIONS
Symbol
Name
Data Input
Reset
I/O
Description
D
I
I
Input for serial data.
RS
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
WCLK
WEN1
Write Clock
I
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
Write Enable 1
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin.
When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
WEN2/LD Write Enable 2/
Load
I
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is config-
ured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag
offsets.
P0-P7
Program Inputs
Offsets for the programmable flag registers are entered at these inputs on the rising edge of
WCLK when LD and WEN are LOW
Q
Data Output
Read Clock
O
I
Output for serial data.
RCLK
REN
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
Read Enable 1
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
OE
EF
Output Enable
Empty Flag
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high impedance state.
O
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
Almost-Empty
Flag
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF
FF
Programmable
Almost-Full Flag
O
O
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7. PAF is synchronized to WCLK.
Full Flag
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
VCC
Power
One +5Volt power supply pin.
One 0Volt ground pin.
GND
Ground
3111 tbl 01
5.04
2
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
VCCM
Military Supply Voltage
4.5
4.5
5.0
5.0
5.5
5.5
V
V
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect to
GND
V
VCCC
Commercial
Supply Voltage
Supply Voltage
TA
Operating
Temperature
Temperature
Under Bias
Storage
0 to +70
–55 to +125
°C
°C
GND
VIH
0
0
0
V
V
Input High Voltage
Commercial
2.0
—
—
TBIAS
TSTG
IOUT
–55 to +125 –65 to +135
–55 to +125 –65 to +135
VIH
VIL
Input High Voltage
Military
2.2
—
—
—
—
V
°C
Temperature
DC Output
Current
Input Low Voltage
Commercial & Military
0.8
V
50
50
mA
3111 tbl 03
NOTE:
3111 tbl 02
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthespecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
Input Capacitance
VIN = 0V
10
10
pF
(1,2)
COUT
Output Capacitance
VOUT = 0V
pF
NOTES:
3111 tbl 04
1. With output deselected (OE = HIGH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
IDT72423
IDT72203
IDT72423
IDT72203
IDT72213
IDT72213
Commercial
tCLK = 10, 12, 15ns
Military
tCLK = 15, 25ns
Symbol
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Min.
Typ.
Max.
Min.
Typ.
Max.
10
Unit
µA
µA
V
(1)
ILI
–1
–10
2.4
—
—
—
—
—
—
1
–10
–10
2.4
—
—
(2)
ILO
10
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = -2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
—
—
0.4
80
—
0.4
100
V
(3)
ICC
—
—
—
mA
3111 tbl 05
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Measurements are made with outputs unloaded. Tested at fCLK = 20MHz.
5.04
3
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commmercial
Com'l & Mil.
72423L15
72203L15
72213L15
Military
72423L10
72423L12
72203L12
72213L12
72423L25
72203L25
72213L25
72203L10
72213L10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
tA
Clock Cycle Frequency
Data Access Time
100
2
—
7.5
—
2
83.3
8
—
2
66.7
10
—
3
40
15
Mhz
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
—
—
—
—
—
—
—
—
—
—
—
—
6.5
6.5
—
—
—
—
—
12
5
—
—
—
—
—
—
—
—
—
—
12
—
7
15
6
—
––
—
—
—
—
—
—
—
—
15
—
8
25
10
10
6
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Time
Clock Low Time
5
6
Data Set-up Time
3
4
tDH
Data Hold Time
0
0
1
1
tENS
tENH
tRS
Enable Set-up Time
3
3
4
6
Enable Hold Time
Reset Pulse Width(1)
0
0.2
12
12
12
––
0
1
1
10
10
10
10
0
15
15
15
—
0
25
25
25
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
3
3
3
3
tOHZ
tWFF
tREF
tAF
3
3
7
3
8
3
7.5
7.5
7.5
7.5
5
—
—
—
—
5
8
—
—
—
—
6
10
10
10
10
—
—
—
—
—
10
8
8
tAE
8
tSKEW1 Skew time between Read Clock &
Write Clock for Empty Flag &Full Flag
—
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
22
—
22
—
28
—
40
—
ns
NOTES:
3111 tbl 06
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
1.1KΩ
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
D.U.T.
30pF*
1.5V
680Ω
See Figure 1
3111 tbl 07
3111 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.04
4
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Read Enables (
)—When the Read Enable (REN) is
REN
SIGNAL DESCRIPTIONS
INPUTS:
LOW, data is read from the RAM array to the output register
on the LOW-to-HIGH transition of the read clock (RCLK).
When the Read Enable (REN) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag(EF)willgoLOW,inhibitingfurtherreadoperations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enable (REN) is ignored when the FIFO is empty.
Data In (D) — Input for serial data.
CONTROLS:
Reset ( )—Reset is accomplished whenever the Reset
RS
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF)willberesettoHIGHaftertRSF.TheEmptyFlag(EF)and
Programmable Almost-Empty Flag (PAE) will be reset to low
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Output Enable ( )—When Output Enable (OE) is en-
OE
abled (LOW), the output buffer receives data from the output
register. When Output Enable (OE) is disabled (HIGH), the Q
data output is in a high-impedance state.
Write Enable 2/Load (WEN2/ )—This is a dual-purpose
LD
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth expan-
sion. If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset
(RS = LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load
(WEN2/LD)isHIGH, datacanbeloadedintotheinputregister
and RAM array on the LOW-to-HIGH transition of every write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of any on-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) and
Write Enable 2/Load (WEN2/LD) are ignored when the FIFO
is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS
= LOW). The IDT72423/72203/72213 devices contain four 8-
bit offset registers which can be loaded with data on the
Program Inputs (P0 - P7). See Figure 3 for details of the size
of the registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/
LD) are set LOW, data on the Program Inputs (P0 - P7) are
written into the Empty (Least Significant Bit) offset register on
the first LOW-to-HIGH transition of the write clock (WCLK).
Data is written into the Empty (Most Significant Bit) offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK), into the Full (Least Significant Bit) offset
register on the third transition, and into the Full (Most Signifi-
cant Bit) offset register on the fourth transition. The fifth
transition of the write clock (WCLK) again writes to the Empty
(Least Significant Bit) offset register.
Write Clock (WCLK)—A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or coinci-
dent.
Write Enable 1 (
)—If the FIFO is configured for
WEN1
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAMarrayontheLOW-to-HIGHtransitionofeverywriteclock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go high after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
EmptyFlag(EF)andProgrammableAlmost-EmptyFlag(PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or coinci-
dent.
5.04
5
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK(1)
Selection
However, writing all offset registers does not have to occur
atonetime. Oneortwooffsetregisterscanbewrittenandthen
bybringingtheWriteEnable2/Load(WEN2/LD)pinHIGH,the
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence
is written.
LD
WEN1
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
1
0
1
No Operation
Write into FIFO
No Operation
ProgramInputs(P0-P7)—Flagoffsetsontheseinputsare
entered into the programmable offset registers on the rising
edge of WCLK when LD and WEN are LOW.
3111 tbl 08
Figure 2. Write Offset Register
72423 - 64 x 1-BIT
6 5
72203 - 256 x 1-BIT
72213 - 512 x 1-BIT
8
8
8
8
0
8
8
8
8
7
7
0
0
0
0
8
8
8
8
0
7
7
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
0
0
0
0
(MSB)
0
6 5
0
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
0
(MSB)
0
3111 drw 05
Figure 3. Offset Register Location and Default Values
5.04
6
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
writes for the IDT72203, (512-m) writes for the IDT72213. The
offset “m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable
Almost-Full Flag (PAF) will go LOW at Full-7 words.
TheProgrammableAlmost-FullFlag(PAF)issynchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
OUTPUTS:
Full Flag ( )—The Full Flag (FF) will go LOW, inhibiting
FF
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 64 writes for the IDT72423, 256 writes for the IDT72203,
512 writes for the IDT72213.
The Full Flag (FF) is synchronized with respect to the LOW-
to-HIGH transition of the write clock (WCLK).
Programmable Almost-Empty Flag (
)—The Pro-
PAE
grammable Almost-Empty Flag (PAE) will go LOW when the
read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty offset registers. If no reads
are performed after Reset the Programmable Almost-Empty
Flag (PAE) will go HIGH after "n+1" for the IDT72423/72203/
72213. If there is no Empty offset specified, the Program-
mable Almost-Empty Flag (PAE) will go LOW at Empty+7
words.
Empty Flag ( )—The Empty Flag (EF) will go LOW,
EF
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag (
)—The Program-
PAF
The Programmable Almost-Empty Flag (PAE) is synchro-
nized with respect to the LOW-to-HIGH transition of the read
clock (RCLK).
mable Almost-Full Flag (PAF) will go LOW when the FIFO
reaches the Almost-Full condition. If no reads are performed
after Reset (RS), the Programmable Almost-Full Flag (PAF)
will go LOW after (64-m) writes for the IDT72423, (256-m)
Data Outputs (Q) — Output for serial data.
TABLE 1: STATUS FLAGS
NUMBER OF WORDS IN FIFO
72423
72203
72213
0
1 to n(1)
FF
H
H
H
H
L
PAF
H
PAE
L
EF
L
0
1 to n(1)
0
1 to n(1)
H
L
H
H
H
(n+1) to (64-(m+1))
(64-m)(2) to 63
64
(n+1) to (256-(m+1))
(256-m)(2) to 255
256
(n+1) to (512-(m+1))
(512-m)(2) to 511
512
H
H
L
H
L
H
H
3111 tbl 09
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
5.04
7
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
RS
RS
REN
tRSS
t
RSR
t
RSS
RSS
t
t
RSR
RSR
WEN1
t
WEN2/LD(1)
EF, PAE
tRSF
tRSF
FF, PAF
tRSF
(2)
OE = 1
OE = 0
Q
3111 drw 05
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as
a load enable for the programmable flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
5.04
8
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
CLK
t
CLKH
tCLKL
WCLK
D
t
DH
t
DS
DATA IN VALID
t
ENH
t
ENS
NO OPERATION
NO OPERATION
WEN1
WEN2/
(If Applicable)
tWFF
tWFF
FF
RCLK
REN
(1)
SKEW1
t
2655 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 5. Write Cycle Timing
5.04
9
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
CLK
tCLKL
tCLKH
RCLK
REN
t
ENH
tENS
NO OPERATION
t
REF
tREF
EF
Q
tA
VALID DATA
tOLZ
t
OHZ
t
OE
OE
(1)
SKEW1
t
WCLK
WEN1
WEN2
2655 drw 08
Note:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle
Timing
Figure 6. Read Cycle Timing
5.04
10
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
D
D1
D2
D3
D0 (First Valid Write)
tENS
WEN1
WEN2
(If Applicable)
(1)
tFRL
tSKEW1
RCLK
EF
tREF
REN
Q
tA
tA
D0
D1
tOLZ
tOE
OE
2655 drw 09
Note:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
5.04
11
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK
t
DS
tDS
t
SKEW1
tSKEW1
DATA WRITE
D
t
WFF
t
WFF
tWFF
FF
WEN1
WEN2
(If Applicable)
RCLK
REN
tENH
tENH
t
ENS
tENS
tA
LOW
OE
Q
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.04
12
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
t
DS
t
DS
D
DATA WRITE 1
DATA WRITE 2
tENH
tENH
tENS
t
t
ENS
ENS
WEN1
tENH
t
ENH
t
ENS
WEN2
(If Applicable)
(1)
FRL
(1)
tFFL
t
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN
LOW
OE
Q
tA
DATA READ
DATA IN OUTPUT REGISTER
2655 drw 11
Note:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
5.04
13
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
CLKH
tCLKL
(4)
WCLK
WEN1
t
t
ENS
ENS
t
t
ENH
ENH
WEN2
(If Applicable)
tPAF
(1)
Full - (m+1) words in FIFO
Full - m words in FIFO(2)
PAF
(3)
tSKEW2
t
PAF
RCLK
REN
t
ENS
tENH
2655 drw 12
NOTES:
1. PAF offset = m.
2. 64 - m words in for IDT72423, 256 - m words in FIFO for IDT72203, 512 - m words for IDT72213.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAFto change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.04
14
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
WEN1
tENH
tENH
tENS
tENS
WEN2
(If Applicable)
(1)
n words in FIFO
n+1 words in FIFO
PAE
(2)
tPAE
tSKEW2
tPAE
(3)
RCLK
REN
tENS tENH
2655 drw 13
NOTES:
1. PAE offset = n.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAEto change during that clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN1
tDS
tDH
P0 - P7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
2655 drw 14
Figure 12. Write Offset Registers Timing
5.04
15
IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
are for 64/256/512 bits or less. In this configuration, the Write
Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the
pin operates as a control to load and read the programmable
flag offsets.
OPERATING CONFIGURATIONS
SINGLEDEVICECONFIGURATION—AsingleIDT72423/
72203/72213maybeusedwhentheapplicationrequirements
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
READ CLOCK (RCLK)
READ ENABLE (REN)
IDT
72423/
WRITE ENABLE 2/LOAD (WEN2/LD)
OUTPUT ENABLE (OE)
72203/
DATA OUT (Q)
72213
DATA IN (D)
FULL FLAG (FF)
EMPTY FLAG (EF)
PROGRAMMABLE (PAF)
PROGRAM INPUTS (P0 - P7)
PROGRAMMABLE (PAE)
3111 drw 16
Figure 14. Block Diagram of Single 64 x 1/256 x 1/512 x 1 Synchronous FIFO
DEPTH EXPANSION—The IDT72423/72203/72213 can
be adapted to applications when the requirements are for
greater than 64/256/512 words. The existence of two enable
pins on the write port facilitates depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth
expansion configuration thus the Programmable flags are set
to the default values. Two read enables can be created by
adding a two-input AND gate to the REN line of the FIFO.
Depth expansion is possible by using one enable input for
system control while the other enable input is controlled by
expansion logic to direct the flow of data. A typical application
would have the expansion logic alternate data access from
one device to the next in a sequential manner. The IDT72423/
72203/72213 operates in the Depth Expansion configuration
when the following conditions are met:
1.The WEN2/LD pin is held HIGH during Reset so that this
pin operates a second Write Enable.
2.An external two-input AND gate is used to create two
read enables, REN1 and REN2. The output of the AND
gate is tied to the REN pin of the FIFO device, one input
of the AND gate is designated REN1, the other REN2.
3.External logic is used to control the flow of data.
Please see the Application Note "Depth Expansion of IDT's
Synchronous FIFOs Using the Ring Counter Approach" for
details of this configuration.
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK Commercial (0
°
C to +70
°C)
B
Military (–55
°
C to +125 C)
°
Compliant to MIL-STD-883, Class B
TP
TD
SO
Plastic Thin DIP (300 mils wide)
Ceramic Thin DIP (300 mils wide)
Small Outline IC
10
12
15
25
Com'l. Only
Com'l. Only
Com'l and Mil.
Mil. Only
Clock Cycle Time (tCLK
)
Speed in Nanoseconds
L
Low Power
72423 64 x 1 Synchronous FIFO
72203 256 x 1 Synchronous FIFO
72213 512 x 1 Synchronous FIFO
3111 drw 18
5.04
16
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