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IDT72P51767L7-5BBI [IDT]

FIFO, 128KX40, 3.8ns, Asynchronous, CMOS, PBGA376;
IDT72P51767L7-5BBI
型号： IDT72P51767L7-5BBI
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

FIFO, 128KX40, 3.8ns, Asynchronous, CMOS, PBGA376

先进先出芯片
文件： 总88页 (文件大小：798K)
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1.8VMULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION  
5,242,880bits  
10,485,760bits  
IDT72P51767  
IDT72P51777  
•
User Selectable Bus Matching Options:  
FEATURES  
– x40 in to x40 out  
– x40 in to x20 out  
– x20 in to x20 out  
– x20in to x40out  
•
Choose from among the following memory density options:  
IDT72P51767  
IDT72P51777  
Total Available Memory = 5,242,880 bits  
Total Available Memory = 10,485,760 bits  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
User selectable I/O: 1.5V HSTL or 1.8V eHSTL  
100% Bus Utilization, Read and Write on every clock cycle  
Selectable Back off one (BOI) or IDT standard mode of operation  
Ability to operate on packet or word boundaries  
Mark and Re-Write operation  
•
•
•
Configurable from 1 to 128 Queues  
Multiple default configurations of symmetrical queues  
Default multi-queue device configurations  
– IDT72P51767: 512 x 40 x 128Q  
Mark and Re-Read operation  
– IDT72P51777: 1,024 x 40 x 128Q  
Individual, Active queue flags (EF, FF, PAE, PAF)  
8 bit parallel flag status on both read and write ports  
Direct or polled operation of flag status bus  
Expansion of up to 256 queues  
•
Number of queues and queue sizes may be configured; at  
master reset, though serial programming, (via the queue  
address bus)  
•
•
•
•
•
•
166 MHz High speed operation (6ns cycle time)  
0.48ns access time  
Independent Read and Write access per queue  
Echo Read Clock available  
Internal PLL  
On-chip Output Impedance matching  
JTAG Functionality (Boundary Scan)  
Available in a 376-pin BGA, 1mm pitch, 23mm x 23mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
Green parts available, seeing Ordering Information  
FUNCTIONALBLOCKDIAGRAM  
10G DDR MULTI-QUEUE FLOW-CONTROL DEVICE  
ECHO CLOCK  
2
RADEN  
Q127  
WADEN  
FSTR  
ESTR  
RDADD  
8
WRADD  
REN  
Q126  
Q125  
8
RCLK  
WEN  
EREN  
WCLK  
OE  
Q
out  
D
in  
x40 or x20  
DATA IN  
x40 or x20  
DATA OUT  
EF  
FF  
PAE  
PAF  
PAFn  
PAEn  
Q0  
8
8
6724 drw01  
CIDTOandMtheMIDTElogRoaCretrIaAdemLarksAofInNtegDratedIDNevicDeTUechSnolTogyR,InIcAL TEMPERATURE RANGES  
JANUARY 2006  
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6724/1  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Table of Contents  
Features ......................................................................................................................................................................................................................... 1  
Description ...................................................................................................................................................................................................................... 5  
Pin configuration .............................................................................................................................................................................................................. 7  
Detailed Description ......................................................................................................................................................................................................... 8  
Pin Descriptions ............................................................................................................................................................................................................. 10  
Pin number table ........................................................................................................................................................................................................... 15  
Recommended DC operating conditions ........................................................................................................................................................................ 16  
Absolutemaximumratings.............................................................................................................................................................................................. 16  
DC electrical characteristics ............................................................................................................................................................................................ 17  
AC electrical characteristics ............................................................................................................................................................................................ 19  
Functional description .................................................................................................................................................................................................... 22  
Serial Programming.............................................................................................................................................................................................. 24  
Default Programming ............................................................................................................................................................................................ 27  
Parallel Programming ........................................................................................................................................................................................... 27  
Modes of operation ........................................................................................................................................................................................................ 29  
Standard mode operation ..................................................................................................................................................................................... 29  
IDT Standard mode vs. BOI mode ........................................................................................................................................................................ 29  
PLL on vs PLL off modes ...................................................................................................................................................................................... 30  
Read Queue Selection and Read Operation ......................................................................................................................................................... 33  
Switching Queues on the Write Port ...................................................................................................................................................................... 34  
Switching Queues on the Read Port ..................................................................................................................................................................... 44  
Flag Description ............................................................................................................................................................................................................ 52  
PAFn Flag Bus Operation .................................................................................................................................................................................... 52  
Full Flag Operation............................................................................................................................................................................................... 52  
Empty Flag Operation........................................................................................................................................................................................... 52  
Almost Full Flag .................................................................................................................................................................................................... 53  
Almost Empty Flag ................................................................................................................................................................................................ 53  
JTAG Interface............................................................................................................................................................................................................... 83  
JTAGAC electrical characteristics ................................................................................................................................................................................... 87  
Ordering Information ...................................................................................................................................................................................................... 88  
List of Tables  
Table 1 — Summary of the differences between the 4M MQ and 10G MQ ........................................................................................................................ 9  
Table 2 — DC andAC specifications (informative) ......................................................................................................................................................... 21  
Table 3 — IDTto XGMII Interface Mapping Schema ..................................................................................................................................................... 21  
Table 4 — Device programming mode comparison ........................................................................................................................................................ 22  
Table 5 — Setting the queue programming mode during master reset ............................................................................................................................. 23  
Table 6 — ID[2:0] and WRADD[7:5]/RDADD[7:5] Configuration .................................................................................................................................... 27  
Table 7 — Parallel Programming Mode Queue Configuration Example(1) ...................................................................................................................... 28  
Table 8 — WriteAddress Bus, WRADD[7:0]................................................................................................................................................................... 32  
Table 9 — ReadAddress Bus, RDADD[7:0] .................................................................................................................................................................. 33  
Table 10 — Write Queue Switch Operation .................................................................................................................................................................... 35  
Table 11 — Backup Usage when Re-entering a Queue ................................................................................................................................................. 43  
Table 13 — Same Queue Switch ................................................................................................................................................................................... 45  
Table 12 — Read Queue Switch Operation.................................................................................................................................................................... 45  
Table 14 — Flag operation boundaries & Timing ........................................................................................................................................................... 55  
Table 15 — Interface Data Rates ................................................................................................................................................................................... 57  
Table 16 — Bus-Matching Configurations ...................................................................................................................................................................... 58  
JANUARY18,2006  
2
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
List of Figures  
Figure 1. Multi-Queue Flow-Control Device Block Diagram............................................................................................................................................. 6  
Figure 2a. AC Test Load................................................................................................................................................................................................ 18  
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18  
Figure 3. HSTLTermination for XGMII........................................................................................................................................................................... 21  
Figure 4. Reference Signals .......................................................................................................................................................................................... 22  
Figure 5. Expansion for Unlimited Number of Multi-Queue Devices Example .................................................................................................................. 28  
Figure 6. Device Programming Hierarchy ..................................................................................................................................................................... 29  
Figure 7. DDR Read Operation with PLL ON................................................................................................................................................................. 30  
Figure 8. DDR Read Operation with PLL OFF............................................................................................................................................................... 30  
Figure 9. SDR Read Operation with PLL ON ................................................................................................................................................................. 31  
Figure 10. SDR Read Operation with PLL OFF ............................................................................................................................................................. 31  
Figure 11. Write Port Switching Queues Signal Sequence .............................................................................................................................................. 34  
Figure 12. Switching Queues Bus Efficiency ................................................................................................................................................................... 34  
Figure 13. Simultaneous Queue Switching ..................................................................................................................................................................... 35  
Figure 14.Application: Reading words from the MQ using the EOPbit to end the read operation..................................................................................... 36  
Figure 15. Output Data during a Queue Switch (SDR w/o PLL)...................................................................................................................................... 37  
Figure 16. Output Data during a Queue Switch (SDR w/ PLL) ....................................................................................................................................... 38  
Figure 17. Output Data during a Queue Switch (DDR w/ PLL) ....................................................................................................................................... 39  
Figure 18. Output Data during a Queue Switch (DDR w/o PLL) ..................................................................................................................................... 40  
Figure 19. Output Data during two Queue Switches (DDR w/ PLL) ................................................................................................................................ 41  
Figure 20. Output Data during two Queue Switches (DDR w/o PLL) .............................................................................................................................. 42  
Figure 21. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 44  
Figure 22. Switching Queues Bus Efficiency ................................................................................................................................................................... 44  
Figure 23. Simultaneous Queue Switching ..................................................................................................................................................................... 45  
Figure 24. MARK and Re-Write Sequence .................................................................................................................................................................... 46  
Figure 25. MARK and Re-Read Sequence ................................................................................................................................................................... 46  
Figure 26. MARKing a Queue - Write Queue MARK ...................................................................................................................................................... 47  
Figure 27. MARKing a Queue - Read Queue MARK ..................................................................................................................................................... 47  
Figure 28. UN-MARKing a Queue - Write Queue UN-MARK ......................................................................................................................................... 48  
Figure 29. UN-MARKing a Queue - Read Queue UN-MARK ........................................................................................................................................ 48  
Figure 30. Leaving a MARK active on the Write Port ...................................................................................................................................................... 49  
Figure 31. Leaving a MARK active on the Read Port ..................................................................................................................................................... 49  
Figure 32. Inactivating a MARK on the Write PortActive ................................................................................................................................................. 50  
Figure 33. Inactivating a MARK on the Read PortActive ................................................................................................................................................ 50  
Figure 34. DDR Source Synchronous CenterAligned Clocking .................................................................................................................................... 57  
Figure 35. SDR EdgeAligned Clocking ........................................................................................................................................................................ 57  
Figure 36. Bus-Matching ByteArrangement .................................................................................................................................................................. 59  
Figure 37. Master Reset ................................................................................................................................................................................................ 60  
Figure 38. Default Programming .................................................................................................................................................................................... 61  
Figure 39. WriteAddress/ReadAddress Programming ................................................................................................................................................... 62  
Figure 40. Serial Port Connection for Serial Programming .............................................................................................................................................. 63  
Figure 41. Serial Programming (2 Device Expansion) ................................................................................................................................................... 64  
Figure 42. SDR Write Queue Select, Write Operation and Full Flag Operation ................................................................................................................ 65  
Figure 43. DDR Write Operation, Write Queue Select, Full Flag Operation...................................................................................................................... 66  
Figure 44. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 67  
Figure 45. Full Flag Timing in Expansion Configuration.................................................................................................................................................. 68  
Figure 46. SDR Read Queue Select, Read Operation (IDT mode) ................................................................................................................................ 69  
Figure 47. DDR Read Operation, Read Queue Select, EF & PAE Flag Operation ......................................................................................................... 70  
Figure 48. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 71  
Figure 49. Standard Mode Pointers on Queue Re-entry for DDR Read Operation ......................................................................................................... 72  
Figure 50. BOI Mode Pointers on Queue Re-entry for DDR Read Operation ................................................................................................................. 72  
Figure 51. Read Queue Selection with Read Operations (IDT mode) (SDR mode, PLL = OFF) ..................................................................................... 73  
Figure 52. Read Queue Select, Read Operation and OE Timing .................................................................................................................................... 74  
Figure 53.Almost Full FlagTiming and Queue Switch .................................................................................................................................................... 75  
Figure 54.Almost Full FlagTiming ................................................................................................................................................................................. 75  
JANUARY18,2006  
3
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
List of Figures (Continued)  
Figure 55.Almost Empty FlagTiming ............................................................................................................................................................................. 76  
Figure 56. PAEn - Direct Mode - Status Word Selection ................................................................................................................................................. 77  
Figure 57. PAFn - Direct Mode - Status Word Selection ................................................................................................................................................. 77  
Figure 58. PAEn - Direct Mode, Flag Operation............................................................................................................................................................. 78  
Figure 59. PAFn - Direct Mode, Flag Operation............................................................................................................................................................. 79  
Figure 60. PAFn Bus - Polled Mode .............................................................................................................................................................................. 80  
Figure 61. Connecting two 10G MQ 128Q devices in Expansion Mode .......................................................................................................................... 81  
Figure 62. Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 ............................................................... 82  
Figure 63. Boundary ScanArchitecture ......................................................................................................................................................................... 83  
Figure 64. TAPController State Diagram ....................................................................................................................................................................... 84  
Figure 65. Standard JTAGTiming.................................................................................................................................................................................. 87  
JANUARY18,2006  
4
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
4userselectablebits as partofthe40bitword. Theuserwillbeabletopass  
alongparitybitsthroughtheMulti-Queuetouseforerrordetectioninaup/down  
stream device. The Multi-Queue device does not provide parity checking  
circuits.  
DESCRIPTION  
The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are  
singlechipsolutionscontainingupto128configurablequeues.Allqueueswithin  
thedevicehaveacommondatainputbus,Din[39:0](writeport)andacommon  
dataoutputbusQout[39:0],(readport).Datawrittenintothewriteportisdirected  
toarespectivequeueviaanintegratedde-multiplexfunction.Datareadfrom  
the read port is accessed from a given queue transparently via an internal  
multiplexoperation.Datawritesandreadscanbeperformedathighspeeds  
upto166MHzDDRallowingdataratesupto10Gigabits/s(OC-192). Byutilizing  
highspeedinterfacessuchas1.5VHSTL,coupledwithax40bitdatabusand  
10Mb of data storage, the 10G Multi-Queue can interface with the industry  
standard10Gigabits/secMediaIndependentInterface(XGMII)toallowhigh  
speeddatatransmissionover10GEthernet andSONETlinecards.Datawrite  
andreadoperationsaretotallyindependentofeachother.TheWriteClockand  
ReadClockcanoperate atindependentfrequencies.Adifferentqueuemay  
beselectedonthewriteportandreadportorbothportsmayselectthesame  
queuesimultaneously. Multipleclockingschemesareofferedforthisdeviceas  
well. Theusercanutilizeeither singleended ordifferential clockingforDDR  
readoperations.DDRwriteoperationutilizeasingleendedclock.SDRwrite  
andreadoperationsutilizeasingleendedclock.  
InBackoffOnemode,theusercanswitchqueueswithouthavingtoreadthe  
lastpipelineddatawordthatisstoredintheoutputregisterwhichinIDTstandard  
modeisrequiredtobereadoutduringaqueueswitch. Thelastpipelineddata  
wordinBOImodeisretainedintheoutputdataregisteruntilitisactivelyread.  
AMarkandRe-writeandaMarkandRe-readfunctionareavailableonthe  
writeandreadportsrespectively.Thesefunctionsallowsforamarklocationto  
be independently issued on the read and/or write ports, in their respective  
queues. The option to reset a given queue to the mark location effectively  
dropping data written into the queue or allow data to be read again from the  
device.  
Thedevicesofferadefaultconfigurationuponreset,offering128 symmetrical  
queuesconfiguredat start-up,whichmeanstheusercanprogram thenumber  
ofqueues todividethe10Mb/5Mbofmemorydependingonthedevice.The  
Multi-Queuescanevenbeprogrammedtosupportonesinglequeuetobeused  
as a FIFO for high performance applications of sequential queuing. The  
programmableflagpositionsarealsouserprogrammable.Iftheuserdoesnot  
wish to program the multi-queue device, a default option is available that  
configuresthedeviceinapredeterminedmanner.AMasterResetlatchesin  
allconfigurationsetuppinsandmustbeperformedbeforeprogrammingofthe  
devicecantakeplace.  
Themulti-queueflow-controldeviceshavethecapabilityofoperatingitsI/O  
ineither1.5VHSTL,or1.8VeHSTL mode.ThetypeofI/Oisselectedviathe  
IOSELinput.Thecoresupplyvoltage(VCC)tothemulti-queueisalways1.8V,  
however the output levels can be set independently via a separate supply,  
VDDQ. Thepackageusedwillbea23mmx23mm,BB-376BGApackagefor  
betternoiseimmunityandgroundbounceprevention.  
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehas  
afullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard  
TestAccessPortandBoundaryScanArchitecture.  
ThedevicesprovideFullflagandEmptyflagstatusforthequeueselected  
forwriteandreadoperationsrespectively.AlsoaProgrammableAlmostFull  
(PAF)andProgrammableAlmostEmpty(PAE)flagforeachqueueisprovided.  
Two8bitprogrammableflagbusses (PAFn,PAEn)areavailable,providing  
status of queues that are not the present queue selected for write or read  
operations.When8orfewerqueues areconfiguredinthedevice,theseflag  
busses provide an individual flag per queue, when more than 8 queues are  
used;thequeuestatusismultiplexedthroughthe8stuslines.Themultiplexing  
canbe configuredeithera PolledorDirectmode ofbus.  
BusMatchingisavailableonthisdevice;eitherportcanbe x20bitsorx40  
bitswide. WhenBusMatchingisusedthedeviceensuresthelogicaltransfer  
ofdatathroughput.. Witha40databitsconfiguration paritycheckingandpacket  
taggingisachievableifdesired.Paritycheckingisavailablethroughtheuseof  
JANUARY18,2006  
5
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
D
in  
x20, x40  
2
D
- D  
39  
0
WCLK  
WEN WCS  
TMS  
TDI  
INPUT  
DEMUX  
JTAG  
Logic  
TDO  
TCK  
8
WRADD  
WADEN  
Write Control  
Logic  
TRST  
Write Pointers  
BOI  
BOI  
Mode Logic  
8
PAF  
PAEn  
FSTR  
PAFn  
8
General Flag  
Monitor  
FSYNC  
Upto 128  
FIFO  
Queues  
FXO  
FXI  
EF  
Active Q  
Flags  
PAE  
10 Mbit  
Dual Port  
Memory  
Active Q  
Flags  
FF  
PAF  
PAE  
SI  
SO  
SCLK  
General Flag  
Monitor  
Serial  
Multi-Queue  
Programming  
ESTR  
ESYNC  
EXI  
SENI  
SENO  
EXO  
Read Pointers  
FM  
8
4
Reset  
Logic  
BM[3:0]  
RDADD  
RADEN  
RCS  
Read Control  
Logic  
MAST  
REN  
RCLK  
QSEL[2:0]  
Device ID  
3 Bit  
OUTPUT  
MUX  
ERCLK  
PLL  
PAE/ PAF  
Offset  
ERCLK  
2
DFM  
OUTPUT  
REGISTER  
MRS  
6724 drw02  
IO Level Control  
Vref  
OE  
Q
- Q  
0
39  
Q
x20, x40  
out  
Figure 1. Multi-Queue Flow-Control Device Block Diagram  
JANUARY18,2006  
6
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINCONFIGURATION  
A1 BALL PAD CORNER  
A
TRST  
GND  
GND  
GND  
GND  
GND  
GND  
D11  
D12  
D13  
D9  
D10  
D14  
D7  
D8  
D5  
D6  
D3  
D4  
D1  
D2  
TMS  
TCK  
TDI  
TDO  
GND  
ID2  
ID1  
ID0  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q11  
Q12  
Q16  
Q13  
Q14  
Q15  
GND  
GND  
GND  
GND  
GND  
GND  
B
C
D
E
F
D0  
Q10  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
D17  
D16  
D19  
D15  
D18  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
GND  
GND  
GND  
GND  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
Q17  
Q18  
Q19  
FF  
EREN  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
GND  
GND  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDD  
DNC  
ERCLK  
ERCLK  
PAE5  
V
DDQ  
V
DDQ  
VDDQ  
V
DDQ  
PAE7 PAE6  
PAE4 PAE3  
PAF6  
PAF3  
PAF0  
PAF7  
PAF4  
PAF1  
PAF  
PAF5  
PAF2  
G
H
J
VDD  
VDDQ  
VDDQ  
VDDQ  
V
DD  
VDD  
PAE2  
REN  
PAE1 PAE0  
V
DD  
VDD  
RCS  
AVDD  
AVSS  
VREF FSYNC FXO  
V
DD  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
V
DD  
RCLK  
AVSS  
K
L
SENI SENO  
SCLK  
SO  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
SI  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PAE  
AVSS  
AVDD  
ZQ  
GND  
GND  
GND  
WCS  
M
N
P
R
T
VREF  
WCLK WADEN GND  
WEN  
EF  
WRADD0 WRADD1 WRADD2 GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
WRADD3 WRADD4 WRADD5  
WRADD6 WRADD7  
V
DD  
GND  
GND  
V
DD  
BOI  
ESYNC EXO  
OE  
VDD  
VDD  
V
DD  
ESTR  
EXI  
V
DD  
VDD  
RDADD1 RDADD0  
MRS  
FXI  
FSTR  
FM  
VDDQ  
VDDQ  
V
DDQ  
RADEN  
VDDQ  
U
V
RDADD4 RDADD3 RDADD2  
RDADD7 RDADD6 RDADD5  
MAST  
PLLON  
TP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
D20  
D23  
GND  
D21  
D24  
D26  
V
DD  
V
DD  
V
DD  
V
DD  
V
DD  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
V
DD  
V
DD  
V
DD  
VDD  
VDD  
W
D22  
V
DD  
V
DD  
V
DD  
VDD  
V
DD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
V
DD  
Q22  
Q24  
Q21  
Q20  
Y
GND  
D25  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
Q23  
GND  
GND  
AA  
BB  
GND  
GND  
GND  
GND  
D27  
D28  
D29  
D30  
D31  
D32  
D33  
D34  
D35  
D36  
D37  
D38  
D39  
QSEL1 DFM  
BM2  
BM1  
Q39  
BM3  
Q37  
Q38  
Q35  
Q36  
Q33  
Q34  
Q31  
Q32  
Q29  
Q30  
Q27  
Q28  
Q25  
Q26  
GND  
GND  
GND  
GND  
QSEL0 QSEL2  
BM0  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
6724 drw03  
NOTE:  
1. DNC - Do Not Connect.  
PBGA (BB376-1, order code: BB)  
TOP VIEW  
JANUARY18,2006  
7
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus  
forthatqueue.Conversely,thereadporthasanEmptyflag,providingstatus  
ofthedatabeingreadfromthequeueselectedonthereadport.Aswellasthe  
Emptyflagthedeviceprovidesadedicatedalmostemptyflag.Thisalmostempty  
flagissimilartothealmostemptyflagofaconventionalIDTFIFO.Thedevice  
provides a user programmable almost empty flag for each 128 queues and  
whena respective queue is selectedonthe readport, the almostemptyflag  
providesstatusforthatqueue.  
DETAILEDDESCRIPTION  
MULTI-QUEUE STRUCTURE  
The IDT multi-queue flow-control device has a single data input port and  
singledataoutputportwithupto128FIFOqueuesinparallelbufferingbetween  
thetwoports.Theusercansetupbetween1and128Queueswithinthedevice.  
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing  
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,  
independentofoneanother.  
PROGRAMMABLE FLAG BUSSES  
MEMORYORGANIZATION/ALLOCATION  
Inadditiontothesededicatedflags,full&almostfullonthewriteportandOutput  
Ready&almostemptyonthereadport,therearetwoflagstatus busses.An  
almostfullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostempty  
flagstatusbusisprovided,againthisbusis8bitswide.Thepurposeofthese  
flagbussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels  
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,  
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby  
the user) for each of the 128 queues in the device.  
IntheIDT72P51767/72P51777multi-queueflow-controldevicestheuser  
hastheoptionofutilizing1to128queues,thereforethe8bitflagstatusbusses  
aremultiplexedbetweenthe128queues,aflagbuscanonlyprovidestatusfor  
8ofthe128queuesatanymoment,thisisreferredtoasa“StatusWord”,such  
thatwhenthebusisprovidingstatusofqueues1through8,thisisstatusword  
1,whenitis queues 9through16,this is status word2andsoonuptostatus  
word16.Iflessthan128queuesaresetupinthedevice,therearestill4status  
words,suchthatin“Polled”modeofoperationtheflagbuswillstillcyclethrough  
4status words. Ifforexample only22queues are setup, status words 1and  
2willreflectstatusofqueues1through8and9through16respectively.Status  
word3willreflectthestatusofqueues17through22ontheleastsignificant6  
bits,themostsignificant2bitsoftheflagbusaredon’tcare.Theremainingstatus  
words are not used as there are no queues to report.  
The flag busses are available in two user selectable modes of operation,  
“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus  
ofeachstatuswordsequentially,thatis,oneachrisingedgeofaclocktheflag  
busisupdatedtoshowthestatusofeachstatuswordinorder.Therisingedge  
ofthewriteclockwillupdatethealmostfullbus andarisingedgeontheread  
clockwillupdatethealmostemptybus.Themodeofoperationisalwaysthesame  
forboththealmostfullandalmostemptyflagbusses.Whenoperatingindirect  
mode,thestatuswordontheflagbusisselectedbytheuser.Sotheusercan  
actuallyaddressthestatuswordtobeplacedontheflagstatusbusses,these  
flagbussesoperateindependentlyofoneanother.Addressingofthealmostfull  
flagbusisdoneviathewriteportandaddressingofthealmostemptyflagbus  
is done via the read port.  
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing  
256x40bits.Whentheuserisconfiguringthenumberofqueuesandindividual  
queuesizestheusermustallocatethememorytorespectivequeues,inunits  
ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem  
isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany  
given queue must be in increments of 256 x40. For the IDT72P51767 and  
IDT72P51777theTotalAvailableMemoryis1024and512blocksrespectively  
(a blockbeing256x40). Queues canbe builtfromthese blocks tomake any  
size queue desired and any number of queues desired.  
BUS WIDTHS  
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.  
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport  
andoutputportcanbeeitherx20,x40bitswide,thereadandwriteportwidths  
canbesetindependentlyofoneanother.Becauseaportsarecommontoall  
queuesthewidthofthequeuesisnotindividuallyset.Theinputwidthofallqueues  
are the same andthe outputwidthofallqueues are the same.  
WRITING TO & READING FROM THE MULTI-QUEUE  
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete  
queueviathewritequeueaddressinput.Conversely,databeingreadfromthe  
devicereadportisreadfromaqueueselectedviathereadqueueaddressinput.  
Data can be simultaneously written into and read from the same queue or  
differentqueues.Onceaqueueisselectedfordatawritesorreads,thewriting  
andreadingoperationisperformedinthesamemannerasaconventionalIDT  
synchronous FIFO, utilizing clocks and enables, there is a single clock and  
enable per port. When a specific queue is addressed on the write port, data  
placedonthedatainputsiswrittentothatqueuesequentiallybasedontherising  
edgeofawriteclockprovidedsetupandholdtimesaremet.Conversely,data  
isreadontotheoutputportafteranaccesstimefromarisingedgeonaread  
clock.  
Theoperationofthewriteportiscomparabletothefunctionofaconventional  
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon  
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput  
providesstatusoftheselectedqueue.Whenaqueueisselectedontheoutput  
port, the next word in that queue will be available for reading on the output  
register.Allsubsequentwordsfromthatqueuerequireanenabledreadcycle.  
Datacannotbereadfromaselectedqueueifthatqueueisempty,thereadport  
providesanEmptyflagindicatingwhendatareadoutisvalid.Iftheuserswitches  
toaqueuethatisempty,thelastwordfromthepreviousqueuewillremainon  
theoutputbus.ThedevicecanoperateinIDTStandardmodeorBOImode.  
InIDTStandardmodethereadportprovidesawordtotheoutputbus(Qout)  
foreachclockcyclethatRENisasserted.RefertoFigure46,SDRReadQueue  
Select, Read Operation (IDT Mode).  
EXPANSION  
Expansionofmulti-queuedevicesispossible.Expansionachieveseither  
depthorqueueexpansion.DepthExpansionmeansexpandingthedepthsof  
individual queues. Queue expansion means increasing the total number of  
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore  
memoryblockswithinamulti-queuedevicecanbeallocatedtoafewernumber  
ofqueuesto increasethedepthofeachqueue.Forexample,depthexpansion  
of2devicesprovidesthepossibilityof2queues,eachqueuebeingsetupwithin  
asingledeviceutilizingallmemoryblocksavailabletoproduceasinglequeue.  
This is thedeepestqueuethatcansetupwithinadevice.  
Forqueueexpansionamaximumnumberof256queues(2x128queues)  
maybesetup.Iffewerqueuesaredesired,thenmorememoryblockswillbe  
availabletoincreasequeuedepthsifdesired.RefertoFigure61,Connecting  
two 10G Multi-Queue 128Q devices in Expansion Mode, and Figure 62,  
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected  
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost  
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice  
providesauserprogrammablealmostfullflagforall128queuesandwhena  
JANUARY18,2006  
8
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Connectingthreeormore10GMulti-Queue128QinExpansionmodeusing  
WRADD bit 7 / RDADD bit 7 for device connection details.  
- Three “echo” output pins: ERCLK, ERCLK, and EREN  
usedforSourceSynchronousdataontheoutput.Datacanbecenter  
alignedontheEchoClockorissuedontherisingedgeoftheEchoClock.  
-AccessTime(Ta)reducedto0.48nswithEchoClockusedforfaster  
Synchronizeddatadeliverydownstream  
10Gbps MULTI-QUEUE DIFFERENCES FROM THE 4M MULTI-QUEUE  
The 10G Multi-Queue was developed to support very high performance  
applicationsthatneeded10Gb/sofbandwidth,andtheflexibilityofbuffering  
packetsofinformationinlargeburstssuchasJumboEthernetpacketsthatcan USER FLEXIBILITY IMPROVEMENTS  
beaslargeas9KBs. Listedbelowarethedifferencesbetweenthe10GMulti-  
Queueandtheprevious4MMulti-Queuewithdescriptionsoftheenhancements  
madetosupportperformancefunctionsinqueuing.  
• 10Mbitsofstorageandqueuingdensityforsupportlargepacketframes  
suchasJumboEthernet  
• DuringaQueueswitch,BOImodepreservesthedatawordintheoutput  
registeruntilit'sread.  
PERFORMANCEENHANCEMENTS  
• “Real Time” Flags, for both DDR and SDR.  
- PAF/PAE have 1 more cycle (WCLK/RCLK) latency (3 vs. 2)  
- Tskew of EF/PAE with respect to WCLK has 1 WCLK cycle delay.  
- Tskew of FF/PAF with respect to RCLK has 1 RCLK cycle delay.  
• ProgrammableDefaultconfigurationof128,64,32,16,8or4symmetrical  
queues are available using DFM, QSEL[2:0] pins  
• 333.34 Mbps (per pin) High speed data rate in DDR mode  
• x40Dinandx40Qout(8morepinsforuserselectableoperationsuchas  
paritycheckorpackettagging)  
• Electricalcompatibilityto802.3aeXGMIIspecificationforpassive  
interconnectiontoEthernetdevices.  
- Single clocking in DDR and SDR, PLL on/off Mode. (PAD_PLLON  
pin) allowing data latency to be the same for SDR and DDR.  
• Burstof2timingandinterfacelogic  
• UserselectableI/O:1.5VHSTL,or1.8VeHSTLforfasterswitchingI/O  
• Expansionofupto256queuesand/or80Mbitlogicalconfigurationusing  
upto8multi-queuedevices  
• Defaultflagoffsetvalueisdefinedaccordingtobusmatchingconfiguration  
- The PAE flag can be used as a packet indicator  
-Outputimpedancematchingforsignalqualityontheoutputpins.  
- More Data latency (same cycle on write, 1 cycle on read)  
TABLE 1 — SUMMARY OF THE DIFFERENCES BETWEEN  
THE 4M MQ AND 10G MQ  
FEATURE  
4M MQ (IDT72P51769)  
10M MQ (IDT72P51777)  
DataTransferModes  
BusWidth  
SDR  
x36, x18, x9  
no  
SDR, DDR  
x40, x20  
yes  
XGMIICompatibility  
Accesstime(ta)  
3.6 ns max  
4Mb  
0.48nsmax  
10Mb  
DataStorageCapacity  
DataThroughput  
OperatingFrequency  
ConfigurableQueues  
Package  
7.2Gbps  
10Gbps  
200mhz  
166mhz  
Up to 128  
256pinPBGA  
no  
Up to 128  
376 pin BGA  
yes  
OutputImpedanceTechnology  
I/OVoltages  
1.5V,1.8V,2.5V  
no  
1.5V,1.8V  
yes  
EchoreadClock  
ModesofOperation  
OutputdataClocking  
FWFT,IDT,Packet  
Edgealigned  
IDT, BOI  
Centeredaligned  
JANUARY18,2006  
9
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS  
Symbol &  
(Pin No.)  
Name  
I/OTYPE  
Description  
BM [3:0]  
BusMatching  
1.8V LVTTL Thesepinsdefinethebuswidthanddatatransferrate(DDR/SDR)oftheinputwriteportandtheoutput  
(BM3-BB13  
BM2-AA12  
BM1-BB12  
BM0-BB11)  
INPUT  
readportofthedevice. Thebuswidths/dataratesaresetduringaMasterRestcycle.TheBM[3:0]signals  
mustmeetthesetupandholdtimerequirementsofMasterResetandmustnottoggle/changestateafter  
a MasterReset cycle.  
BOI  
(P20)  
BackOffOne  
Mode  
HSTL  
INPUT  
WheninBOI,dataisback-offonepositioninwhichPacket1andPacket2areoutagainduringsecond  
QueueSwitch.Seesectionon10GbpsMulti-queueDifferencesfromthe4Mmulti-queue,previouspage.  
D[39:0]  
(See Pin No.  
tablefordetails)  
DataInputBus  
HSTL  
INPUT  
These are the 32data inputpins. Data is writtenintothe device via these inputpins onthe risingedge  
ofWCLKprovidedthatWEN is LOW. Anyunuseddata inputpins shouldbe tiedHIGH.  
D[39:36]userdefinableinputbits  
D[33]userdefinableD[32]userdefinableD[31:0]datainputbits  
DFM  
(AA11)  
DefaultMode  
EmptyFlag  
1.8V LVTTL The10Gmulti-queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyvia  
INPUT  
theserialport,ortheusercanusethedefaultmethod.IfDFMisLOWatMasterResetthenserialmode  
willbeselected,ifDFMisHIGHthendefaultmodeisselected.  
EF  
(N21)  
HSTL  
OUTPUT  
TheEmptyFlag(EF)providesvalidstatusfortheselectedqueue.TheEmptyFlagindicatestheselected  
queue is empty, all words have been read. This flag is delayed to match the data output path delay.  
ERCLK  
(E22)  
Echo Read  
Clock  
HSTL  
OUTPUT  
TherisingedgeofthisclockiscenteredalignedwithQoutdata.  
Read Clock Echo is the inverse of ERCLK.  
ERCLK  
(F20)  
Echo Read  
Clock  
HSTL  
OUTPUT  
EREN  
(E21)  
Echo Read  
Enable  
HSTL  
OUTPUT  
EchoReadEnable output, usedinconjunctionwithERCLKandERCLK.  
ESTR  
(R20)  
PAEn Flag Bus  
HSTL  
INPUT  
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK  
andtheRDADDbustoselectaquadrantofqueuestobeplacedontoPAEnoutput.Aquadrantaddressed  
viatheRDADDbusisselectedontherisingedgeofRCLKprovidedthatESTRisHIGH.IfPolledoperation  
hasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbusselectioncannotbemade,  
(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompletedandSENOhasgoneLOW.  
ESYNC  
(P21)  
PAEn Bus Sync  
HSTL  
OUTPUT  
ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus  
duringPolledoperationofthePAEnbus.DuringPolledoperationeachquadrantofqueuestatus flags  
is loadedontothePAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads  
quadrant1ontoPAEn,thesecondRCLKrisingedgeloadsquadrant2andsoon.ThefifthRCLKrising  
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed  
ontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theESYNC  
outputwillbeLOW.  
EXI  
(R21)  
PAEnBus  
ExpansionIn  
HSTL  
INPUT  
TheEXIinputisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolledPAEn bus  
operationhasbeenselected.EXIofdevice‘N’connectsdirectlytoEXOofdevice‘N-1’.TheEXIreceives  
atokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputmustbetiedLOWifthe  
PAEnbus is operatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinputmustbe  
connectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdeviceshouldbe  
tiedLOW,whendirectmodeisselected.  
EXO  
(P22)  
PAEnBus  
ExpansionOut  
HSTL  
OUTPUT  
EXOis anoutputthatis usedwhenmulti-queuedevices areconnectedinexpansionmodeandPolled  
PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This  
pinpulses whendevice Nhas placedits final(4th)quadrantontothe PAEnbus withrespecttoRCLK.  
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising  
edgethefirstquadrantofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthroughthechain  
andEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice  
inthechainprovides synchronizationtotheuserofthis loopingevent.  
FF  
(E1)  
Full Flag  
HSTL  
OUTPUT  
ThispinprovidesthefullflagoutputfortheactiveQueue,thatis,thequeueselectedontheinputportfor  
write operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera queue  
selection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue  
providedFF is HIGH.This flaghas High-Impedancecapability,this is importantduringexpansionof  
JANUARY18,2006  
10  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol &  
Pin No.  
Name  
I/OTYPE  
Description  
FF (Continued) Full Flag  
(E1)  
HSTL  
OUTPUT  
devices,whentheFF flagoutputofupto8devicesmaybeconnectedtogetheronacommonline.The  
devicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutputintoHigh-  
Impedance.WhenaqueueselectionismadeonthewriteportthisoutputwillswitchfromHigh-Impedance  
controlonthenextWCLKcycle.This flagis assertedsynchronous toWCLK.  
FM  
Flag Mode  
1.8V LVTTL ThispinissetupbeforeaMasterResetandmustnottoggleduringanydeviceoperation.Thestateofthe  
(U2)  
INPUT  
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled  
orDirectmode.IfFMis HIGH,Polledmodeis selected,ifFMLOW,Directmodeis selected.  
FSTR  
(T2)  
PAFn Flag  
BusStrobe  
HSTL  
INPUT  
IfdirectmodeforthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLKand  
the WRADDbus toselecta quadrantofqueues tobe placedontothe PAFnbus outputs. Aquadrant  
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If  
polledoperations has beenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus  
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted  
andSENOhas gone LOW.  
FSYNC  
(J2)  
PAFn Bus Sync  
HSTL  
OUTPUT  
FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus  
duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags  
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads  
quadrant1ontoPAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising  
edgewillagainloadquadrant1queuestatusflags.DuringtheWCLKcyclethatquadrant1ofaselected  
deviceisplacedontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,  
theFSYNCoutputwillbeLOW.  
FXI  
(T1)  
PAFnBus  
ExpansionIn  
HSTL  
INPUT  
TheFXIinputisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolledPAFn bus  
operationhasbeenselected.FXIofdevice‘N’connectsdirectlytoFXOofdevice‘N-1’.TheFXIreceives  
atokenfromthepreviousdeviceinachain.InsingledevicemodetheFXIinputmustbetiedLOWifthe  
PAFnbus is operatedindirectmode.IfthePAFnbus is operatedinpolledmodetheFXIinputmustbe  
connectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdeviceshouldbe  
tiedLOW,whendirectmodeisselected.  
FXO  
(J3)  
PAFnBus  
ExpansionOut  
HSTL  
OUTPUT  
FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled  
PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This  
pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAFnbuswithrespecttoWCLK.  
This pulse (token)is thenpassedontothe nextdevice inthe chain‘N+1’andonthe nextWCLKrising  
edgethefirstquadrantofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthroughthechain  
andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice  
inthechainprovides synchronizationtotheuserofthis loopingevent.  
ID[2:0]  
Device ID Pins 1.8V LVTTL TheID[2:0]pinsareusedtouniquelyaddressindividualdeviceswhenmultipleMulti-Queuedevicesare  
(ID2-A12  
ID1-B12  
ID0-A13)  
INPUT  
connectedinexpansionmode.AddressingdevicesinexpansionmoderequiresmatchingWRADD/  
RDADDaddressbitswiththeaddressthat isassignedtoeachdevicebytheID[2:0]pins. Duringwrite/  
read operations the WRADD/RDADD address are compared to the device ID [2:0] value. Note:  
expansionmodesupportsamaximum256queues,regardlessofthenumberofdevicesusedinexpansion  
mode.Thefirstdeviceinachainofmulti-queue’s(connectedinexpansionmode),maybesetupas‘000’,  
the secondas ‘001". Insingle device mode the ID[2:0]pins shouldbe setupas ‘0xx’andthe MSb(bit  
7) of the WRADD and RDADD address busses should be zero. The ID[2:0] inputs setup a respective  
deviceIDduringMasterReset.TheseIDpinsmustnottoggleduringanydeviceoperation.Note,thedevice  
selectedas the ‘Master’does nothave tohave the IDof‘000’.  
MAST  
(U1)  
MasterDevice 1.8V LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),is  
INPUT  
theMasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemasterifitisLOWthenitisaSlave.The  
masterdeviceisthefirsttotakecontrolofalloutputsafteraMasterReset,allslavedevicesgotoHigh-  
Impedance,preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,this  
pinmustbesetHIGH.  
MRS  
(T3)  
MasterReset  
HSTL  
INPUT  
TheMasterResetisusedtoconfigurethedevice.Toconfigurethedeviceconfigurationsignalsmustbe  
assertedthatmeetthesetuptimeandholdtimerequirementsofaMasterResetcycle.TransitioningMRS  
fromHIGHtoLOWthenLOWtoHIGHperformsacompleteMasterResetcycle.Note,additionaldevice  
programmingisrequiredaftermasterreset.  
JANUARY18,2006  
11  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol &  
Pin No.  
Name  
I/OTYPE  
Description  
OE  
(R22)  
OutputEnable  
HSTL  
INPUT  
TheOutputEnablesignalisthethree-statecontrolofthemulti-queuedataoutputbusQ[39:0],Qout.Ifa  
devicehasbeenconfiguredasa“Master”device,theQoutdataoutputswillbeinalowimpedancecondition  
iftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbeinhighimpedance.Ifadeviceis  
configureda“Slave”device,thentheQoutdataoutputswillalwaysbeinhighimpedanceuntilthatdevice  
has beenselectedontheReadPort,atwhichpointOEprovides three-stateofthatrespectivedevice.  
PAE  
(N20)  
Programmable  
Almost-Empty  
Flag  
HSTL  
OUTPUT  
ThispinprovidestheAlmost-EmptyflagstatusfortheQueuethathasbeenselectedontheoutputportfor  
readoperations,(selectedviaRCLK,RDADDandRADEN).ThispinisLOWwhentheselectedQueue  
isalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagissynchronized  
toRCLK.  
PAEn[7:0]  
(PAE7-F21  
PAE6-F22  
PAE5-G20  
PAE4-G21  
PAE3-G22  
PAE2-H20  
PAE1-H21  
PAE0-H22)  
Programmable  
FlagBus  
HSTL  
OUTPUT  
ThePAEnbusis8bitswide.DuringaMasterResetthisbusissetupforAlmostEmptyconfiguration.This  
outputbusprovidesPAEstatusof8queues(1quadrant),withinaselecteddevice.DuringQueueread/  
writeoperationstheseoutputsprovideprogrammableemptyflagstatusorpacketdataavailablestatus,  
ineitherpolledordirectmode.Themodeofflagoperationisdeterminedduringmasterresetviathestate  
oftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionof  
multi-queuedevices.DuringdirectoperationthePAEnbusisupdatedtoshowthePAEstatusofaquadrant  
ofqueues withinaselecteddevice.Selectionis madeusingRCLK,ESTRandRDADD.DuringPolled  
operationthePAEnbusisloadedwiththePAEstatusofmulti-queueflow-controlquadrantssequentially  
based on the rising edge of RCLK.  
PAF  
(F3)  
Programmable  
Almost–FullFlag OUTPUT  
HSTL  
ThispinprovidestheAlmost-FullflagstatusfortheQueuethathasbeenselectedontheinputportforwrite  
operations,(selectedviaWCLK,WRADDandWADEN).This pinis LOWwhentheselectedQueueis  
almost-full.ThisflagoutputmaybeduplicatedononeofthePAFnbuslines.ThePAEflagisasserted  
synchronoustoWCLK.  
PAFn[7:0]  
(PAF7-F2  
PAF6-F1  
PAF5-G3  
PAF4-G2  
PAF3-G1  
PAF2-H3  
PAF1-H2  
PAF0-H1)  
Programmable  
Almost-FullFlag OUTPUT  
Bus  
HSTL  
ThePAFnbusis8bitswide.AtanyonetimethisoutputbusprovidesPAFstatusof8queues(1quadrant),  
withinaselecteddevice.DuringQueueread/writeoperationstheseoutputsprovideprogrammablefull  
flagstatus,ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterreset  
viathestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduring  
expansionofmulti-queuedevices.DuringdirectoperationthePAFnbusisupdatedtoshowthePAFstatus  
ofaquadrantofqueueswithinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDand  
WADEN.DuringPolledoperationthePAFnbusisloadedwiththePAFstatusofmulti-queueflow-control  
quadrantssequentiallybasedontherisingedgeofWCLK.  
PLL ON  
(V1)  
PLL ON  
HSTL  
INPUT  
ThispinisusedtoenablethePLL.WhenPLLisactivated,datawillbeclockedoutbyPLLgeneratedclock.  
Q[39:0](Qout) DataOutputBus  
(See Pin No.  
tablefordetails)  
HSTL  
OUTPUT  
Thesearethe40dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge  
ofRCLKprovidedthatRENisLOW,OEisLOWandtheQueueisselected.Duetobus-matchingnotall  
outputsmaybeused,anyunusedoutputsshouldnotbeconnected.  
QSEL[2:0]  
QueueSelect  
1.8V LVTTL TheQSELpins providesvariousqueueprogrammingoptions.RefertoTable10,WriteQueueSwitch  
(QSEL2-BB10  
QSEL1-AA10  
QSEL0-BB9)  
INPUT  
Operationfordetails.  
RADEN  
(T22)  
ReadAddress  
Enable  
HSTL  
INPUT  
The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to  
bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided  
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN  
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,  
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthepart  
has beencompletedandSENOhas goneLOW.  
RCLK  
(J22)  
ReadClock  
HSTL  
INPUT  
WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheselectedqueueviatheoutputbus  
Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while  
RADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthePAEn  
flagquadranttobeplacedonthePAEnbusduringdirectflagoperation.Duringpolledflagoperationthe  
PAEnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE,and  
JANUARY18,2006  
12  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol &  
Pin No.  
Name  
I/OTYPE  
Description  
RCLK (Cont'd) ReadClock  
(J22)  
HSTL  
INPUT  
EFoutputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXOandEXIsignalsarebased  
onRCLK. RCLKmustbe continuous andfree-running.  
RCS  
(J21)  
Read Chip  
Select  
HSTL  
INPUT  
The RCS signalinconcertwith REN signalprovides controltoenable data ontothe outputreaddata  
bus. During a Master Reset cycle the RCS itis don’tcare signal.  
RDADD[7:0] ReadAddress  
(RDADD7-V20 Bus  
RDADD6-V21  
RDADD5-V22  
RDADD4-U20  
RDADD3-U21  
RDADD2-U22  
RDADD1-T20  
RDADD0-T21)  
HSTL  
INPUT  
Forthe128QdevicetheRDADDbusis8bits.TheRDADDbusisadualpurposeaddressbus.Thefirst  
functionofRDADDistoselectaQueuetobereadfrom.Theleastsignificant5bitsofthebus,RDADD[4:0]are  
usedtoaddress1of128possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,  
RDADD[7:5]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion  
mode.These3MSB’swilladdressadevicewiththematchingIDcode.(SeeID[2:0]descriptionformore  
detailonmatchingIDcode.ThesecondfunctionoftheRDADDbusistoselectthequadrantofqueues  
tobeloadedontothePAEnbusduringstrobedflagmode.Theleastsignificant4bits,RDADD[3:0]are  
usedtoselectthequadrantofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]  
areagainusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.  
Address bitRDADD[4]is don’tcareduringquadrantselection.  
REN  
ReadEnable  
SerialClock  
HSTL  
INPUT  
TheRENinputenablesreadoperationsfromaselectedQueuebasedonarisingedgeofRCLK.Aqueue  
tobereadfromcanbeselectedviaRCLK,RADENandtheRDADDaddressbusregardlessofthestate  
ofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecondRCLK  
cycle after queue selection regardless of REN. A read enable is not required to cycle the PAEnbus  
(inpolledmode)ortoselectthe PAEnquadrant, (indirectmode).  
(J20)  
SCLK  
(K3)  
HSTL  
INPUT  
Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput  
clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice  
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed  
theSCLKofalldevices shouldbeconnectedtothesamesource.  
SENI  
(K1)  
SerialInput  
Enable  
HSTL  
INPUT  
Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe  
part(via a risingedge ofSCLK), providedthe SENIinputofthatdevice is LOW. Ifmultiple devices are  
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial  
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain  
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI  
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.  
SENO  
(K2)  
SerialOutput  
Enable  
HSTL  
OUTPUT  
Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queue  
devicehasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,  
SENOwillgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO  
willalsogoHIGH. Whenthe SENOoutputgoes LOW, the device is readytobeginnormalread/write  
operations.Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENO  
outputshouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogramming  
ofthefirstdeviceiscomplete,SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOW  
andsoonthroughoutthechain.WhenagivendeviceinthechainisfullyprogrammedtheSENOoutput  
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.  
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.  
SI  
(L2)  
SerialIn  
HSTL  
INPUT  
Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.  
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion  
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO  
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice  
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.  
SO  
(L3)  
SerialOut  
HSTL  
OUTPUT  
Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain  
tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe  
chain. The SOofthe finaldevice ina chainshouldnotbe connected.  
TCK  
(B10)  
JTAGClock  
HSTL  
INPUT  
ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test  
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge  
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds  
tobe tiedtoGND.  
JANUARY18,2006  
13  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol &  
(Pin No.)  
Name  
I/OTYPE  
Description  
TDI  
(A11)  
JTAGTestData  
HSTL  
INPUT  
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan  
operation, Inputtestdata seriallyloadedvia the TDIonthe risingedge ofTCKtoeitherthe Instruction  
Register,IDRegisterandBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected  
TDO  
(B11)  
JTAGTestData  
Output  
HSTL  
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan  
operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction  
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein  
SHIFT-DR and SHIFT-IR controller states.  
TP  
(U3)  
IDTInternal  
TestPin  
LVTTL  
ForIDTinternaltestpurposeonly,mustbetiedtoGNDfornormal/correctoperation.  
TMS  
(A10)  
JTAGMode  
Select  
HSTL  
INPUT  
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe  
devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.  
TRST  
(A9)  
JTAGReset  
HSTL  
INPUT  
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not  
automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHfor  
fiveTCKcycles.IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.  
Ifthe JTAGfunctionis usedbutthe userdoes notwanttouseTRST, then TRST canbe tiedwithMRS  
toensureproperqueueoperation.IftheJTAGfunctionisnotusedthenthissignalneedstobetiedtoGND.  
Aninternalpull-upresistorforcesTRSTHIGHifleftunconnected.  
WADEN  
(M3)  
WriteAddress  
Enable  
HSTL  
INPUT  
TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto  
bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided  
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).WADEN  
shouldnotbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,  
thatawritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingofthepart  
has beencompletedandSENOhas goneLOW.  
WCLK  
(M2)  
WriteClock  
HSTL  
INPUT  
WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedQueueviatheinputbus,  
Din.TheQueuetobewrittentoisselectedviatheWRADDaddressbusandarisingedgeofWCLKwhile  
WADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalsoselecttheflag  
quadranttobeplacedonthePAFnbusduringdirectflagoperation.DuringpolledflagoperationthePAFn  
busiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,PAFand  
FFoutputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignalsarebased  
onWCLK.TheWCLKmustbecontinuous andfree-running  
WCS  
(L1)  
WriteChip  
Select  
HSTL  
INPUT  
TheWCSsignalinconcertwithWENsignalprovidescontroltoenabledatafromtheinputwritedatabus  
tobe writtenintothe device. Duringa MasterResetcycle theWCS itis don’tcare signal.  
WEN  
(M1)  
WriteEnable  
HSTL  
INPUT  
TheWENinputenableswriteoperationstoaselectedQueuebasedonarisingedgeofWCLK.A queue  
tobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddressbusregardlessofthestate  
ofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLKcycleafter  
queueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFnbus(inpolled  
mode)ortoselectthePAFnquadrant, (indirectmode).  
WRADD[7:0] WriteAddress  
(WRADD7-R2 Bus  
WRADD6-R1  
WRADD5-P3  
WRADD4-P2  
WRADD3-P1  
WRADD2-N3  
WRADD1-N2  
WRADD0-N1)  
HSTL  
INPUT  
TheWRADDbusis8bits.TheWRADDbusisadualpurposeaddressbus.ThefirstfunctionofWRADD  
istoselectaQueuetobewrittento.Theleastsignificant5bitsofthebus,WRADD[4:0]areusedtoaddress  
1of128possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,WRADD[7:5]areused  
toselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.These3MSB’s  
willaddressadevicewiththematchingIDcode.(SeeID[2:0]descriptionformoredetailonmatchingID  
code.ThesecondfunctionoftheWRADDbusistoselectthequadrantofqueuestobeloadedontothe  
PAFnbusduringstrobedflagmode.Theleastsignificant4bits,WRADD[3:0]areusedtoselectthequadrant  
ofadevicetobeplacedonthePAFnbus.Themostsignificant3bits,WRADD[7:5]areagainusedtoselect  
1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitWRADD[4]  
isdon’tcareduringquadrantselection.  
ZQ  
(N22)  
ZQ  
HSTL  
INPUT  
OutputImpedanceMatchingInput.Thisinputisusedtotunethedeviceoutputstothesystemdatabus  
impedance.Q[39:0]outputimpedanceissetto0.2xRQ,whereRQisaresistorconnectedbetweenZQ  
andground. This pincannotbeconnecteddirectlytoGNDorleftunconnected.  
JANUARY18,2006  
14  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol &  
Pin No.  
Name  
I/OTYPE  
Description  
VDD  
+1.8VSupply  
Power  
These are VCC power supply pins and must all be connected to a +1.8V supply  
(See below)  
VDDQ  
(See below)  
OutputVoltage  
Reference  
Power  
INPUT  
These pins must be tied to the desired output supply voltage (=1.5V for HSTL and =1.8V for eHSTL).  
Vref  
(J1, M21)  
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable  
Voltage”RecommendedDCOperatingConditions”.Theinputprovides thereferencelevelforHSTL/  
eHSTLinputs.  
GND  
(See below)  
Ground  
Ground  
Power  
Ground  
These are Ground pins and must all be connected to the Ground of the power supply.  
AVDD  
(K21, M22)  
PLL Power  
PLL Ground  
1.8V PLL Power Supply.  
AVSS  
Groundforthe PLLdevice. Shouldbe connectedtogroundofthe system.  
(L(21,22), K22)  
NOTE:  
1. Inputs should not change after Master Reset.  
PIN NUMBER TABLE  
Symbol  
Name  
I/OTYPE  
Pin Number  
D[39:0]  
DataInputBus HSTL-LVTTL D39-AA9,D38-BB8,D37-AA8,D36-BB7,D35-AA7,D34-BB6,D33-AA6,D32-BB5,D31-AA5,D30-BB4,  
INPUT  
D29-AA4, D28-BB3, D27-AA3, D(26,25)-Y(3,4), D(24-22)-W(3-1), D(21,20)-V(3,2), D(19,18)-E(2,3),  
D(17-15)-D(1-3), D(14,13)-C(4,3), D12-B3, D11-A3, D10-B4, D9-A4, D8-B5, D7-A5, D6-B6, D5-A6,  
D4-B7, D3-A7, D2-B8, D1-A8, D0-B9  
Q[39:0]  
DataOutputBus HSTL-LVTTL Q39-AA13,Q38-BB14,Q37-AA14,Q36-BB15,Q35-AA15,Q34-AA15,Q33-AA16,Q32-BB17,Q31-AA17,  
Q30-BB18, Q29-AA18, Q28-BB19, Q27-AA19, Q26-BB20, Q25-AA20, Q(24,23)-Y(20,19),  
Q(22-20)-W(20-22), Q(19-17)-D(22-20), Q(16,15)-C(19,20), Q14-B20, Q13-A20, Q12-B19, Q11-A19,  
Q10-B18, Q9-A18, Q8-B17, Q7-A17, Q6-B16, Q5-A16, Q4-B15, Q3-A15, Q2-B14, Q1-A14, Q0-B13  
VDD  
+1.8VSupply  
Power  
D(4-10,13-19), E(4-9,14-17,19), G18, H(4,5,18,19), J(4,19), P(4,19), R(3-5,18,19), V(4-8,15-19),  
W(4-10,13-19)  
VDDQ  
GND  
O/PRailVoltage  
GroundPin  
Power  
C(5-10,13-18) E18, F(4,5,18,19), G(4,5,19), T(4,5,18,19), U(4,5,18,19), Y(5-10,14-18)  
Ground  
A(1,2,21,22), B(1,2,21,22), C(1,2,11,12,21,22), D(11,12), E(10-13), J(5,9-14,18), K(4,5,9-14,18-20),  
L(4,5,9-14,18-20), M(4,5,9-14,18-20), N(4,5,9-14,18,19), P(5,9-14,18), V(9-14), W(11,12),  
Y(1,2,11-13,21,22), AA(1,2,21,22), BB(1,2,21,22)  
JANUARY18,2006  
15  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ABSOLUTEMAXIMUMRATINGS  
CAPACITANCE(TA = +25°C, f = 1.0MHz)  
Symbol  
Rating  
Commercial  
Unit  
Symbol  
Parameter(1)  
Conditions  
Max.  
Unit  
VTERM  
TerminalVoltage  
–0.5to+2.9(2)  
V
(2,3)  
CIN  
Input  
VIN = 0V  
10(3)  
pF  
with respect to GND  
Capacitance  
TSTG  
IOUT  
StorageTemperature  
DCOutputCurrent  
–55 to +125  
–50 to +50  
°C  
mA  
(1,2)  
COUT  
Output  
VOUT = 0V  
15  
pF  
Capacitance  
NOTES:  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
1. With output deselected, (OE ≥ VIH).  
2. Characterized values, not currently tested.  
3. CIN for Vref is 20pF.  
2. Compliant with JEDEC JESD8-5. VDD terminal only.  
RECOMMENDEDDCOPERATINGCONDITIONS  
Symbol  
VDD  
Parameter  
Min.  
Typ.  
Max.  
Unit  
SupplyVoltage  
1.7  
1.8  
1.9  
V
VDDQ  
OutputRailVoltageforI/Os eHSTL  
HSTL  
1.7  
1.4  
1.8  
1.5  
1.9  
1.6  
V
V
GND  
SupplyVoltage  
0
0
0
V
(2)  
VIH  
InputHighVoltage  
eHSTL  
HSTL  
VREF+0.2  
VREF+0.2  
—
—
—
—
V
V
VIL  
InputLowVoltage  
eHSTL  
HSTL  
—
—
—
—
VREF-0.2  
VREF-0.2  
V
V
VREF(1)  
(HSTL only)  
VoltageReferenceInput  
eHSTL  
HSTL  
0.8  
0.68  
0.9  
0.75  
1.0  
0.9  
V
V
TA  
TA  
OperatingTemperatureCommercial  
OperatingTemperatureIndustrial  
0
—
—
70  
85  
°C  
°C  
-40  
NOTES:  
1. VREF is only required for HSTL or eHSTL inputs.  
2. VIH AC Component = VREF + 0.4V  
JANUARY18,2006  
16  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
DCELECTRICALCHARACTERISTICS  
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
ILI  
InputLeakageCurrent  
OutputLeakageCurrent  
–10  
10  
µA  
ILO  
–10  
10  
VDDQ/2+0.12  
VDDQ/2+0.12  
VDDQ  
µA  
V
VOH1(7)  
VOL1(8)  
VOH2(9)  
VOL2(10)  
Output High Voltage (test conditions: RQ = 205Ω IOH = -8mA)  
Output Low Voltage (test conditions: RQ = 205Ω IOL = 8mA)  
OutputHighVoltage(testconditions:IOH =-0.1mA)  
OutputLowVoltage(testconditions:IOL =0.1mA)  
VDDQ/2-0.12  
VDDQ/2-0.12  
VDDQ -0.12  
VSS  
V
V
0.2  
V
IDD1(1,2)  
Active VDD Current (VDD = 1.8V)  
I/O = HSTL  
I/O = eHSTL  
—
—
200  
200  
mA  
mA  
IDD2(1, 5)  
Standby VDD Current (VDD = 1.8V)  
I/O = HSTL  
I/O = eHSTL  
—
—
120  
120  
mA  
mA  
(1,2)  
IDDQ  
ActiveVDDQ Current  
(VDDQ = 1.5V HSTL)  
(VDDQ = 1.8V eHSTL)  
I/O = HSTL  
I/O = eHSTL  
—
—
20  
20  
mA  
mA  
NOTES:  
1. Both WCLK and RCLK toggling at 20MHz.  
2. Data inputs toggling at 10MHz.  
3. Total Power consumed: PT = [(VDD x IDD) + (VDDQ x IDDQ)].  
4. Outputs are not 2.5V or 3.3V tolerant.  
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.  
The following inputs should be pulled to VDD: WEN, REN, SENI, MRS, TDI, TMS and TRST.  
All other inputs are don't care and should be at a known state.  
6. The ZQ pin is used to control the device outputs (Q[39:0], EREN, ERCLK, and ERCLK).  
7. Outputs are impedance-controlled. IOH= -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω< RQ < 350Ω. This parameter is tested at RQ = 250Ω  
which gives a nominal 50Ω output impedance.  
8. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω< RQ < 350Ω This parameter is tested at RQ = 250Ω  
which gives a nominal 50Ω output impedance.  
9. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point.  
10. This measurement is taken to ensure that the output has the capability of pulling to VSS, and is not intended to be used as an impedance measurement point.  
JANUARY18,2006  
17  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
HSTL  
AC TEST LOADS  
1.5V AC TEST CONDITIONS  
InputPulseLevels  
0.25to1.25V  
0.4ns  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
0.75  
VDDQ/2  
NOTE:  
1. VDDQ = 1.5V ± 0.1V.  
EXTENDEDHSTL  
Figure 2a. AC Test Load  
1.8V AC TEST CONDITIONS  
InputPulseLevels  
0.4 to 1.4V  
0.4ns  
6
5
4
3
2
1
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
0.9  
VDDQ/2  
NOTE:  
1. VDDQ = 1.8V ± 0.1V.  
20 30 50 80 100  
Capacitance (pF)  
200  
6724 drw04a  
Figure 2b. Lumped Capacitive Load, Typical Derating  
OUTPUT ENABLE & DISABLE TIMING  
Output  
Enable  
Output  
Disable  
VIH  
OE  
VIL  
tOE &  
tOLZ  
tOHZ  
Output  
Normally  
LOW  
V
DDQ/2  
V
CC/2  
100mV  
100mV  
100mV  
V
OL  
V
OH  
Output  
Normally  
HIGH  
100mV  
VCC/2  
VDDQ/2  
6724 drw05  
NOTE:  
1. REN is HIGH.  
JANUARY18,2006  
18  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ACELECTRICALCHARACTERISTICS  
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)  
Commercial  
Com'l and Ind'l  
IDT72P51767L6  
IDT72P51777L6  
IDT72P51767L7-5  
IDT72P51777L7-5  
Symbol  
fC  
Parameter  
Clock Cycle Frequency  
DataAccessTime  
Min.  
—
Max.  
166  
1.0  
3.6  
—
—
—
—
—
—
—
—
—
—
3.6  
3.6  
10  
Min.  
—
-1.2  
0.8  
7.5  
3.0  
3.0  
0.7  
0.7  
2.2  
0.7  
30  
Max.  
133  
1.2  
3.8  
—
—
—
—
—
—
—
—
—
—
3.8  
3.8  
10  
Unit  
MHz  
ns  
tA (PLL ON)  
-1.0  
0.6  
6.0  
2.8  
2.8  
0.48  
0.48  
2.0  
0.5  
30  
tA (PLL OFF) DataAccessTime  
ns  
tCLK  
tCLKH  
tCLKL  
tDS  
Clock Cycle Time  
Clock High Time  
Clock Low Time  
DataSetupTime  
DataHoldTime  
ns  
ns  
ns  
ns  
tDH  
ns  
tENS  
EnableSetupTime  
EnableHoldTime  
ns  
tENH  
tRS  
ns  
(3)  
ResetPulseWidth  
ns  
tRSS  
ResetSetupTime  
15  
15  
ns  
tRSR  
tOHZ  
tOE  
ResetRecoveryTime  
OutputEnabletoOutputinHighZ  
OutputEnable toOE  
Clock Cycle (SCLK)  
Serial Clock Cycle  
Serial Clock High  
10  
10  
ns  
0.6  
0.6  
—
0.8  
0.8  
—
100  
45  
ns  
ns  
fS  
MHz  
ns  
tSCLK  
tSCKH  
tSCKL  
tSDS  
100  
45  
—
—
—
—
—
—
—
20  
—
—
—
—
—
—
—
20  
ns  
Serial Clock Low  
45  
45  
ns  
SerialDatainSetup  
Serial Data in Hold  
20  
20  
ns  
tSDH  
tSENS  
tSENH  
tSDO  
tSENO  
tSDOP  
tSENOP  
tPCWQ  
tPCRQ  
tAS  
0.8  
20  
0.8  
20  
ns  
SerialEnableSetup  
SerialEnable Hold  
ns  
0.8  
—
0.8  
—
—
0.8  
0.8  
—
—
2.2  
0.7  
—
—
2.2  
0.7  
2.2  
0.7  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
ns  
SCLK to Serial Data Out  
SCLK to Enable Out  
SerialData OutDelay  
SerialEnable Delay  
ProgrammingtoWriteQueueSelection  
ProgrammingtoReadQueueSelection  
AddressSetup  
ns  
—
20  
20  
ns  
0.8  
0.8  
—
3.6  
3.6  
7
3.6  
3.6  
7
ns  
ns  
cycles  
cycles  
ns  
—
7
7
2.0  
0.5  
-—  
-—  
2.0  
0.5  
2.0  
0.5  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
—
—
3.6  
3.6  
—
—
—
—
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
—
—
3.8  
3.8  
—
—
—
—
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
tAH  
Address Hold  
ns  
tWFF  
tREF  
tSTS  
Write Clock to Full Flag (FF)  
Read Clock to Empty Flag (EF)  
StrobeSetup  
ns  
ns  
ns  
tSTH  
tQS  
StrobeHold  
ns  
QueueSetup  
ns  
tQH  
QueueHold  
ns  
tWAF  
tRAE  
tPAF  
tPAE  
tPAELZ  
tPAEHZ  
tPAFLZ  
WCLK to PAF flag  
RCLK to PAE flag  
WCLK to Sync PAF bus  
RCLK to Sync PAE bus  
RCLK to Low-Z  
ns  
ns  
ns  
ns  
ns  
RCLK to High-Z  
ns  
WCLK to PAF Bus Low-Z  
ns  
NOTES:  
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order.  
2. Values guaranteed by design, not currently tested.  
JANUARY18,2006  
19  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ACELECTRICALCHARACTERISTICS(CONTINUED)  
(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)  
Commercial  
Com'l and Ind'l  
IDT72P51767L6  
IDT72P51777L6  
IDT72P51767L7-5  
IDT72P51777L7-5  
Symbol  
tPAFHZ  
tFFHZ  
tFFLZ  
Parameter  
WCLK to PAF Bus High-Z  
WCLK to FF High-Z  
WCLK to FF Low-Z  
RCLK to EF High-Z  
RCLK to EF Low-Z  
WCLK to PAF Bus Sync  
WCLK to PAF Bus Exp  
RCLK to PAF Bus Sync  
RCLK to PAF Bus Exp  
Min.  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
—
Max.  
Min.  
0.8  
Max.  
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
3.8  
3.2  
5
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
3.6  
2.5  
4
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
—
tEFHZ  
tEFLZ  
tFSYNC  
tFXO  
tESYNC  
tEXO  
tERCLK(DDR) RCLK to ERCLK (DDR)  
tERCLK(SDR) RCLK to ERCLK (SDR)  
—
—
tSKEW1  
tSKEW2  
tSKEW3  
tXIS  
Skew time for EF and FF  
Skew time for PAF and PAE  
Skew time for PAF/PAE[0:7]  
ExpansionInputSetup  
ExpansionInputHold  
PLLLockTime  
6.0  
6.0  
6.0  
2.0  
0.5  
—
—
—
—
—
—
15  
7.0  
7.0  
7.0  
2.2  
0.7  
—
—
—
—
—
—
15  
tXIH  
tLOCK  
NOTES:  
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order.  
2. Values guaranteed by design, not currently tested.  
JANUARY18,2006  
20  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
XGMII REFERENCE SPECIFICATION  
Whenimplementedas achip-to-chipinterface, theXGMIIuses HighSpeed  
TheXGMIIuses1.5VHighSpeedTransceiverLogic(HSTL)signallevels. TransceiverLogic(HSTL),specifiedfora1.5voltoutputbuffersupplyvoltage.  
TheelectricalcharacteristicsoftheXGMIIarespecifiedsuchthattheXGMII XGMIIchip-to-chipsignalsshallcomplywithEIA/JEDECStandardEIA/JESD8-  
can be applied within a variety of 10 Gb/s equipment types. The electrical 6usingClassI,outputbuffers.Outputimpedanceshallbegreaterthan38Ωto  
specificationsareselectedforanintegratedcircuittointegratedcircuitapplication. assureacceptableovershootandundershootperformanceinanun-terminated  
TheelectricalcharacteristicsspecifiedinthisclauseapplytoallXGMIIsignals. interconnection.  
TABLE 2 — DC AND AC SPECIFICATIONS (INFORMATIVE)  
Symbol  
VDDQ  
Parameter  
OutputVoltageSupply  
InputReferenceVoltage  
DC Input Logic High  
DC Input Logic Low  
ACInputLogicHigh  
AC Input Logic Low  
Minimum  
1.4  
Nominal  
Maximum  
1.6  
Units  
V
1.5  
VREF  
0.68  
0.75  
0.90  
V
VIH_DC  
VIL_DC  
VIH_AC  
VIL_AC  
VREF+0.10  
-0.30  
-
-
-
-
VDDQ+0.3  
VREF-0.1  
-
V
V
VREF+0.20  
-
V
VREF-0.20  
V
optional  
VTT = Vddq/2  
r
50 ohms  
Figure 3. HSTL Termination for XGMII  
TABLE 3 — IDT TO XGMII INTERFACE MAPPING SCHEMA  
Signal Type  
IDT Interface Signal  
Nomenclature  
XGMII Signal  
Nomenclature  
Input Port  
-InputPortData  
D[31:0]  
D[32:39]  
WEN  
TXD [31:0]  
Userdefinable  
N/A  
TXC[3:0]  
N/A  
-InputPortEnable  
-InputPortControl  
-InputPortStatus  
-InputPortClock  
N/A  
FF, PAF  
WCLK  
TX_CLK  
Output Port  
-OutputPortData  
Q[31:0]  
RXD [31:0]  
Q[32:39]  
Userdefinable  
-OutputPortEnable  
-OutputPortControl  
-OutputPortStatus  
-OutputPortClock  
REN  
N/A  
N/A  
RXC [3:0}  
N/A  
EF, PAE  
RCLK  
RX_CLK  
JANUARY18,2006  
21  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
DFM–Programmingmode,serialordefault  
FUNCTIONALDESCRIPTION  
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither  
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.  
See Figure 37, Master Reset for relevant timing.  
MASTERRESET  
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW  
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol  
registersareinitializedandrequireprogrammingeitherseriallybytheuservia  
theserialport,orviaparallelprogrammingorbyusingthedefaultsettings.Refer  
to Figure 6, Device Programming Hierarchy for the programming hierarchy  
structure.Duringamasterresetthestateofthefollowinginputsdeterminethe  
functionalityofthepart,thesepinsshouldbeheldHIGHorLOW.  
FM – Flag bus Mode  
PROGRAMMINGMODECAPTURED  
OntherisingofMRStheprogrammingmodesignals(QSEL[2:0],DFM)are  
captured.Oncetheprogrammingmodesignalsarecaptured(latched),refer  
to Table 5, Setting the Queue Programming Mode during Master Reset for  
details.Itwillthenrequireanumberofclockcyclesforthedevicetocomplete  
theconfiguration.ConfigurationcompletionisindicatedwhentheSENOsignal  
transitionsfromhightolow.Theconfigurationcompletionindicationisconsistent  
withthe previous MQdevice.  
BM[3:0]–Bus Matchingoptions  
MAST – Master Device  
ID0, 1, 2 – Device ID  
QSEL[2:0]QueueSelectMode  
MRS  
QSEL[2:0]  
DFM  
See Table for definition of value  
DFM = LOW for Serial Programming mode  
6724 drw06  
Figure 4. Reference Signals  
TABLE 4 — DEVICE PROGRAMMING MODE COMPARISON  
Programming Options  
Serial Programming Mode  
Default/Parallel Programming Mode  
QueueSelection  
QueueDepth  
Any number from 1 to 128  
Any number from 1 to 128  
Eachqueue depthcanbe individualized  
DefaultValue(totalavailablememorydivided  
by number of queues)  
PAE/PAF  
Programmable to any value  
Defaultvalue  
Bus-Matching  
Anyavailable optioncanbe selectedusing  
BM[3:0]pins  
Anyavailable optioncanbe selectedusing  
BM[3:0]pins  
I/Ovoltage  
Anyavailable optioncanbe selected  
Anyavailable optioncanbe selected  
JANUARY18,2006  
22  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE5—SETTINGTHEQUEUEPROGRAMMINGMODEDURINGMASTERRESET  
Default  
Mode  
/MRS  
↑
(DFM)  
QSEL 2  
QSEL 1  
QSEL 0  
Queue Programming Method  
Serial programming mode  
RESERVED  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
↑
↑
RESERVED  
↑
RESERVED  
↑
RESERVED  
↑
RESERVED  
↑
RESERVED  
↑
RESERVED  
↑
Selects 128 Queues  
Selects 64 Queues  
Selects 32 Queues  
Selects 16 Queues  
Selects 8 Queues  
Selects 4 Queues  
↑
↑
↑
↑
↑
Parallel programming enables the user  
to program the number of queues using  
the Write Address bus  
Parallel programming enables the user  
to program the number of queues using  
the Read Address bus  
↑
1
1
1
1
1
1
0
1
↑
6724 drw07  
JANUARY18,2006  
23  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SERIAL PROGRAMMING  
utilizethe‘C’programtogeneratetheserialbitstream,theprogramprompting  
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid- theuserforthenumberofdevicestobeprogrammed.TheSENOandSO(serial  
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber out)ofthefirstdeviceshouldbeconnectedtotheSENIandSIinputsofthesecond  
of queues, depth of each queue and position of the PAF/PAE flags within devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe  
respective queues. All user programming is done via the serial port after a SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould  
master reset has taken place. Internally the multi-queue device has setup beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould  
registerswhichmustbeseriallyloaded,theseregisterscontainvaluesforevery be monitored by the user. When SENO of the final device goes LOW, this  
queuewithinthedevice,suchas thedepthandPAE/PAFoffsetvalues.The indicatesthatserialprogrammingofalldeviceshasbeensuccessfullycompleted.  
IDT72P51767/72P51777 devices are capable of up to 128 queues and Upon detection of completion of programming, the user should cease all  
thereforecontain128setsofregistersforthesetupofeachqueue.  
During a Master Reset if the DFM (Default Mode) input is LOW, then the  
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.  
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled  
devicewillrequireserialprogrammingbytheuser.Itisrecommendedthatthe bytheuser,this is thefirstdevicetohaveits internalregisters seriallyloaded  
userutilize a ‘C’programprovidedbyIDT, this programwillpromptthe user bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake  
for all information regarding the multi-queue setup. The program will then itsSENOoutputLOWandbypasstheserialdataloadedontheSIinputtoitsSO  
generateaserialbitstreamwhichshouldbeseriallyloadedintothedevicevia output.Theserialinputoftheseconddeviceinthechainisnowloadedwiththe  
theserialport.FortheIDT72P51767/72P51777devicestheserialprogram- datafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENIinput  
mingrequiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycles LOW.Thisprocesscontinuesthroughthechainuntilalldevicesareprogrammed  
with SENI enabled), calculated by: 27+(Qx104) where Q is the number of and the SENO of the final device (or master device, ID = '000') goes LOW.  
queuestheuserwishestosetupwithinthedevice.  
Once all serial programming has been successfully completed, normal  
Once the master reset is complete and MRS is HIGH, the device can be operations,(queueselections onthereadandwriteports)maybegin.When  
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial connectedinexpansionconfiguration,theIDT72P51767/72P51777devices  
port on a rising edge of SCLK (serial clock), provided that SENI (serial in require a total number of serially loaded bits per device to complete serial  
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully programming,(SCLKcycleswithSENIenabled),calculatedby:n[27+(Qx104)]  
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going where Qis the numberofqueues the userwishes tosetupwithinthe device,  
active,LOW.Upondetectionofcompletionofprogramming,theusershould where n is the number of devices in the chain.  
cease all programming and take SENI inactive, HIGH. Note, SENO follows  
SeeFigure40,SerialPortConnectionandFigure41,SerialProgramming  
SENIonceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOW forconnectionandtiminginformation.  
afterprogrammingprovidedSENI is LOW,onceSENI is takenHIGHagain,  
TheIDT72P51777/72P51767devicecanbeprogrammedusingtheserial  
SENO will also go HIGH. The operation of the SO output is similar, when inputsignals(SENI,SI,SCLK).Serialprogrammingisaccomplishedbyshifting  
programmingofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput. in26bitwords.Itrequires1HeaderWordtostarttheprogrammingsequence  
If devices are being used in expansion configuration the serial ports of andanadditional4ProgrammingWordsforeachqueuethatisconfiguredwithin  
devicesshouldbecascaded.Theusercanloadalldevicesviatheserialinput thedevice.  
portcontrolpins,SI&SENI,ofthefirstdeviceinthechain.Again,theusermay  
EACH OF THE 26 BIT WORDS ARE DESCRIBED BELOW:  
HeaderWord:Thisis1st26-bitwordandhasthefollowingbitassignments.  
• Bits[25:7]istheStartofHeaderidentifier.  
• Bits [6:0]are the numberofqueues tobe programmed.  
TheStartofHeaderidentifierMUSTbeallones(1’s).Theall1’spatternintheHeaderwordsignifiesthestartoftheprogrammingcycle.TheHeader  
Word is only needed once for each device. For example, for 128 queues bits [6:0] = “1111111” for 32 queues bits [6:0] = “0011111”.  
Bits  
25  
24 23  
22  
21 20  
19  
18  
17 16 15 14  
13 12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Value  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Q64 Q32 Q16 Q8 Q4 Q2 Q1  
FF:This is the 2nd 26-bitwordandrepresents the FullFlagprogrammedvalue. The FullFlagvalue is equaltothe Queue depth-2. Eachqueue requires an  
individual FF value.  
Bits  
25 24 23 22 21 20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Binary 0  
0
0
0
0
0
524288 262144 131072 65536 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16  
8
4
2
1
Value  
JANUARY18,2006  
24  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PAE:Thisisthe3rd 26-bitwordandrepresentstheProgrammableAlmostEmpty(PAE)value. EachqueuerequiresanindividualPAEvalue.ThePAEvalue  
that is programmed into the device is the number of words. For example, for a PAE value = 52 words, bits [19:0] = “00000000000000110100”.  
Bits  
25 24 23 22 21 20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Binary 0  
0
0
0
0
0
524288 262144 131072 65536 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16  
8
4
2
1
Value  
PAF:This is the 4th 26-bitwordandrepresents the Programmable AlmostFull(PAF)value. Eachqueue requires anindividualPAF value.ThePAF value  
thatis programmedintothe device is the “Queue DepthValue”–“The PAF Offsetvalue”. Forexample, witha Queue Depthof16K(16384)anda desired  
PAF value = 39 words, bits [19:0] = “00000011111111011001”.  
Bits  
25 24 23 22 21 20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Binary 0  
0
0
0
0
0
524288 262144 131072 65536 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16  
8
4
2
1
Value  
Queue End/Start Address  
This is the 5th 26-bit word and represents both the start and end address of each queue.  
End Address: The queue end address is bits [25:13] of the 26-bit. An end addresses is specified as; Queue Depth – 1k . Ending address are specified in  
increments of1Kwords. Forexample,foraQueueDepthof16K,thefirstqueuewouldhaveastartingaddress of0,bits [12:0]=“0000000000000”andan  
end address of 15K, bits [25:13] = “0000000001111”,  
StartAddress:Thequeuestartingaddressisbits[12:0]ofthe26-bitword.Startaddressesarespecifiedinincrementsofwords.Thefirstqueueshouldalways  
startataddress0.Thestartingaddressofthenextqueueshouldbeprogrammedatanaddressthatiswordsgreatertheendingaddressofthepreviousqueue.  
Bits  
25  
24  
23  
22  
21  
20  
19 18 17 16 15 14 13 12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Value 4096 2048 1024 512 256 128  
64 32 16  
8
4
2
1
4096 2048 1024 512 256 128  
64  
32  
16  
8
4
2
1
EndAddress  
StartAddress  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
The following is an explanation of the binary file created by the C program for the 10G MQ devices (IDT72P51767/72P51777).  
The DesiredDevice Configurationis;  
• Number of Queues = 32  
• Each Queue Depth = 16k  
• Each Queue PAE Value = 52  
• Each Queue PAF Value = 39  
This is the Start of Header Identifier.  
The Start of Header Identifier signifies  
the start of the programming cycle.  
This is number of queues (32) that will  
11111111111111111110011111  
be configured in the device.  
00000000000011111111111110  
Queue Programming  
00000000000000000000110100  
00000000000011111111011001  
00000000111110000000000000  
Queue 0  
Full Flag Programmed Value  
Programmable Almost Empty Value  
Programmable Almost Full Value  
Queue End/Start Address  
Queue End  
Address  
Queue Start  
Address  
00000000000011111111111110  
00000000000000000000110100  
00000000000011111111011001  
00000001111110000000100000  
Queue 1  
00000000000011111111111110  
00000000000000000000110100  
00000000000011111111011001  
00000010111110000001000000  
Queue 2  
Queue 3  
00000000000011111111111110  
00000000000000000000110100  
00000000000011111111011001  
00000011111110000001100000  
00000000000011111111111110  
00000000000000000000110100  
00000000000011111111011001  
00011111111110001111100000  
Queue 31  
This indicates the end of the  
programming sequence for  
the device.  
0
Stop Bit  
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(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
DEFAULTPROGRAMMING  
device to be set through either the Write Address (WRADD) bus or Read  
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi- Address(RDADD)busaftertheMasterResetcycle.WithinParallelProgram-  
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming ming mode the Multi-Queue (MQ) device programmable parameters are;  
is not permitted). Default programming provides the user with a simpler, numberofqueues,queuedepth,PAE/PAFflagoffsetvalue,busmatchingand  
howeverlimitedmeanstosetupthemulti-queueflow-controldevice,ratherthan the I/O voltage level. As previously indicated, the number of queues are  
usingtheserialprogrammingmethod.Thedefaultmodewillconfigureamulti- configuredusingthewriteorreadaddressbus,howeverbusmatchingisset  
queuedevicewiththemaximumnumberofqueues setup,andtheavailable duringtheMasterResetcycle.Thevaluethatis setduringtheMasterReset  
memoryallocatedequallybetweenthequeues.Thevalues ofthePAE/PAF cycle is determined by the Bus Matching (BM) bits. For the IDT72P51767/  
offsetsisdeterminedbythestateofthe(default)pinduringamasterreset.  
FortheIDT72P51767/72P51777devices thedefaultmodewillsetup128 offsetsatmasterresetisdeterminedbythestateoftheinput.  
queues,eachqueuebeing256x40,512x40,and1024x40 deeprespectively. When configuring the IDT72P51767/72P51777 devices in Parallel Pro-  
72P51777devicesinParallelProgrammingModethevalueofthePAE/PAF  
WhenconfiguringtheIDT72P51767/72P51777devicesindefaultmodethe grammingModetheusersimplyhastoapplyWCLKcyclesafteramasterreset,  
usersimplyhastoapplyWCLKcyclesafteramasterreset,untilSENO goes untilSENOgoesLOW,thissignalsthatParallelProgrammingiscomplete.These  
LOW,thissignalsthatdefaultprogrammingiscomplete.Theseclockcyclesare clockcyclesarerequiredforthedevicetoloaditsinternalsetupregisters.When  
requiredforthedevicetoloaditsinternalsetupregisters.Whenasinglemulti- asinglemulti-queuedeviceisused,thecompletionofdeviceprogrammingis  
queuedeviceisused,thecompletionofdeviceprogrammingissignaledbythe signaledbytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,that  
SENOoutputofadevicegoingfromHIGHtoLOW.Note,thatSENImustbeheld SENImustbeheldLOWwhenadeviceissetupforParallelProgrammingmode.  
LOWwhenadeviceissetupfordefaultprogrammingmode.  
Whenmulti-queuedevicesareconnectedinexpansionconfiguration,the ID[2:0] PINS AND WRADD/RDADD CONFIGURATIONS  
SENIofthefirstdeviceinachaincanbeheldLOW.TheSENOofadeviceshould  
The10GDDRMulti-Queuewillhavetheabilitytoexpanduptoamaximum  
connecttotheSENIofthenextdeviceinthechain.TheSENOofthefinaldevice of 256 Queues by 2 to 8 devices depending on the configuration setup. For  
isusedtoindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthe programming the ID Codes for each device the WRADD/RDADD address  
master(ID='000')SENOgoesLOWnormaloperationsmaybegin.Again,all busesimposethelimitationof256Queuesbecause,withan8-bitaddressbus,  
devices will be programmed with their maximum number of queues and the the3MSBintheWRADD/RDADDareusedtodecodetheID[2:0]pinsoneach  
memory divided equally between them. Please refer to Figure 38, Default device. Theslavedevicesmustbeconfiguredbeforethemasterdeviceaswell.  
Programming.  
For8-deviceexpansiontheleast[4:0]bitsareusedforexpansionaddressing  
meaningaconfigurationof32queuescanbeaccomplished.TheMSBs[7:5]  
willselectwhichoftheeightdevicestoaccessdependingontheirMSBID[2:0]  
PARALLELPROGRAMMING  
DuringaMasterResetcycle(i.e.the MRSsignaltransitionsfromHIGHto settings. IfID[2:0]is000,thenitservesasthemasterdevice. Otherwise,the  
LOWthenLOWtoHIGH)iftheDFM(DefaultMode)inputsignalisHIGHand devices will serve as the slave devices. Ex: For using two 128 queue MQ  
the QSEL[2:0] input signal is "110" for Write address and "111" for Read devices,ID[2:0]=0xxisforselectingthemasterdevice. Forusing8devices,  
address, the Multi-Queue Flow Control device is configured for Parallel ID[2:0]=111isforselectingthe8thslavedeviceandWRADD/RDADDbits[4:0]  
Programming.ParallelProgrammingenablesthenumberofqueueswithinthe for configuring 32 queues/device. And so on.  
TABLE6—ID[2:0]ANDWRADD[7:5]/RDADD[7:5]CONFIGURATION  
Queues Addressed  
x
128  
64  
32  
16  
8
4
2
ID[2:0]MasterDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
0xx  
00x  
000  
000  
000  
000  
000  
ID[2:0]2ndDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
1xx  
NA  
NA  
NA  
NA  
NA  
NA  
10x  
01x  
11x  
NA  
NA  
NA  
NA  
100  
010  
110  
001  
101  
011  
111  
100  
010  
110  
001  
101  
011  
111  
100  
010  
110  
001  
101  
011  
111  
100  
010  
110  
001  
101  
011  
111  
100  
010  
110  
001  
101  
011  
111  
ID[2:0]3rdDevice Configuration  
WRADD[7:5] or RDADD[7:5]  
ID[2:0]4thDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
ID[2:0]5thDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
ID[2:0]6thDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
ID[2:0]7thDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
ID[2:0]8thDeviceConfiguration  
WRADD[7:5] or RDADD[7:5]  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE 7 — PARALLEL PROGRAMMING MODE QUEUE CONFIGURATION  
EXAMPLE(1)  
WRADD/RDADD[7:0]  
128Queues/Device  
64Queues/Device  
32Queues/Device  
16Queues/Device  
8Queues/Device  
4Queues/Device  
1Queue/Device  
7
x
x
x
x
x
x
x
6
1
0
0
0
0
0
0
5
1
1
0
0
0
0
0
4
1
1
1
0
0
0
0
3
1
1
1
1
0
0
0
2
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
NOTE:  
1. Users can also program 6 different settings in Default Programming mode using QSEL[2:0] and DFM pins instead of using Parallel Programming Mode.  
This table above shows how a user might program the number of queues in the device and can program any 1-128 queues in the device by using  
the WRADD/RDADD[7:0] pins.  
The10GMulti-Queuealsohas thecapabilityofexpandedtheoreticallyto TomakethispossibletheIDpin,ID2ofallslavedevicesmustbeconnectedto  
unlimitednumberofdevices. AsFigure5shows,theWRADD[7]andRDADD[7] “1”andtheMasterdeviceIDPins,ID[2:0],shouldequal000. Itisnotrecommend  
will act as the Write Chip Select Enable and Read Chip Select Enable expandinggreaterthan10devices becausesufficientcapacitiveloadingon  
respectively, andthe usercanthendecode eachMulti-Queue device sepa- eachbusmakesitdiffculttodriveagreatermultipleofdevicesperbus. Thereal  
rately using these pins and still maintain 128 Queues per device. The WCSandRCSpinscanbetiedtoagroundplaneontheboardtosaveFPGA  
WRADD[6:0] and RDADD[6:0] can still be routed as shared buses to each pins.  
device,ascanwriteandreaddatabusesandexternalcontrolpinsandflags.  
RCLK  
WCLK  
/WEN  
/REN  
Slave2  
ID=110  
W_A[6:0]  
W_A7  
R_A[6:0]  
R_A7  
W_A7_S2  
(!/WCS2)  
R_A7_S2  
(!/RCS2)  
DIN  
QOUT  
WCLK  
/WEN  
RCLK  
RCLK  
/REN  
WCLK  
/WEN  
Q_BUS  
Slave1  
ID=101  
W_A[6:0]  
W_A7  
R_A[6:0]  
R_A7  
W_A7_S1  
(!/WCS1)  
R_A7_S1  
(!/RCS1)  
DIN  
QOUT  
/REN  
D_BUS  
RCLK  
/REN  
WCLK  
/WEN  
Master  
WADDR<6:0>  
RADDR<6:0>  
W_A[6:0] ID=000R_A[6:0]  
W_A7  
DIN  
R_A7  
W_A7_M  
(/WCS0)  
R_A7_M  
(/RCS0)  
QOUT  
Figure 5. Expansion for Unlimited Number of Multi-Queue Devices Example  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
WhenMulti-QueuedevicesareconnectedinanExpansionConfiguration, PROGRAMMINGHIERARCHY  
theSENIsignalofthefirstdeviceinachainmustbeheldLOW.TheSENOsignal  
Configuring the device is a 2 stage sequence. The first stage is to set the  
ofadeviceshouldconnecttotheSENIofthenextdeviceinthechain.TheSENO expansion device type, the desired programming mode and the device  
of the final device is used to indicate that the programming of all devices is operatingmodeduringthemasterresetcycle(i.e.ontherisingedgeofMaster  
complete. When the master device (ID=’000') SENO signal goes LOW the Reset(MRS)).ThesecondstageistosetvaluessuchasPAE/PAF,number  
internalprogrammingiscompleteandqueuewrite/readoperationmaybegin. of queues, queue depth, etc. using the programming mode (serial, parallel,  
PleaserefertoFigure41,ParallelProgrammingforsignaltimingdetails.  
default)selectedinstage1.RefertoFigure6,DeviceProgrammingHierarchy.  
Master Reset Cycle  
Device Operating Mode  
Selected  
Expansion  
Device Type  
Selected  
Device  
Programming  
Mode Selected  
BOI Mode or IDT Standard mode  
Master  
Slave  
Device  
Device  
Serial  
Programming  
Parallel Queue  
Programming  
Default  
Programming  
6724 drw08  
Figure 6. Device Programming Hierarchy  
IDT standard mode, the device operates as the IDT72P51769 (4M multi-  
queue) device as shown in Figure 49 and 50.  
Theotheroption,orBOImode,hasthedevicereissuethelastdatafroma  
queueuponreentrytothatqueue. Thisallowsforacustomertomonitoradata  
bitandstopreadingbasedontheoutput(e.g.,EndofPacketorEOP).Note:  
theEFflagisalwaysupdated“realtime”usingthereadcountinbothmodes.  
MODESOFOPERATION  
STANDARDMODEOPERATION  
The10GMulti-queuesupportstwomodesofoperation,IDTStandardMode  
and BOI Mode.  
IDT STANDARD MODE VS. BOI MODE  
Thedevicemodeisconfiguredduringthemasterresetcycle.Onlytheread  
sideisaffectedbythesetwomodes,thewritesideisidenticalinbothmodes.In  
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(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PLL ON VS PLL OFF MODES  
ThePLLhasafrequencyresponserateof85-166MHz. ThePLLreduces  
theaccesstime(ta)fortheDDR. Below85MHzorinSDRmode,thePLLmust  
be turned off. The following diagrams show the difference between the two  
modes:  
RCLK  
REN  
tERCLK  
ERCLK  
ERCLK  
EREN  
tA  
QOUT  
(PLL on)  
6724 drw09b  
NOTES:  
1. Echo clocks are center aligned.  
2. ERCLK is aligned with internal PLL generated clock.  
3. QOUT is clocked out 1 cycle after valid REN.  
4. Data Access time (Ta) is +/-1.0ns when PLL is on, with respect to rising edges of RCLK (1 Clock Latency).  
Figure 7. DDR Read Operation with PLL ON  
RCLK  
REN  
ERCLK  
EREN  
t
A
QOUT  
(PLL off)  
EF  
PAE  
6724 drw09c  
NOTES:  
1. ERCLK has uncontrollable delay when PLL is off.  
2. DOUT is clocked out 1 cycle after valid REN.  
3. Data Access time (Ta) is <3.6ns when PLL is off, with respect to rising/falling edges of RCLK.  
Figure 8. DDR Read Operation with PLL OFF  
30  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
RCLK  
REN  
tERCLK  
ERCLK  
ERCLK  
EREN  
tA  
QOUT  
(PLL on)  
EF  
PAE  
6724 drw09d  
NOTES:  
1. In single-ended clocking scheme, ERCLK is 50% duty cycle.  
2. QOUT is clocked out 1 cycle after valid REN.  
3. Data Access time (Ta) is +/-1.0ns when PLL is on, with respect to rising edges of RCLK.  
Figure 9. SDR Read Operation with PLL ON  
RCLK  
REN  
ERCLK  
EREN  
tA  
QOUT  
(PLL off)  
EF  
PAE  
6724 drw09e  
NOTES:  
1. ERCLK has uncontrollable delay when PLL is off, Ta <3.6ns when PLL is off.  
2. DOUT is clocked out 1 cycle after valid REN.  
3. Data Access time (Ta) is <3.6ns when PLL is off, with respect to rising edges of RCLK.  
Figure 10. SDR Read Operation with PLL OFF  
31  
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(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
STANDARDMODEOPERATION  
Changingqueuesrequires4WCLKcyclesonthewriteport(seeFigure42,  
SDRWriteQueueSelect,WriteOperationandFullflagOperation).WADEN  
goes high signaling a change of queue (clock cycle “A”). The address on  
WRADDatthattimedeterminesthenextqueue.Datapresentedduringthat  
WRITE QUEUE SELECTION AND WRITE OPERATION  
(STANDARDMODE)  
The IDT72P51767/72P51777 multi-queue flow-control devices can be cycle,willbewrittentotheactive(each)queue,providedWENisLOW.IfWEN  
configured up to a maximum of 128 queues which data can be written via a is HIGH(inactive), data willnotbe writtenina queue. The write portdiscrete  
commonwriteportusingthedatainputs(Din),writeclock(WCLK)andwrite fullflagwillupdatetoshowthefullstatusofthenewlyselectedqueue.Datapresent  
enable(WEN).Thequeuetobewrittenisselectedbytheaddresspresenton onthedatainputbus(Din),canbewrittenintothenewlyselectedqueueonthe  
the write address bus (WRADD) during a rising edge on WCLK while write risingedgeofWCLK achangeofqueue,providedWENisLOWandthequeue  
addressenable(WADEN)isHIGH.ThestateofWENdoesnotimpactthequeue isnotfull.Iftheselectedqueueisfullatthepointofitsselection,anywritestothat  
selection.Thequeueselectionrequires4WCLKcycle.Allsubsequentdata queue willbe prevented. Data cannotbe writtenintoa fullqueue.  
writeswillbetothisqueueuntilanotherqueueisselected.  
RefertoFigure42,SDRWriteQueueSelect,WriteOperationandFullflag  
Standardmodeoperationisdefinedasindividualwordswillbewrittentothe Operation, and Figure 45, Full Flag Timing in Expansion Configuration for  
device. The write port is designed such that 100% bus utilization can be timingdiagrams.  
obtained.ThismeansthatdatacanbewrittenintothedeviceoneveryWCLK  
risingedge including the cycle thata newqueue is beingaddressed.  
TABLE 8 — WRITE ADDRESS BUS, WRADD[7:0]  
Operation WCLK WADEN FSTR  
WRADD[7:0]  
7 6 5 4 3 2  
1 0  
Write  
Queue  
Select  
1
0
0
1
Device Select  
(Compared to  
ID2,1,0)  
Write Queue Address  
(6 bits = 64 Queues  
7 bits = 128 Queues)  
7 6 5  
4
3 2 1 0  
PAFn  
Quadrant  
Select  
Device Select  
(Compared to  
ID2,1,0)  
X
Status Word  
Address  
Status Word  
Address  
Queue Status on PAFn Bus  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Q0 : Q7 → PAF0 : PAF7  
Q8 : Q15 → PAF0 : PAF7  
Q16 : Q23 → PAF0 : PAF7  
Q24 : Q31 → PAF0 : PAF7  
Q32 : Q39 → PAF0 : PAF7  
Q40 : Q47 → PAF0 : PAF7  
Q48 : Q55 → PAF0 : PAF7  
Q56 : Q63 → PAF0 : PAF7  
Q64 : Q71 → PAF0 : PAF7  
Q72 : Q79 → PAF0 : PAF7  
Q80 : Q87 → PAF0 : PAF7  
Q88 : Q95 → PAF0 : PAF7  
Q96 : Q103 → PAF0 : PAF7  
Q104 : Q111 → PAF0 : PAF7  
Q112 : Q119 → PAF0 : PAF7  
Q120 : Q127 → PAF0 : PAF7  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
READ QUEUE SELECTION AND READ OPERATION  
(STANDARDMODE)  
Standardmodeoperationisdefinedasindividualwordswillbereadfromthe  
device. The read port is designed such that 100% bus utilization can be  
The IDT72P51767/72P51777 multi-queue flow-control devices can be obtained.ThismeansthatdatacanbereadoutofthedeviceoneveryRCLK  
configureduptoamaximumof128queueswhichdatacanbereadviaacommon risingedge includingthe cycle that a newqueue is beingaddressed.  
readportusingthe data outputs (Qout), readclock(RCLK)andreadenable  
ChangingqueuesrequiresaminimumoffourRCLKcyclesonthereadport  
(REN). An output enable, OE control pin is also provided to allow High- (see Figure 46, SDR Read Queue Select, Read Operation). RADEN goes  
ImpedanceselectionoftheQoutdataoutputs.Themulti-queuedevicereadport highsignalinga change ofqueue (clockcycle “D”). The address onRDADD  
operatesinstandardIDTmodeorBOImode.Thequeuetobereadisselected atthattimedeterminesthenextqueue.Datapresentedduringthatcyclewillbe  
bythe address presentedonthe readaddress bus (RDADD)duringa rising read.Readingdatacancontinuefromtheactivequeue,providedRENisLOW.  
edgeonRCLKwhilereadaddressenable(RADEN)isHIGH.ThestateofREN IfRENisHIGH(inactive),datawillnotbereadfromthequeue.Ifanewselected  
does not impact the queue selection. The queue selection requires 4 RCLK queueisempty,readsfromthatqueuewillbeprevented.Datacannotberead  
cycles.Allsubsequentdatareadswillbefromthisqueueuntilanotherqueue fromanemptyqueue. RememberthatOEallowstheusertoplacethedataoutput  
isselected.  
bus(Qout)intoHigh-Impedanceandthedatacanbereadintotheoutputregister  
regardlessofOE.  
Refer to Table 9, for Read Address Bus arrangement.  
TABLE 9 — READ ADDRESS BUS, RDADD[7:0]  
Operation  
RCLK RADEN ESTR  
RDADD[7:0]  
7 6 5 4 3 2  
1 0  
Read Queue  
Select  
1
0
Device Select  
(Compared to  
ID2,1,0)  
Read Queue Address  
(6 bits = 64 Queues  
7 bits = 128 Queues)  
7 6 5  
Device Select  
(Compared to  
ID2,1,0)  
4
X
3 2 1 0  
Status Word  
Address  
PAEn  
Quadrant  
Select  
0
1
Status Word  
Address  
Queue Status on PAEn Bus  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Q0 : Q7 → PAF0 : PAF7  
Q8 : Q15 → PAF0 : PAF7  
Q16 : Q23 → PAF0 : PAF7  
Q24 : Q31 → PAF0 : PAF7  
Q32 : Q39 → PAF0 : PAF7  
Q40 : Q47 → PAF0 : PAF7  
Q48 : Q55 → PAF0 : PAF7  
Q56 : Q63 → PAF0 : PAF7  
Q64 : Q71 → PAF0 : PAF7  
Q72 : Q79 → PAF0 : PAF7  
Q80 : Q87 → PAF0 : PAF7  
Q88 : Q95 → PAF0 : PAF7  
Q96 : Q103 → PAF0 : PAF7  
Q104 : Q111 → PAF0 : PAF7  
Q112 : Q119 → PAF0 : PAF7  
Q120 : Q127 → PAF0 : PAF7  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SWITCHING QUEUES ON THE WRITE PORT  
bus (WRADD) during a rising edge of WCLK while Write Address Enable  
The IDT72P51767/72P51777 multi-queue flow-control devices can be (WADEN)isHIGH.Forreference,thestateofWriteEnable(WEN)isa“Don’t  
configureduptoamaximumof128queues.Dataiswrittenintoaqueueusing Care”duringaqueueselection.WENhassignificanceduringthequeuemark  
theDataInput(Din)bus,WriteClock(WCLK)andWriteEnable(WEN)signals. operation.Selectingaqueuerequires4WCLKcycles.RefertoFigure11,Write  
SelectingaqueueoccursbyplacingthequeueaddressontheWriteAddress PortSwitchingQueuesSignalSequence.  
Queue Switch Cycle  
QS-1  
QS0  
QS1  
QS2  
QS3  
WCLK  
Queue  
address  
Queue  
address  
WRADD  
WADEN  
6724 drw13  
Figure 11. Write Port Switching Queues Signal Sequence  
The IDT72P51767/72P51777 multi-queue flow-control device supports  
Formaximumefficiency,duringthe4clockcyclesrequiredtoswitchqueues  
changing(switching)queues everyfour(4)clockcycles. Toswitchfromthe theIDT72P51767/72P51777multi-queueflow-controldevicecancontinueto  
PresentQueue(PQ)toanotherqueuerequiresaqueueaddresstobeplaced writeintothePresentQueue(PQ).ThePresentQueueisdefinedasthecurrent  
on the Write Address Bus (WRADD) bus and a rising edge of Write Clock selectedqueue.RefertoFigure12,SwitchingQueuesBusEfficiency.  
(WCLK)andWriteAddressEnable(WADEN)isHIGH.Therearenorestrictions  
as to the order to which queues are selected or switched into or out of.  
*
Queue Switch Cycles  
WCLK  
WEN  
WADEN  
PQ  
PQ  
PQ  
PQ  
NQ  
NQ  
Din  
6724 drw14  
NOTES:  
1. PQ = Present Queue  
NQ = Next Queue  
* Requires 4 clock cycles to switch queues.  
Figure 12. Switching Queues Bus Efficiency  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
The IDT72P51767/72P51777 multi-queue flow-control device supports ThesimultaneousqueueswitchingmayoccurwitheithertheWriteClockand  
writingandreadingfromeitherthesamequeueoffromdifferentqueues.The ReadClocksynchronousorasynchronoustoeachother.Forreferencerefer  
devicealsosupportssimultaneousqueueswitchingonthewriteandreadports. toFigure13,Simultaneous QueueSwitching.  
WCLK  
WEN  
WADEN  
PQ  
PQ  
PQ  
PQ  
PQ  
NQ  
Din  
RCLK  
REN  
RADEN  
Qout  
PQ  
PQ  
PQ  
PQ  
PQ  
PQ  
PQ  
NQ  
6724 drw15  
Figure 13. Simultaneous Queue Switching  
Themulti-queueflow-controldevicerequires4clockcyclestoswitchqueues  
onthewriteport.RefertoTable10,WriteQueueSwitchOperationforadetailed  
descriptionofeachqueueswitchclockcycle.  
TABLE 10 — WRITE QUEUE SWITCH OPERATION  
Queue Switch Cycle  
IDT Mode  
QS-1  
QS0  
QS1  
QS2  
QueueSwitchInitiated,Rewrite/NoRewriteselection  
Queue MARK / Un-MARK  
—
• PAF signal updated for Next Queue (NQ)  
• Full Flag (FF) updated for NQ  
QS3  
StartofWriteDataOperation  
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(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
OUTPUT DATA DURING A QUEUE SWITCH  
REN  
REN  
(internal)  
RCLK  
tA  
EOP(1) EOP + 1(1)  
Qout  
EREN  
6724 drw15a  
During this cycle the 10G MQ  
device de-asserts EREN, and  
maintains word=EOP + 1 to the  
output data bus.  
During this cycle the 10G MQ  
device delivers word=EOP. The  
receiving device detects EOP and  
de-asserts REN, However the MQ  
sees a rising edge of RCLK with  
REN asserted and interprets it as  
another read request, and delivers  
EOP +1 on the next cycle.  
During this cycle the 10G MQ  
device detects the assertion of REN  
Data latency = cycle + 3.6ns (max)  
NOTE:  
1. Application specific.  
Figure 14. Application: Reading words from the MQ using the EOP bit to end the read operation  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
REN  
RCLK  
tA  
Qout  
0
1
EREN  
6724 drw15b  
During this cycle the 10G MQ  
device de-asserts EREN, and  
maintains word=0 to the output  
data bus.  
During this cycle the 10G MQ  
device delivers word=0.  
Data latency = cycle + 3.6ns (max)  
(from REN asserted)  
During this cycle the 10G MQ  
device detects the assertion of REN  
Figure 15. Output Data during a Queue Switch (SDR w/o PLL)  
JANUARY18,2006  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Parameters: SDR Mode, PLL=ON, 1 read operation, centered aligned data/clock  
pause, 1 word read operation  
REN  
RCLK  
tA  
Qout  
0
1
EREN  
6724 drw15c  
During this cycle the 10G MQ  
device de-asserts EREN,  
maintains the output data  
register with word=0.  
During this cycle the 10G MQ  
device asserts EREN, loads the  
output data register with word=0.  
During this cycle the 10G MQ  
device detects the assertion of REN  
Data latency = cycle + (+/-0.48ns)  
(from REN asserted)  
Figure 16. Output Data during a Queue Switch (SDR w/ PLL)  
JANUARY18,2006  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Parameters: DDR Mode, PLL=ON, 1 word read operation, centered aligned data/clock  
pause with No queue switch, 1 word read operation  
REN  
RCLK  
tA  
2 3  
0
1
Qout  
EREN  
6724 drw15d  
During this cycle the 10G MQ  
device de-asserts EREN,  
maintains the output data  
register with word=1.  
During this cycle the 10G MQ  
device asserts EREN, loads the  
output data register with word-0  
then word=1.  
During this cycle the 10G MQ  
device detects the assertion of REN  
Data latency = cycle + tA (+/-0.48ns)  
(from REN asserted)  
Figure 17. Output Data during a Queue Switch (DDR w/ PLL)  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Parameters: DDR Mode, PLL=OFF, 1 word read operation, edge aligned data/clock  
pause with No queue switch, 1 word read operation  
REN  
RCLK  
tA  
2 3  
0
1
Qout  
EREN  
6724 drw15e  
During this cycle the 10G MQ  
device de-asserts EREN,  
maintains the output data  
register with word=1.  
During this cycle the 10G MQ  
device asserts EREN, loads the  
output data register with word-0  
then word=1.  
During this cycle the 10G MQ  
device detects the assertion of REN  
Data latency = cycle + tA (3.6ns)  
Figure 18. Output Data during a Queue Switch (DDR w/o PLL)  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Parameters: DDR Mode, PLL=ON, 2 word read operation, WITH QUEUE SWITCH  
to NQ and QUEUE SWITCH BACK TO ORIGINAL QUEUE, 2 word read operation  
REN  
4 cycles  
4 cycles  
RCLK  
tA  
1
a
b
0
c
Qout  
d
EREN  
6724 drw15f  
During this cycle the 10G MQ  
device de-asserts EREN, loads  
the output data register with  
word=2 and addresses memory.  
During this cycle the 10G MQ  
device asserts EREN, loads the  
output data register with word-0  
& 1 and addresses memory.  
tA = cycle + (+/-0.48ns)  
During this cycle the 10G MQ  
device detects the assertion of REN  
and addresses memory word=0 & 1.  
Figure 19. Output Data during two Queue Switches (DDR w/ PLL)  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Parameters: SDR Mode, PLL=OFF, 3 word read operation, edge aligned data/clock,  
pause with No queue switch.  
REN  
-2  
-1  
0
RCLK  
tA  
EOP - 1(1)  
EOP(1)  
EOP - 2(1)  
Qout  
EREN  
6724 drw15g  
During this cycle the 10G MQ  
device de-asserts EREN, maintains  
the output data register with word=1  
During this cycle the 10G MQ  
device asserts EREN, loads the  
output data register with word-0  
then word=1.  
Data latency = cycle + tA (3.6ns) max  
During this cycle the 10G MQ  
device detects the assertion of REN.  
NOTE:  
1. Application specific.  
Figure 20. Output Data during two Queue Switches (DDR w/o PLL)  
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(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE 11 — BACKUP USAGE WHEN RE-ENTERING A QUEUE  
Operating  
Frequency  
Range  
Mode of  
Operation  
Clock used by  
receiving device  
to latch data  
Method to Stop  
Read Port  
operation  
Word Count  
-1 word MQ  
backup  
required  
N
1Mhz to 166Mhz  
SDR  
PLL=OFF  
SDR  
Read Clock  
1Mhz to 166Mhz  
Read Clock  
/ERCLK  
EOP Processing  
Word Count  
EOP Processing  
Word Count  
EOP Process  
Word Count  
EOP Process  
Y (BOI)  
N
PLL=OFF  
83.33Mhz to  
166Mhz  
83.33Mhz to  
166Mhz  
SDR  
PLL=ON  
DDR  
PLL=ON  
DDR  
PLL=OFF  
SDR  
PLL=OFF  
SDR  
PLL=OFF  
SDR  
/ERCLK  
Y (BOI)  
N
1Mhz to 100Mhz  
Read Clock  
Read Clock  
ERCLK  
1Mhz to 100Mhz  
Y (BOI)  
N
90Mhz to  
100Mhz  
90Mhz to  
100Mhz  
ERCLK  
Y (BOI)  
PLL=OFF  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SWITCHING QUEUES ON THE READ PORT  
Address Enable (RADEN)is HIGH. Forreference, the state ofReadEnable  
The IDT72P51767/72P51777 multi-queue flow-control devices can be (REN) is a “Don’t Care” during a read port queue selection. REN has  
configureduptoamaximumof128queues.Dataisreadfromaqueueusing significance duringthe queue markoperation. Selectinga queue requires 4  
the Data Output (Qout) bus, Read Clock (RCLK) and Read Enable (REN) RCLK cycles. Refer to Figure 21, Read Port Switching Queues Signal  
signals.Selectingaqueueonthereadportoccursbyplacingthequeueaddress Sequence.  
ontheReadAddressbus(RDADD)duringarisingedgeofRCLKwhileRead  
Queue Switch Cycle  
QS-1  
QS0  
QS1  
QS2  
QS3  
RCLK  
Queue  
address  
Queue  
address  
RDADD  
RADEN  
6724 drw16  
Figure 21. Read Port Switching Queues Signal Sequence  
The IDT72P51767/72P51777 multi-queue flow-control device supports  
Formaximumefficiency,duringthe4clockcyclesrequiredtoswitchqueues  
changing(switching)queues everyfour(4)clockcycles. Toswitchfromthe theIDT72P51767/72P51777multi-queueflow-controldevicecancontinueto  
PresentQueue(PQ)toanotherqueuerequiresaqueueaddresstobeplaced readfromthePresentQueue(PQ).ThePresentQueueisdefinedasthecurrent  
on the Read Address Bus (RDADD) bus and a rising edge of Read Clock selectedqueue.RefertoFigure22.SwitchingQueuesBusEfficiency.  
(RCLK) and Read Address Enable (RADEN) is HIGH. There are no  
restrictionsastotheordertowhichqueuesareselectedorswitchedintoorout  
of.  
Queue Switch Cycles  
RCLK  
REN  
RADEN  
PQ  
PQ  
PQ  
PQ  
PQ  
PQ  
NQ  
Qout  
6724 drw17  
NOTE:  
PQ = Present Queue  
NQ = Next Queue  
Figure 22. Switching Queues Bus Efficiency  
JANUARY18,2006  
44  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SIMULTANEOUS QUEUE SWITCHING  
WriteClocksynchronousorasynchronoustoeachother.Forreferencerefer  
toFigure23,Simultaneous QueueSwitching.  
Themulti-queueflow-controldevicerequires4clockcyclestoswitchqueues  
onthereadport,refertoTable12,ReadQueueSwitchOperationforadetailed  
descriptionofeachqueueswitchclockcycles.  
The IDT72P51767/72P51777 multi-queue flow-control device supports  
readingandwritingfromeitherthesamequeueorfromdifferentqueues.The  
devicealsosupportssimultaneousqueueswitchingonthereadandwriteports.  
ThesimultaneousqueueswitchingmayoccurwitheithertheReadClockand  
WCLK  
WEN  
WADEN  
PQ  
PQ  
PQ  
PQ  
NQ  
Din  
RCLK  
REN  
RADEN  
Qout  
PQ  
PQ  
PQ  
PQ  
PQ  
PQ  
NQ  
6724 drw18  
Figure 23. Simultaneous Queue Switching  
TABLE 12 — READ QUEUE SWITCH OPERATION  
Queue Switch  
Cycle  
IDT Mode  
QS-1  
QS0  
QS1  
QS2  
QueueSwitchInitiated,Re-read/NoRe-readselection  
Queue MARK / Un-MARK  
—
• PAE signal updated for Next Queue (NQ)  
• Empty Flag (EF) updated for NQ  
QS3  
StartofReadDataOperation  
TABLE 13 — SAME QUEUE SWITCH  
PQ  
NQ  
Supported  
Comment  
NotMarked  
NotMarked  
Marked  
NotMarked  
Marked  
Yes  
Yes  
QueueSwitchisignored  
Add Mark to current queue  
Not Marked, No Reread  
Not Marked, Reread  
Marked, No Reread  
Marked, Reread  
NotAllowed  
Yes  
Marked  
Remove Mark  
Keep Mark  
Legend:  
PQ = Present Queue  
NQ = Next Queue  
Marked  
NotAllowed  
Yes  
Marked  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
QUEUE MARKing  
MARK AND REWRITE/ MARK AND REREAD  
TheoverallintentoftheMARKfunctionistoprovidetheabilitytoeitherre-  
writeand/orre-readinformationthatis storedintoaqueue.  
TheMARKfunctionalityoperatesinanymodecombination (BOImode,IDT  
StandardMode). Queues ontheWritePortareMARKedusingtheWCLK&  
AqueuecanbeMARKedbyeitherthewriteportorthereadport.TheMARK WADENsignals.QueuesontheReadPortareMARKedusingtheRCLKand  
operationisportindependent.Thesamequeuecanbemarkedbythewriteport RADENsignals. Refertothe followingtimingdiagrams foradditionalqueue  
and the read port simultaneously. Only the active queue can be MARKed, MARKdetails.RefertoFigure24and25forfurtherinformation.  
multiplequeuescanNOTbeMARKedbyaport.Aport(writeorread)mayonly  
designateonequeueMARKedatatime. Uponaqueueswitchadecisionmust  
bemadeastowhethertoreturntotheMarkedlocationorthelastaccessaddress.  
A
QS-1  
B
QS0  
C
QS1  
D
E
QS2  
QS3  
WCLK  
WEN  
QS  
WADEN  
DIN  
Present Queue (PQ)  
Next Queue (NQ)  
6724 drw29  
•
•
@QS-1, if WEN=0 and WADEN=1, PQ will be updated in QS0,1, and 2, and NQ data will be written in QS3.  
@QS-1,ifWEN_N=1andWADEN=1,there is noupdate forPQduringQS0-QS2.Nexttime PQis switchedback,data willbe writtenintolastupdate  
location(rewrite).  
•
•
@QS0, WADENstatus is usedtodetermine if a “mark”is requestedforNQ. IfWADEN=1inQS0, NQwillbe marked. InIDTmode, the firstNQ  
positionafterQSis marked(latchWFCRvalues before QS3),data can’tbe readoutbeyondthis location.  
@QS0,ifWADEN=0,NQisnotmarked.  
Figure 24. MARK and Re-Write Sequence  
A
QS-1  
B
QS0  
C
QS1  
D
QS2  
E
QS3  
F
QS4  
RCLK  
REN  
QS  
RADEN  
QOUT  
Present Queue  
Next Queue  
6724 drw30  
• @QS-1,ifREN=0andRADEN=1,PresentQueuewillbeupdatedinQS0,QS1,andQS2,andthedatafromtheNextQueue(NQ)willbeavailableinQS4.  
• @QS-1,ifREN=1andRADEN=1,PresentQueuewillnotbeupdatedQS0-QS2.TheNexttimePQisselected,thedatawillbefromthelastupdatedlocation.  
• @QS0,RADENstatus is usedtodetermine ifa “mark”is requestedforNQ.IfRADEN=1inQS0,NQwillbe marked.InIDTmode,firstNQpositionafter  
QSis marked(latchRFCRvalues before QS3), data can’t overwrite this location.  
Figure 25. MARK and Re-Read Sequence  
JANUARY18,2006  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
This rising edge of  
Wri te Queue M A RK  
WCLK isthestart of the  
1st cycle  
A
B
Wri te Queue  
Select Cycle  
Write Queue  
MARK Cycle  
WCLK  
WADEN  
WADEN  
ACTION  
B
A
1
1
1
0
Selects the Queue and MARK the Queue  
Selects a Queue  
6724 drw36  
Figure 26. MARKing a Queue - Write Queue MARK  
This rising edge of  
RCLK isthestart  
of the1st cycle  
Read Queue MARK  
A
B
Read Queue  
Select Cycle  
Read Queue  
MARK Cycle  
RCLK  
RADEN  
RADEN  
ACTION  
B
A
1
1
1
0
Selects the Queue and MARK the Queue  
Selects a Queue  
6724 drw37  
Figure 27. MARKing a Queue - Read Queue MARK  
MARK Operational Notes:  
WritePort  
ReadPort  
- MARKing can only occur during a Queue switch cycle  
- The entire Queue is MARKedata time.  
- MARKisusedtomarkthefirstlocationoftheQueue.  
- MARK can NOT be moved within the queue.  
- MARKing can only occur during a Queue switch cycle  
- OnlythefirstlocationoftheQueuecanbeMARKed.  
- TheMARKcanNOTbemovedlocationtolocationwithinthequeue.  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Un-MARKing a Queue  
UN-MARKing a Queue  
This rising edge of  
Write Queue UN-MARK  
WCLK i s the start  
of the1st cycle  
A
B
Write Queue  
Select Cycle  
Write Queue  
MARK Cycle  
WCLK  
WADEN  
WADEN  
ACTION  
B
A
1
0
Selects a Queue and UN-MARK the Queue  
6724 drw38  
Figure 28. UN-MARKing a Queue - Write Queue UN-MARK  
This rising edge of  
Read Queue UN-MARK  
RCLK isthestart  
of the1st cycle  
A
B
Read Queue  
Select Cycle  
Read Queue  
MARK Cycle  
RCLK  
RADEN  
RADEN  
ACTION  
B
A
1
0
Selects a Queue and UN-MARK the Queue  
6724 drw39  
Figure 29. UN-MARKing a Queue - Read Queue UN-MARK  
UN-MARK Operational Notes:  
WritePort  
ReadPort  
- Un-MARKing can only occur during a Queue switch cycle.  
- UN-MARKingaQueuecanbeaccomplishedbyeitherswitchingto  
thesamequeueorswitchingtoanotherqueue.  
- Un-MARKing can only occur during a Queue switch cycle.  
- UN-MARKingaQueuecanbeaccomplishedbyeitherswitchingtothe  
samequeueorswitchingtoanotherqueue.  
- Note only 1 queue can be marked at any given time.  
- TheMARKcanNOTbemovedlocationtolocationwithinthequeue.  
- Note only 1 queue can be marked at any given time.  
- TheMARKcanNOTbemovedlocationtolocationwithinthequeue.  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Leaving a MARK Active  
DuringaQueueswitchthevalueofWENforthewriteportandRENforthe  
readportdetermineswhethertheMARKremainsactiveorisde-activated.  
Leaving a MARK active on the Write Port  
Write Queue  
Select Cycle  
Write Queue  
MARK Cycle  
WCLK  
WADEN  
Leave the MARK  
WEN  
(A rewrite  
request)  
6724 drw40  
Figure 30. Leaving a MARK active on the Write Port  
Leaving a MARK active on the Read Port  
Read Queue  
Select Cycle  
Read Queue  
MARK Cycle  
RCLK  
RADEN  
Leave the MARK  
REN  
(A re-read  
request)  
6724 drw41  
Figure 31. Leaving a MARK active on the Read Port  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Inactivating a MARK  
DuringaQueueswitchthevalueofWENforthewriteportandRENforthe  
readportdetermineswhethertheMARKremainsactiveorisde-activated.  
Inactivating a MARK on the Write Port  
Write Queue  
Select Cycle  
Write Queue  
MARK Cycle  
WCLK  
WADEN  
Inactivate the  
Write Port MARK  
WEN  
6724 drw42  
(No re-write)  
Figure 32. Inactivating a MARK on the Write Port Active  
Inactivating a MARK on the Read Port  
Read Queue  
Select Cycle  
Read Queue  
MARK Cycle  
RCLK  
RADEN  
Inactivate the  
Read Port MARK  
REN  
6724 drw43  
(No re-read)  
Figure 33. Inactivating a MARK on the Read Port Active  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Write Cycle  
1st Cycle  
2nd Cycle  
WEN  
(active LOW)  
WADEN  
(active HIGH)  
WEN  
(active LOW)  
0
WADEN  
(active HIGH)  
Action  
NO  
0
1
0
1
0
1
0
0
0
1
1
Operation  
Selects a  
Queue  
NO  
Operation  
NO  
0
1
1
1
Operation  
6724 drw44  
Read Cycle  
Action  
1st Cycle  
2nd Cycle  
RADEN  
REN  
REN  
(active LOW)  
0
RADEN  
(active HIGH)  
0
(active HIGH)  
(active LOW)  
NO  
0
1
0
1
0
0
1
1
Operation  
Selects a  
Queue  
NO  
Operation  
NO  
0
1
1
1
0
1
Operation  
6724 drw45  
JANUARY18,2006  
51  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag  
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis  
madeonlyasingledevicedrivestheFFflagbusandallotherFF flagoutputs  
connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes  
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control  
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennone  
ofitsqueuesareselectedforwriteoperations.  
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF  
flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill  
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.  
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased  
onthe1-3bitIDcode(1iftwomulti-queueareconfiguredwithamaximumtotal  
of256queues,2iffourdevicesareusedtotallingamaximumof256queues,  
and3ifthereareuptoeightdeviceswithamaximumtotalof256queues)found  
inthe1-3mostsignificantbitsofthewritequeueaddressbus,WRADD.Ifthe  
1-3mostsignificantbitsofWRADDmatchthe1-3bitIDcodesetuponthestatic  
inputs,ID0,ID1andID2thentheFFflagoutputoftherespectivedevicewillbe  
inaLow-Impedancestate.Iftheydonotmatch,thentheFFflagoutputofthe  
respectivedevicewillbeinaHigh-Impedancestate.SeeFigure45,FullFlag  
TiminginExpansionConfigurationfordetailsofflagoperation,includingwhen  
more thanone device is connectedinexpansion.  
FLAGDESCRIPTION  
PAFn FLAG BUS OPERATION  
The IDT72P51767/72P51777 multi-queue flow-control device can be  
configuredforupto128queues,eachqueuehavingitsownalmostfullstatus.  
Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF,on  
thewriteport.Queuesthatarenotselectedforawriteoperationcanhavetheir  
PAFstatus monitoredviathe PAFnbus.ThePAFnflagbus is 8bits wide,so  
that8queuesatatimecanhavetheirstatusoutputtothebus.If9ormorequeues  
aresetupwithinadevicethenthereare2methodsbywhichthedevicecanshare  
thebusbetweenqueues,“Direct”modeand“Polled”modedependingonthe  
state ofthe FM(FlagMode)inputduringa MasterReset. If8orless queues  
aresetupwithinadevicetheneachwillhaveitsowndedicatedoutputfromthe  
bus.If8orlessqueuesaresetupinsingledevicemode,itisrecommendedto  
configure the PAFnbus topolledmode as itdoes notrequire usingthe write  
address(WRADD).  
FULL FLAG OPERATION  
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.  
TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe  
writeportforwriteoperations.Internallythemulti-queueflow-controldevice  
monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however  
onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe  
FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.  
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput  
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,  
onthe3rdcycleafteranewqueueselectionismade.Theuserthenhasafull  
status forthenewqueueonecycleaheadoftheWCLKrisingedgethatdata  
can be written into the new queue. That is, a new queue can be selected on  
thewriteportviatheWRADDbus,WADENenableandarisingedgeofWCLK.  
Onthe4thrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthe  
newlyselectedqueue.OntheforthrisingedgeofWCLKfollowingthequeue  
selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata  
andenablesetup&holdtimesaremet.  
Note,theFFflagwillprovidestatusofanewlyselectedqueuethreeWCLK  
cycleafterqueueselection,whichisonecyclebeforedatacanbewrittentothat  
queue.Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assuming  
thataqueueswitchhas beenmadetoaqueuethatis actuallyfull).  
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur  
basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand  
keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa  
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue  
flag (selected on the write port). A queue selected on the read port may  
experienceachangeofitsinternalfullflagstatusbasedonreadoperations.  
See Figure 42, SDR Write Queue Select, Write Operation and Full Flag  
OperationandFigure45,FullFlagTiminginExpansionConfigurationfortiming  
information.  
EMPTYFLAGOPERATION(EF)  
Themulti-queueflow-controldeviceprovidesasingleEmptyflagoutput,EF.  
TherisingedgeofanRCLKcyclethatplacesnewdataontotheoutputregister  
ofthe readport. Internallythe multi-queue flow-controldevice monitors and  
maintainsastatusoftheemptyconditionofallqueueswithinit.  
SeeFigure46,SDRReadQueueSelect,ReadOperation fordetailsofthe  
timing.  
EXPANSION–EMPTYFLAGOPERATION  
Whenmulti-queuedevicesareconnectedinExpansionconfiguration,theEF  
flagsofalldevicesshouldbeconnectedtogether,suchthatasystemcontroller  
monitoring and managing the multi-queue devices read port only looks at a  
singleEFflag(asopposedtoadiscreteEFflagforeachdevice).ThisEFflag  
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.  
Remember,thatwheninexpansionconfigurationonlyonemulti-queuedevice  
canbereadfromatanymomentintime,thustheEFflagprovidesstatusofthe  
active queue on the read port.  
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheEFflag  
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis  
madeonlyasingledevicedrivestheEFflagbusandallotherEFflagoutputs  
connectedtotheEFflagbusareplacedintoHigh-Impedance.Theuserdoes  
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control  
devicewillautomaticallyplaceitsEFflagoutputintoHigh-Impedancewhennone  
ofitsqueuesareselectedforreadoperations.  
Whenqueueswithinasingledeviceareselectedforreadoperations,theEF  
flagoutputofthatdevicewillmaintaincontroloftheEFflagbus.ItsEFflagwill  
simplyupdatebetweenqueueswitchestoshowtherespectivequeuestatus.  
Themulti-queuedeviceplacesitsEFflagoutputintoHigh-Impedancebased  
onthe1-3bitIDcode(1iftwomulti-queueareconfiguredwithamaximumtotal  
of256queues,2iffourdevicesareusedtotallingamaximumof256queues,  
and3ifthereareuptoeightdeviceswithamaximumtotalof256queues)found  
inthe3mostsignificantbitsofthereadqueueaddressbus,RDADD.Ifthe3most  
significantbitsofRDADDmatchthe1-3bitIDcodesetuponthestaticinputs,ID0,  
ID1andID2thenthe EF flagoutputofthe respective device willbe ina Low-  
Impedancestate.Iftheydonotmatch,thentheEFflagoutputoftherespective  
devicewillbeinaHigh-Impedancestate.  
EXPANSION CONFIGURATION - FULL FLAG OPERATION  
Whenmulti-queuedevicesareconnectedinExpansionconfigurationtheFF  
flagsofalldevicesshouldbeconnectedtogether,suchthatasystemcontroller  
monitoring and managing the multi-queue devices write port only looks at a  
singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag  
isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime.  
Remember,thatwheninexpansionconfigurationonlyonemulti-queuedevice  
canbewrittentoatanymomentintime,thustheFFflagprovidesstatusofthe  
active queue onthe write port.  
JANUARY18,2006  
52  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
ALMOST FULL FLAG  
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost  
As previously mentioned the multi-queue flow-control device provides a emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia  
singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti-  
astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe queuedeviceprogramming(alongwiththenumberofqueues,queuedepths  
writeportforwriteoperations.Internallythemulti-queueflow-controldevice andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe  
monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory  
it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice  
outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue canbedifferentvalues.  
almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe  
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput  
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,  
viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe onthethirdcycleafteranewqueueselectionismade,onthesameRCLKcycle  
userhasperformeddefaultprogramming.  
thatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.That  
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost is,anewqueuecanbeselectedonthereadportviatheRDADDbus,RADEN  
fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe enableandarisingedgeofRCLK.OnthethirdrisingedgeofRCLKfollowing  
PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue a queue selection, the data wordfromthe newqueue willbe available atthe  
device programming (along with the number of queues, queue depths and outputregisterandthePAEflagoutputwillshowtheemptystatusofthenewly  
almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe selectedqueue.ThePAEisflagoutputisdoubleregisterbuffered,sowhena  
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory readoperationoccursatthealmostemptyboundarycausingtheselectedqueue  
depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice statustogoalmostemptythePAEwillgoLOW3RCLKcyclesaftertheread.  
canbedifferentvalues.  
Thesameistruewhenawriteoccurs,therewillbea3RCLKcycledelayafter  
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput thewriteoperation.  
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,  
SothePAEflagdelayfromareadoperationtoPAEflagLOWis3RCLK+  
onthethirdcycleafteranewqueueselectionismade,onthesameWCLKcycle tRAE.ThedelayfromawriteoperationtoPAEflagHIGHis tSKEW2 +RCLK+  
thatdata canactuallybe writtentothe newqueue. Thatis, a newqueue can tRAE.  
beselectedonthewriteportviatheWRADDbus,WADENenableandarising  
edgeofWCLK.OnthethirdrisingedgeofWCLKfollowingaqueueselection,  
Note, if tSKEW is violated there will be one added RCLK cycle delay.  
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag  
thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.ThePAF occur based on a rising edge of RCLK. Internally the multi-queue device  
isflagoutputisdoubleregisterbuffered,sowhenawriteoperationoccursat monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible  
thealmostfullboundarycausingtheselectedqueuestatustogoalmostfullthe thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis  
PAFwillgoLOW3WCLKcyclesafterthewrite.Thesameistruewhenaread nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe  
occurs, there will be a 3 WCLK cycle delay after the read operation.  
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased  
SothePAFflagdelayfromawriteoperationtoPAFflagLOWis3WCLK+ on write operations. The multi-queue flow-control device also provides a  
tWAF.ThedelayfromareadoperationtoPAF flagHIGHistSKEW2 +WCLK+ duplicateofthePAEflagonthePAE[7:0]flagbus,thiswillbediscussedindetail  
tWAF.  
inalatersectionofthedatasheet.  
Note, if tSKEW is violated there will be one added WCLK cycle delay.  
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag  
occur based on a rising edge of WCLK. Internally the multi-queue device PAFn - DIRECT BUS  
SeeFigures25and26forAlmostEmptyflagtimingandqueueswitching.  
monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible  
IfFMisLOWatmasterresetthenthePAFnbusoperatesinDirect(addressed)  
thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis mode. In direct mode the user can address the status word of queues they  
nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe require and it will be placed on to the PAFn bus. For example, consider the  
readportmayexperienceachangeofitsinternalalmostfullflagstatusbased operationofthePAFnbuswhen26queueshavebeensetup.Tooutputstatus  
on read operations. The multi-queue flow-control device also provides a ofthefirststatusword,Queue[0:7]theWRADDbusisusedinconjunctionwith  
duplicateofthePAFflagonthePAF[7:0]flagbus,thiswillbediscussedindetail the FSTR (PAF flag strobe) input and WCLK. The address present on the 4  
inalatersectionofthedatasheet.  
SeeFigures 23and24forAlmostFullflagtimingandqueueswitching.  
leastsignificantbitsoftheWRADDbuswithFSTRHIGHwillbeselectedasthe  
status word address on a rising edge of WCLK. To address status word 0,  
Queue[0:7]theWRADDbusshouldbeloadedwith“0010000”,thePAFnbus  
willchangestatustoshowthenewstatuswordselected1WCLKcycleafterstatus  
ALMOSTEMPTYFLAG  
As previously mentioned the multi-queue flow-control device provides a wordselection.PAFn[0:7]getsstatusofqueues,Queue[0:7]respectively.  
single Programmable Almost Empty flag output, PAE. The PAE flag output Toaddressstatusword1,Queue[8:15],theWRADDaddressis“00100001”.  
providesastatusofthealmostemptyconditionfortheactivequeuecurrently PAFn[0:7]getsstatusofqueues,Queue[8:15]respectively.Toaddressthe2nd  
selectedonthereadportforreadoperations.Internallythemulti-queueflow- statusword,Queue[16:23],theWRADDaddressis“00100010”.PAF[0:7]gets  
controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof statusofqueues,Queue[16:23]respectively.Toaddressthe3rdstatusword,  
allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations Queue[24:31], the WRADD address is “00100011”. PAF[0:1] gets status of  
hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred queues,Queue[24:25]respectively.Remember,only26queuesweresetup,  
toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary sowhenstatusword4isselectedtheunusedoutputsPAF[2:7]willbedon'tcare  
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan states.  
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128)  
canbeselectediftheuserhasperformeddefaultprogramming.  
Note, that if a read or write operation is occurring to a specific queue, say  
queue‘x’onthesamecycleasastatuswordswitchwhichwillincludethequeue  
JANUARY18,2006  
53  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
‘x’,thentheremaybeanextraWCLKcycledelaybeforethatqueuesstatusis PAEn FLAG BUS OPERATION  
correctlyshownontherespectiveoutputofthePAFnbus.However,theactive  
PAFflagwillshowcorrectstatusatalltimes.  
The IDT72P51767/72P51777 multi-queue flow-control device can be  
configured for up to 128 queues, each queue having its own almost empty/  
Statuswordscanbeselectedonconsecutiveclockcycles,thatisthestatus packetreadystatus.Anactivequeuehasitsflagstatusoutputtothediscreteflag,  
wordonthePAFnbuscanchangeeveryWCLKcycle.Also,datapresenton PAE,onthereadport.Queuesthatarenotselectedforareadoperationcan  
theinputbus,Din,canbewrittenintoaQueueonthesameWCLKrisingedge havetheirPAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis8bits  
thatastatuswordisbeingselected,theonlyrestrictionbeingthatawritequeue wide,sothat8queuesatatimecanhavetheirstatusoutputtothebus.If9or  
selectionandPAFnstatuswordselectioncannotbemadeonthesamecycle. morequeuesaresetupwithinadevicethenthereare2methodsbywhichthe  
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAFstatus devicecansharethebusbetweenqueues,"Direct"modeand"Polled"mode  
outputonPAF[0:7]constantly.  
dependingonthestateoftheFM(FlagMode)inputduringaMasterReset.If  
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone 8orlessqueuesaresetupwithinadevicetheneachwillhaveitsowndedicated  
devicethePAFnbussesofalldevicesareconnectedtogether,whenswitching outputfromthe bus. If8orless queues are setupinsingle device mode, itis  
betweenstatus words ofdifferentdevices the usermustutilize the 1-3most recommendedtoconfigurethePAFnbustopolledmodeasitdoesnotrequire  
significantbitsoftheWRADDaddressbus(aswellasthe2LSB’s).These1- usingthewriteaddress (WRADD).  
3MSb’scorrespondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1  
& ID2.  
Please refer to Figure 57 PAFn - Direct Mode Status Word Selection for  
PAEn - DIRECT BUS  
IfFMisLOWatmasterresetthenthePAEnbusoperatesinDirect(addressed)  
mode. In direct mode the user can address the status word of queues they  
requiretobeplacedontothePAEnbus.Forexample,considertheoperation  
ofthePAEnbuswhen26queueshavebeensetup.Tooutputstatusofthefirst  
timinginformation.AlsorefertoTable8,WriteAddressBus,WRADD.  
PAFn – POLLED BUS  
IfFMisHIGHatmasterresetthenthePAFnbusoperatesinPolled(looped) statusword,Queue[0:7]theRDADDbusisusedinconjunctionwiththeESTR  
mode.InpolledmodethePAFnbusonlycyclesthroughthenumberofstatus (PAEflagstrobe)inputandRCLK.Theaddresspresentonthe2leastsignificant  
words requiredtodisplaythestatus ofthenumberofqueues thathavebeen bits of the RDADD bus with ESTR HIGH will be selected as the status word  
setupinthepart.EveryrisingedgeoftheWCLKcausesthenextstatusword address ona risingedge ofRCLK. Sotoaddress status word1, Queue[0:7]  
to be loaded on the PAFn bus. The device configured as the master (MAST theRDADDbusshouldbeloadedwith“xxxx0000”,thePAEnbuswillchange  
inputtiedHIGH),willtakecontrolofthePAFnafterMRSgoesLOW.Forthewhole status toshowthe newstatus wordselected1RCLKcycle afterstatus word  
WCLKcyclethatthefirststatuswordisonPAFntheFSYNC(PAFnbussync) selection.PAEn[0:7]getsstatusofqueues,Queue[0:7]respectively.  
outputwillbeHIGH,forallotherstatuswords,thisFSYNCoutputwillbeLOW.  
Toaddress thesecondstatus word,Queue[8:15],theRDADDaddress is  
This FSYNC output provides the user with a mark with which they can “xxxx0001”. PAEn[0:7]gets status ofqueues,Queue[8:15]respectively.To  
synchronizetothePAFnbus,FSYNCisalwaysHIGHfortheWCLKcyclethat addressthethirdstatusword,Queue[16:23],theRDADDaddressis“xxxx0010”.  
the firststatus wordofa device is presentonthe PAFnbus.  
PAE[0:7]gets status ofqueues, Queue[16:23]respectively. Toaddress the  
Whendevicesareconnectedinexpansionconfiguration,onlyonedevice fourth status word, Queue[24:31], the RDADD address is “xxxx0011”.  
willbesetastheMaster(ID='000'),MASTinputtiedHIGH,allotherdevices PAE[0:1]getsstatusofqueues,Queue[24:25]respectively.Remember,only  
willhaveMASTtiedLOW.Themasterdeviceisthefirstdevicetotakecontrol 26queuesweresetup,sowhenstatusword4isselectedtheunusedoutputs  
ofthePAFnbusandwillplaceitsfirststatuswordonthebusontherisingedge PAE[2:7]willbedon'tcarestates.  
ofWCLK. ForthenextnWCLKcycles(n=numberofqueuesdividedby8with  
Note, that if a read or write operation is occurring to a specific queue, say  
nbeingincreasedbyone foranyremainder)the masterdevice willmaintain queue‘x’onthesamecycleasastatuswordswitchwhichwillincludethequeue  
controlofthePAFnbusandcycleitsstatuswordsthroughit,allotherdevices ‘x’,thentheremaybeanextraRCLKcycledelaybeforethatqueuesstatusis  
holdtheirPAFnoutputsinHigh-Impedance.Whenthemasterdevicehascycled correctlyshownontherespectiveoutputofthePAEnbus.  
allofitsstatuswordsitpassesatokentothenextdeviceinthechainandthat  
Statuswordscanbeselectedonconsecutiveclockcycles,thatisthestatus  
deviceassumescontrolofthePAFnbusandthencyclesitsstatuswordsand wordonthePAEnbuscanchangeeveryRCLKcycle.Also,datacanberead  
soon,thePAFnbuscontroltokenbeingpassedonfromdevicetodevice.This outofaQueueonthesameRCLKrisingedgethatastatuswordisbeingselected,  
tokenpassingisdoneviatheFXOoutputsandFXIinputsofthedevices(“PAF the onlyrestrictionbeingthata readqueue selectionand PAEnstatus word  
ExpansionOut”and“PAFExpansionIn”).TheFXOoutputofthemasterdevice selectioncannotbemadeonthesameRCLKcycle.  
connectstotheFXIoftheseconddeviceinthechainandtheFXOofthesecond  
connectstotheFXIofthethirdandsoon.ThefinaldeviceinachainhasitsFXO outputonPAE[0:7]constantly.  
connectedtotheFXIofthefirstdevice,sothatoncethePAFnbushascycled  
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAEstatus  
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone  
throughallstatuswordsofalldevices,controlofthePAFnwillpasstothemaster devicethePAEnbussesofalldevicesareconnectedtogether,whenswitching  
device again and so on. The FSYNC of each respective device will operate between status words of different devices the user must utilize the 3 most  
independentlyandsimplyindicatewhenthatrespectivedevicehastakencontrol significant bits of the RDADD address bus (as well as the 2 LSB’s). These 3  
ofthebus andis placingits firststatus wordontothePAFnbus.  
MSb’scorrespondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1  
WhenoperatinginsingledevicemodetheFXIinputmustbeconnectedto & ID2.  
theFXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired  
tobe passedintothe device foraccessingthePAFnbus.  
PleaserefertoFigure60,PAFnBus–PolledModefortiminginformation.  
Please refer to Figure 56, PAEn - Direct Mode Status Word Selection for  
timinginformation.AlsorefertoTable9,ReadAddressBus,RDADD.  
JANUARY18,2006  
54  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING  
Empty Flag, EF Flag Boundary  
Full Flag, FF Boundary  
FF Boundary Condition  
I/O Set-Up  
EF Boundary Condition  
I/O Set-Up  
In40 to out40  
In40 to out40 (Almost Empty Mode)  
(Bothportsselectedforsamequeue  
when the 1st Word is written in)  
EF Goes HIGH after 1st Write  
(seenote1belowfortiming)  
FF Goes LOW after D Writes  
(Bothportsselectedforsamequeue  
(seenotebelowfortiming)  
when the 1st Word is written in)  
EF Goes HIGH after 1st Write  
(seenote1belowfortiming)  
In40 to out40  
(Writeportonlyselectedforqueue  
when the 1st Word is written in)  
FF Goes LOW after D Writes  
(seenotebelowfortiming)  
In40 to out20  
(Bothportsselectedforsamequeue  
when the 1st Word is written in)  
EF Goes HIGH after 1st Write  
(seenote1belowfortiming)  
In40 to out20  
(Bothportsselectedforsamequeue  
when the 1st Word is written in)  
FF Goes LOW after D Writes  
(seenotebelowfortiming)  
In20 to out40  
(Bothportsselectedforsamequeue  
when the 1st Word is written in)  
In40 to out20  
(Writeportonlyselectedforqueue  
when the 1st Word is written in)  
FF Goes LOW after D Writes  
(seenotebelowfortiming)  
In20 to out40  
FF Goes LOW after ([D] x 2) Writes  
(seenotebelowfortiming)  
(Bothportsselectedforsamequeue  
NOTE:  
1. EF Timing  
when the 1st Word is written in)  
Assertion:  
In20 to out40  
FF Goes LOW after (D x 2) Writes  
(seenotebelowfortiming)  
Write to EF HIGH: tSKEW1 + RCLK + tROV  
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tREF  
De-assertion:  
(Writeportonlyselectedforqueue  
when the 1st Word is written in)  
Read Operation to EF HIGH: tREF  
2. In40 = SDR40 or DDR20  
NOTE:  
D = Queue Depth  
In20 = SDR20  
FF Timing  
Assertion:  
Write Operation to FF LOW: tWFF  
De-assertion:  
Read to FF HIGH: tSKEW1 + tWFF  
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF  
1. In40 = SDR40 or DDR20  
In20 = SDR20  
Programmable Almost Full Flag, PAF & PAFn Bus Boundary  
I/O Set-Up  
PAF & PAFn Boundary  
in40 to out40  
PAF/PAFn Goes LOW after  
(Bothportsselectedforsamequeuewhenthe1st D-mWrites  
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)  
in40 to out40  
PAF/PAFn Goes LOW after  
(Writeportonlyselectedforsamequeuewhenthe D-mWrites  
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)  
in40 to out20  
PAF/PAFn Goes LOW after  
D-mWrites(seebelowfortiming)  
NOTE:  
D = Queue Depth  
m = Almost Full Offset value.  
1. In40 = SDR40 or DDR20  
In20 = SDR20  
PAF Timing  
Assertion:  
Write Operation to PAF LOW: 3 WCLK + tWAF  
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF  
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 3 WCLK + tWAF  
PAFn Timing  
Assertion:  
Write Operation to PAFn LOW: 2 WCLK* + tPAF  
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF  
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 3 WCLK* + tPAF  
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion  
there may be one additional WCLK clock cycle delay.  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)  
Programmable Almost Empty Flag, PAE Boundary  
I/O Set-Up PAE Assertion  
PAE Goes HIGH after n+1  
(Bothportsselectedforsamequeuewhenthe1st Writes  
Programmable Almost Empty Flag Bus, PAEn Boundary  
I/O Set-Up PAEn Boundary Condition  
PAEn Goes HIGH after  
(Bothportsselectedforsamequeuewhenthe1st n+1Writes  
in40 to out40  
in40 to out40  
Wordiswritteninuntiltheboundaryisreached)  
(seenotebelowfortiming)  
Wordiswritteninuntiltheboundaryisreached)  
(seenotebelowfortiming)  
in40 to out40  
PAEn Goes HIGH after  
in40 to out20  
PAE Goes HIGH after n+1  
(Bothportsselectedforsamequeuewhenthe1st Writes  
(Writeportonlyselectedforsamequeuewhenthe n+1Writes  
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)  
Wordiswritteninuntiltheboundaryisreached)  
(seenotebelowfortiming)  
in40 to out20  
in20 to out40  
PAEn Goes HIGH after n+1  
in20 to out40  
PAE Goes HIGH after  
Writes (seebelowfortiming)  
(Bothportsselectedforsamequeuewhenthe1st ([n+1] x 2) Writes  
PAEn Goes HIGH after  
Wordiswritteninuntiltheboundaryisreached)  
(seenotebelowfortiming)  
(Bothportsselectedforsamequeuewhenthe1st ([n+1] x 2) Writes  
NOTE:  
Wordiswritteninuntiltheboundaryisreached)  
(seenotebelowfortiming)  
n = Almost Empty Offset value.  
1. In40 = SDR40 or DDR20  
in20 to out40  
PAEn Goes HIGH after  
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes  
In20 = SDR20  
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)  
PAE Timing  
Assertion:  
NOTE:  
Read Operation to PAE LOW: 3 RCLK + tRAE  
n = Almost Empty Offset value.  
1. In40 = SDR40 or DDR20  
In20 = SDR20  
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE  
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 3 RCLK + tRAE  
PAEn Timing  
Assertion:  
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE  
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 3 RCLK* + tPAE  
Read Operation to PAEn LOW: 3 RCLK* + tPAE  
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion  
there may be one additional RCLK clock cycle delay.  
PAEn – POLLED BUS  
themasterdevicewillmaintaincontrolofthePAEnbusandcycleitsstatuswords  
IfFMisHIGHatmasterresetthenthePAEnbusoperatesinPolled(looped) throughit,allotherdevicesholdtheirPAEnoutputsinHigh-Impedance.When  
mode.InpolledmodethePAEnbusautomaticallycyclesthroughthe4status themasterdevicehascycledallofitsstatuswordsitpassesatokentothenext  
words withinthe device regardless ofhowmanyqueues have beensetupin deviceinthechainandthatdeviceassumescontrolofthePAEnbusandthen  
thepart.EveryrisingedgeoftheRCLKcausesthenextstatuswordtobeloaded cyclesitsstatuswordsandsoon,thePAEnbuscontroltokenbeingpassedon  
onthePAEnbus.Thedeviceconfiguredasthemaster(MASTinputtiedHIGH), fromdevicetodevice.ThistokenpassingisdoneviatheEXOoutputsandEXI  
willtakecontrolofthePAEnafterMRSgoesLOW.ForthewholeRCLKcycle inputsofthedevices(“PAEExpansionOut”and“PAEExpansionIn”).TheEXO  
thatthefirststatuswordisonPAEntheESYNC(PAEnbussync)outputwillbe outputofthemasterdeviceconnectstotheEXIoftheseconddeviceinthechain  
HIGH,forallotherstatuswords,thisESYNCoutputwillbeLOW.ThisESYNC andtheEXOofthesecondconnectstotheEXIofthethirdandsoon.Thefinal  
outputprovides the userwitha markwithwhichtheycansynchronize tothe deviceinachainhasitsEXOconnectedtotheEXIofthefirstdevice,sothatonce  
PAEnbus,ESYNCisalwaysHIGHfortheRCLKcyclethatthefirststatusword thePAEnbushascycledthroughallstatuswordsofalldevices,controlofthe  
of a device is present on the PAEn bus.  
PAEn will pass to the master device again and so on. The ESYNC of each  
Whendevicesareconnectedinexpansionconfiguration,onlyonedevice respective device will operate independently and simply indicate when that  
willbe setas the Master(ID='000'), MASTinputtiedHIGH, allotherdevices respectivedevicehastakencontrolofthebusandisplacingitsfirststatusword  
willhaveMASTtiedLOW.Themasterdeviceisthefirstdevicetotakecontrol ontothe PAEnbus.  
ofthePAEnbusandwillplaceitsfirststatuswordonthebusontherisingedge  
WhenoperatinginsingledevicemodetheEXIinputmustbeconnectedto  
ofRCLKaftertheMRSinputgoesLOW.ForthenextnRCLKcycles(n=number theEXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired  
ofqueuesdividedby8withnincrementingbyoneshouldtherebearemainder) tobepassedintothedeviceforaccessingthePAEnbus.  
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(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TABLE 15 — INTERFACE DATA RATES  
Supported Data Transfer Rate  
Input Interface  
SDR  
Output Interface  
SDR  
Combination  
Yes  
SDR  
DDR  
Yes  
DDR  
SDR  
Yes  
DDR  
DDR  
Yes  
OUTPUTINTERFACE  
INPUT INTERFACE  
TheoutputinterfacewillprovideaCenteredAligneddataclockforDouble  
DataRate(DDR)operationandEdgeAligneddataclockforSingleDataRate  
(SDR) operation. The output interface will support either Single Data Rate  
(SDR) data transfers or Double Data Rate (DDR) data transfers.  
TheinputportwillsupporteitherEdgeAligneddataclockingorCenterAligned  
dataclocking.Nodeviceconfigurationisrequired.ForreferenceXGMIIuses  
centeralignedclocking.  
TheinputinterfacewillsupporteitherSingleDataRate(SDR)datatransfers  
or Double Data Rate (DDR) data transfers.  
Note,thesumof(tamax+tsumin)mustbelessthanthecycletime.  
DDR Cycle Time  
ERCLK  
(PLL-ON)  
ta_max  
Data  
D0  
D1  
tsu_min  
Figure 34. DDR Source Synchronous Center Aligned Clocking  
SDR Cycle Time  
ERCLK  
(PLL-ON)  
data  
Figure 35. SDR Edge Aligned Clocking  
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(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
BUS MATCHING OPERATION  
portisx40andtheoutputportisx20,thentwodatareadsfromafullqueuewill  
BusMatchingoperationbetweentheinputportandoutputportisavailable. berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the  
Duringamasterresetofthemulti-queuethestateofthethreesetuppins,BM EmptyflagandAlmostEmptyflagoperationsarealwaysbasedonwritesand  
[3:0](BusMatching),determinetheinputandoutputportbuswidthsasshown readsofdatawidthsdeterminedbythereadport.Forexample,iftheinputport  
inTable16,“BusMatchingConfigurations”.20bitwordsand40bitwordscan isx20andtheoutputportisx40,twowriteoperationswillberequiredtocause  
bewrittenintoandreadfromtheQueues.Whenwritingtoorreadingfromthe the Empty flag (EF) of an empty queue to go HIGH (queue is not empty).  
multi-queueinabusmatchingmode,thedeviceordersdataina“LittleEndian”  
format. See Figure 36,Bus MatchingByte Arrangementfordetails.  
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput  
port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput  
TheFullflagandAlmostFullflagoperationis always basedonwrites and portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe  
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput outputportsize).  
TABLE16—BUS-MATCHINGCONFIGURATIONS  
BM3  
BM2  
Write  
Port  
Read  
Port  
(IDR) (ODR) BM1 BM0  
PAE Default  
PAF Default  
D-16  
D-16  
D-16  
D-16  
D-16  
D-32  
D-32  
D-32  
D-16  
D-32  
D-32  
D-32  
D-16  
D-32  
D-32  
D-64  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DDR x40  
DDR x40  
DDR x40  
DDR x40  
DDR x20  
DDR x20  
DDR x20  
DDR x20  
SDR x40  
SDR x40  
SDR x40  
SDR x40  
SDR x20  
SDR x20  
SDR x20  
SDR x20  
DDR x40  
DDR x20  
SDR x40  
SDR x20  
DDR x40  
DDR x20  
SDR x40  
SDR x20  
DDR x40  
DDR x20  
SDR x40  
SDR x20  
DDR x40  
DDR x20  
SDR x40  
SDR x20  
16  
16  
16  
16  
16  
32  
32  
32  
16  
32  
32  
32  
16  
32  
32  
64  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
D39-D30  
D29-D20  
D19-D10  
D9-D0  
BYTE ORDER ON INPUT PORT:  
Write to Queue  
A
B
C
D
Q39-Q30  
Q29-Q20  
Q19-Q10  
Q9-Q0  
BYTE ORDER ON OUTPUT PORT:  
A
B
C
D
Read from Queue  
Write to Queue  
(a) x40 INPUT to x40 OUTPUT  
D39-D30  
D29-D20  
D19-D10  
D9-D0  
A
B
C
D
Q39-Q30  
Q29-Q20  
Q19-Q10  
Q9-Q0  
1st: Read from Queue  
2nd: Read from Queue  
A
B
Q39-Q30  
Q29-Q20  
Q19-Q10  
Q9-Q0  
C
D
(b) x40 INPUT to x20 OUTPUT  
D39-D30  
Q39-Q30  
D29-D20  
Q29-Q20  
D19-D10  
D9-D0  
BYTE ORDER ON INPUT PORT:  
Write to Queue  
A
B
Q19-Q10  
Q9-Q0  
Read from Queue  
A
B
(c) x20 INPUT to x20 OUTPUT  
BYTE ORDER ON OUTPUT PORT:  
D39-D30  
D39-D30  
D29-D20  
D29-D20  
D19-D10  
D9-D0  
A
1st: Write to Queue  
2nd: Write to Queue  
B
D19-D10  
D9-D0  
C
D
Q39-Q30  
Q29-Q20  
Q19-Q10  
Q9-Q0  
D
B
C
A
Read from Queue  
(d) x20 INPUT to x40 OUTPUT  
6724 drw28  
NOTES:  
1. Please refer to Table 16, Bus-Matching set-up for details.  
2. Data bits not used in this configuration.  
Figure 36. Bus-Matching Byte Arrangement  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tRS  
MRS  
t
RSS  
RSS  
WEN  
REN  
t
tRSR  
SENI  
tRSS  
FSTR,  
ESTR  
tRSS  
WADEN,  
RADEN  
t
RSS  
RSS  
RSS  
ID0, ID1,  
ID2  
t
BM[3:0]  
FM  
t
HIGH = Polled mode  
LOW = Strobed (Direct)  
tRSS  
HIGH = Master Device  
LOW = Slave Device  
MAST  
DFM  
t
RSS  
RSS  
HIGH = Queue Programming  
LOW = Serial Programming  
t
QSEL [2:0]  
See Table 2, for setting the Queue Programming  
t
t
t
t
RSF  
HIGH-Z if Slave Device  
FF  
LOGIC "0" if Master Device  
RSF  
RSF  
RSF  
HIGH-Z if Slave Device  
EF  
PAF  
PAE  
LOGIC "0" if Master Device  
LOGIC "1" if Master Device  
HIGH-Z if Slave Device  
HIGH-Z if Slave Device  
LOGIC "0" if Master Device  
t
RSF  
RSF  
LOGIC "1" if Master Device  
HIGH-Z if Slave Device  
PAFn  
PAEn  
t
HIGH-Z if Slave Device  
LOGIC "0" if Master Device  
tRSF  
LOGIC "1" if OE is LOW and device is Master  
HIGH-Z if OE is HIGH or Device is Slave  
Qn  
6724 drw46  
NOTE:  
1. OE can toggle during this period.  
Figure 37. Master Reset  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Master Reset  
Default Mode  
DFM = 0  
MRS  
MRS  
MRS  
DFM  
DFM  
DFM  
MQ2  
MQ1  
MQn  
SENI MasterSENO  
ID=‘000’  
Serial Loading  
Complete  
SENI  
SENO  
SO  
SENI  
SENO  
SO  
Serial Enable  
Serial Input  
SI  
SO  
SI  
SI  
SCLK  
SCLK  
SCLK  
6724 drw50  
Serial Clock  
Figure 40. Serial Port Connection for Serial Programming  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
*A*  
*B*  
*C*  
*D*  
*E*  
*F*  
*G*  
RCLK  
tENH  
tENS  
REN  
RCS  
tAH  
RDADD  
Y
tQH  
RADEN  
Q[39:0]  
t
A
tA  
tA  
tA  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
X8  
X9  
X10  
tREF  
tREF  
tREF  
EF  
tRAE  
tRAE  
PAE  
6724 drw56a  
NOTES:  
1. On Cycle 2, Queue Y is addressed to read data from.  
2. On Cycle 6, Queue Y data is available on the Read bus  
3. On Cycle 5, EF and PAE flags have updated to give the status for Queue Y  
4. Previous Data from Queue X will be read during queue switch until 3 cycle latency from queue switch, plus 1 cycle Read delay of the first word in Queue Y is completed.  
5. REN is high for falling edge of cycle 3 and all of cycle 4 which means Words X6-X8 will not be available for read operation  
Figure 47. DDR Read Operation, Read Queue Select, EF & PAE Flag Operation  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
*A*  
*B*  
*C*  
*D*  
*E*  
*F*  
*G*  
*H*  
*I*  
*J*  
WCLK  
WEN  
2
1
tENH  
tENS  
tAS  
tAH  
tAS  
tAH  
WRADD  
D1  
Q5  
D1 Q9  
tQS  
tQH  
tQH  
tQS  
WADEN  
Din  
tDS  
tDH  
WD-m  
D1 Q5  
tWAF  
tWAF  
tAFLZ  
HIGH-Z  
PAF  
(Device 1)  
tFFHZ  
PAF  
(Device 2)  
6724 drw66  
Cycle:  
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.  
*B* No write occurs, WEN is HIGH.  
*C* No write occurs, WEN is HIGH.  
*D* No write occurs, WEN is HIGH.  
*E* Word, Wd-m is written into Q5 causing the PAF flag to go from HIGH to LOW. The flag latency is 3 WCLK cycles + tWAF.  
*F* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.  
*G* The PAF flag goes LOW based on the write 2 cycles earlier.  
*H* No write occurs, WEN is HIGH.  
*I* The PAF flag goes HIGH due to the queue switch to Q9.  
Figure 53. Almost Full Flag Timing and Queue Switch  
tCLKL  
tCLKL  
WCLK  
WEN  
PAF  
tENS  
tENH  
tWAF  
tWAF  
D - (m+1) words in Queue(2)  
D-(m+1) words  
in Queue  
D - m words in Queue  
tSKEW2  
RCLK  
tENS  
tENH  
6724 drw67  
REN  
NOTE:  
1. The waveform shows the PAF flag operation when no queue switch occurs and a queue is selected on both the write and read ports is being written to then read  
from at the almost full boundary.  
2. Flag Latencies:  
Assertion: 2*WCLK + tWAF  
De-assertion: tSKEW2 + WCLK + tWAF  
3. If tSKEW2 is violated there will be one extra WCLK cycle.  
Figure 54. Almost Full Flag Timing  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLKL  
tCLKH  
WCLK  
tENH  
tENS  
WEN  
PAE  
n+1 words in Queue  
SKEW2  
n+2 words in Queue  
n+1 words in Queue  
tRAE  
t
tRAE  
RCLK  
1
2
tENS  
tENH  
6724 drw69  
REN  
NOTE:  
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read  
from at the almost empty boundary.  
Flag Latencies:  
2. Assertion: 2*RCLK + tRAE  
De-assertion: tSKEW2 + RCLK + tRAE  
3. If tSKEW2 is violated there will be one extra RCLK cycle.  
Figure 55. Almost Empty Flag Timing  
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(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
RCLK  
tQS  
tQH  
t
QS  
tQS  
Status Word 0  
t
QH  
tQH  
Device 1  
Device 1  
Device 1  
Status Word 2  
Status Word 3  
001xxx10  
001xxx11  
001xxx00  
RDADD  
ESTR  
tSTS  
tSTH  
tSTS  
tSTH  
tPAE  
tPAE  
tPAE  
Device 1 Status Word 2  
ENH  
Device 1 Status Word 3 Device 1 Status Word  
0
PAEn  
tENS  
tENH  
tENS  
t
RADEN  
6724 drw70  
NOTES:  
1. Status words can be selected on consecutive cycles.  
2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.  
3. There is a latency of 2 RCLK for the PAEn bus to switch.  
Figure 56. PAEn - Direct Mode - Status Word Selection  
WCLK  
tQS  
tQH  
t
QS  
tQS  
Status Word 2  
t
QH  
tQH  
Device 1  
Device 1  
Device 1  
Status Word 1  
Status Word 3  
001xxx01  
001xxx11  
001xxx10  
WRADD  
FSTR  
tSTS  
tSTH  
tSTS  
tSTH  
tPAF  
tPAF  
tPAF  
PAFn  
Device 1 Status Word 1  
ENH  
Device 1 Status Word 3  
Device 1 Status Word  
2
tENS  
tENH  
tENS  
t
WADEN  
6724 drw71  
NOTES:  
1. Status words can be selected on consecutive cycles.  
2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.  
3. There is a latency of 2 WCLK for the PAFn bus to switch.  
Figure 57. PAFn - Direct Mode - Status Word Selection  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
*A*  
*B*  
1
*C*  
2
*D*  
3
*E*  
*F*  
*G*  
*H*  
WCLK  
WADEN  
FSTR  
tQS  
tQH  
tQS  
tQH  
tSTS  
tSTH  
tENS  
tENH  
WEN  
tAS  
tAH  
tAH  
tAS  
tAS  
tAH  
D4 SW 2  
D3Q8  
011 01000  
WRADD  
Dn  
D5Q24  
101 11000  
tDH  
100 00100  
t
DH  
tDH  
t
DS  
t
DS  
tDS  
Wp+3  
Wp  
Wp+1  
Wp+2  
Wn  
D5Q24  
Writes to Previous Q  
tSKEW3  
RCLK  
RADEN  
ESTR  
tQS  
tQH  
tSTS  
t
STH  
t
ENS  
tENH  
REN  
tAH  
tAS  
tAS  
tAH  
RDADD  
D5 SW 3  
D5Q24  
101 11000  
101 00011  
tA  
t
A
tA  
t
A
tA  
Wy+1  
D5 Q24  
Wy  
D5 Q24  
Wy+2  
D5 Q24  
Wy+3  
D5 Q24  
Device 5 -Qn  
Wa  
D5 Q17  
Wa+1  
D5 Q17  
Previous value loaded on to PAE bus  
Prev PAEn  
tPAEHZ  
tPAE  
tPAEZL  
xxxx xxx0  
D5 SW 3  
xxxx xxx1  
D5 SW 3  
Device 5 PAEn  
xxxx xxx0  
D5 SW 3  
xxxx xxx1  
D5 SW 3  
Previous value loaded on to PAE bus  
D5 Q17 Status  
Bus PAEn  
t
RAE  
tRAE  
tRAE  
D5 Q24  
status  
Device 5 PAE  
6724 drw72  
*FF*  
*AA*  
*BB*  
*CC*  
*DD*  
*GG*  
*EE*  
Cycle:  
*A* Queue 24 of Device 5 is selected for write operations.  
Word, Wp is written into the previously selected queue.  
*AA* Queue 24 of Device 5 is selected for read operations.  
A status word from another device has control of the PAEn bus.  
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.  
*B* Word Wp+1 is written into the previously selected queue.  
*BB* Current Word is kept on the output bus since REN is HIGH.  
*C* Word Wp+2 is written into the previously selected queue.  
*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,  
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).  
*DD* Status word 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency  
before the PAEn bus changes to the new selection.  
*E* Queue 8 of Device 3 is selected for write operations.  
Word Wn+1 is written into Q24 of D5.  
*EE* Word, Wy+1 is read from Q24 of D5.  
*F* No writes occur.  
*FF* Word, Wy+2 is read from Q24 of D5.  
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and status word 4 is placed onto the outputs. The device of the previously selected  
status word now places its PAEn outputs into High-Impedance to prevent bus contention.  
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].  
*G* Status word 3 of device 4 is selected on the write port for the PAFn bus.  
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.  
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.  
Figure 58. PAEn - Direct Mode, Flag Operation  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
*A*  
*B*  
*C*  
*D*  
*E*  
*F*  
*G*  
*H*  
*I*  
RCLK  
tQH  
tQS  
tQS  
tQH  
RADEN  
tSTH  
tSTS  
ESTR  
REN  
tAS  
tAH  
tAH  
tAH  
tAS  
tAS  
D7 SW 0  
RDADD  
D6Q2  
D0Q31  
110 00010  
111 00000  
000 11111  
OE  
t
A
tA  
tA  
tA  
tOLZ  
Qout  
WX  
WX +1  
WD - M + 2  
W0  
WD-M+1  
D0 Q31  
D0 Q31  
D6 Q2  
tSKEW3  
WCLK  
FSTR  
1
2
3
tSTS  
tSTH  
tAS  
tAH  
tAS  
tAH  
WRADD  
D0 quad3  
000 00011  
D0 Q31  
tENS  
tENH  
WEN  
tQS  
tQH  
WADEN  
Din  
t
DS  
t
DH  
tDS  
t
DH  
tDS  
tDH  
W
y+1  
Wy+2  
Word W  
y
D0 Q31  
D0 Q31  
D0 Q31  
tPAFLZ  
tPAF  
tPAF  
Device 0 PAFn  
0xxx xxxx  
0xxx xxxx  
1xxx xxxx  
1xxx xxxx  
0xxx xxxx  
0xxx xxxx  
D0SW3  
D0SW3  
D0SW3  
D0SW3  
D0SW3  
HIGH-Z  
DXSW y  
D0SW3  
Bus PAFn  
tPAFHZ  
HIGH-Z  
DXSW y  
Prev.  
PAFn  
tPAFLZ  
tWAF  
Device 0  
HIGH - Z  
6724 drw73  
PAF  
*AA*  
*BB*  
*CC*  
*DD*  
*EE*  
*FF*  
*GG*  
Cycle:  
*A* Queue 31 of device 0 is selected for read operations.  
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.  
*AA* Status word 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected status word, Quad Y of device X.  
*B* No read operation.  
*BB* Queue 31 of device 0 is selected on the write port.  
*CC* PAFn continues to show status of Quad4 D0.  
The PAFn bus is updated with the status word selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.  
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.  
*DD* No write operation.  
*E* No read operations occur, REN is HIGH.  
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.  
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.  
Word, Wy is written into D0 Q31.  
*F* Queue 2 of Device 6 is selected for read operations.  
*FF* Word, Wy+1 is written into D0 Q31.  
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.  
Word, Wy+2 is written into D0 Q31.  
*H* No read operation.  
Figure 59. PAFn - Direct Mode, Flag Operation  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
APF  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SENI  
SCLK  
SI  
FXI  
EXI  
WCLK  
RCLK  
WEN  
REN  
RCS  
WCS  
WADEN  
RADEN  
FF  
EF  
Slave Device  
ID = 100  
FSTR  
ESTR  
FSYNC  
ESYNC  
Q[39:0]  
RDADD[7:0]  
PAEn  
D[39:0]  
WRADD[7:0]  
PAFn  
PAF  
PAE  
VCC  
GND  
MAST  
ID2  
GND  
GND  
ID1  
ID0  
SENO  
SO  
SI  
FXO  
FXI  
EXO  
EXI  
SENI  
SCLK  
WCLK  
WEN  
RCLK  
REN  
RCS  
WCS  
RADEN  
WADEN  
EF  
FF  
FSTR  
Master Device  
ID = 000  
ESTR  
FSYNC  
ESYNC  
Q[39:0]  
RDADD[7:0]  
PAEn  
D[39:0]  
WRADD[7:0]  
PAFn  
PAE  
PAF  
MAST  
ID2  
VCC  
GND  
GND  
GND  
ID1  
ID0  
FXO  
EXO  
SENO  
SO  
6724 drw75  
NOTE:  
1. ID2 MUST be unique between the devices.  
Figure 61. Connecting two 10G MQ 128Q devices in Expansion Mode  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SENI  
SCLK  
SI  
FXI  
EXI  
WCLK  
WEN  
WCS  
RCLK  
REN  
RCS  
GND  
GND  
WADEN  
FF  
RADEN  
EF  
Slave Device  
ID = 110  
FSTR  
ESTR  
FSYNC  
FM  
ESYNC  
WRADD[7]  
D[39:0]  
Q[39:0]  
RDADD[6:0]  
PAEn  
WRADD[6:0]  
PAFn  
PAF  
PAE  
MAST  
ID2  
GND  
VCC  
VCC  
GND  
RDADD[7]  
EXO  
ID1  
ID0  
SENO  
SENI  
SO  
SI  
FXO  
FXI  
EXI  
SCLK  
WCLK  
WEN  
RCLK  
REN  
RCS  
GND  
WCS  
GND  
RADEN  
WADEN  
EF  
FF  
ESTR  
FSTR  
Slave Device  
ID = 101  
ESYNC  
FSYNC  
FM  
D[39:0]  
Q[39:0]  
RDADD[6:0]  
PAEn  
WRADD[6:0]  
PAFn  
PAF  
PAE  
RDADD[7]  
WRADD[7]  
GND  
VCC  
GND  
VCC  
MAST  
ID2  
ID1  
ID0  
FXO  
EXO  
SENO  
SO  
SI  
SENI  
FXI  
EXI  
SCLK  
WCLK  
WEN  
RCLK  
REN  
RCS  
GND  
GND  
WCS  
RADEN  
WADEN  
FF  
EF  
FSTR  
ESTR  
Master Device  
ID = 000  
FSYNC  
FM  
ESYNC  
Q[39:0]  
D[39:0]  
WRADD[6:0]  
PAFn  
RDADD[6:0]  
PAEn  
PAE  
PAF  
WRADD[7]  
RDADD[7]  
EXO  
VCC  
GND  
GND  
GND  
MAST  
ID2  
ID1  
ID0  
FXO  
SENO  
SO  
6724 drw75a  
Figure 62. Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TheStandardJTAGinterfaceconsistsoffourbasicelements:  
JTAGINTERFACE  
•
•
•
•
Test Access Port (TAP)  
TAPcontroller  
Instruction Register (IR)  
Data Register Port (DR)  
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to  
support the JTAG boundary scan interface. The IDT72P51767/72P51777  
incorporatesthenecessarytapcontrollerandmodifiedpadcellstoimplement  
theJTAGfacility.  
Thefollowingsections provideabriefdescriptionofeachelement.Fora  
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage  
programfilesforthesedevices.  
The Figure belowshows the standardBoundary-ScanArchitecture  
Mux  
DeviceID Reg.  
Boundary Scan Reg.  
Bypass Reg.  
TDO  
TDI  
T
A
clkDR, ShiftDR  
UpdateDR  
P
TMS  
TAP  
TCLK  
Cont-  
roller  
TRST  
Instruction Decode  
clklR, ShiftlR  
UpdatelR  
Instruction Register  
Control Signals  
6724 drw76  
Figure 63. Boundary Scan Architecture  
THETAPCONTROLLER  
TEST ACCESS PORT (TAP)  
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto  
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction  
andDataRegisters forcaptureandupdateofdata.  
The Tap interface is a general-purpose port that provides access to the  
internaloftheprocessor.Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)  
and one output port (TDO).  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
1
Test-Logic  
Reset  
0
1
0
1
1
Run-Test/  
Idle  
Select-  
DR-Scan  
Select-  
IR-Scan  
0
0
1
1
Capture-DR  
Capture-IR  
0
0
0
0
Shift-IR  
Shift-DR  
1
1
1
1
Input = TMS  
Exit1-IR  
Exit1-DR  
0
0
0
0
Pause-IR  
Pause-DR  
1
1
Exit2-IR  
Exit2-DR  
0
0
1
1
Update-IR  
Update-DR  
1
0
1
0
6724 drw77  
NOTES:  
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.  
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).  
3. TAP controller must be reset before normal Queue operations can begin.  
Figure 64. TAP Controller State Diagram  
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction  
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The  
lasttwosignificantbits arealways requiredtobe“01”.  
Shift-IR In this controller state, the instruction register gets connected  
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge  
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction  
register.  
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.  
1149.1)forthefullstatediagram.  
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe  
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression  
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence  
overthe Queue andmustbe resetafterpowerupofthe device. See TRST  
descriptionformoredetailsonTAPcontrollerreset.  
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-  
IRstateorUpdate-IRstateismade.  
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction  
registertobetemporarilyhalted.  
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-  
IRstateorUpdate-IRstateismade.  
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris  
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof  
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.  
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata  
registersselectedbythecurrentinstructionontherisingedgeofTCK.  
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These  
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand  
Update-IRstatesintheInstructionpath.  
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling  
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned  
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-  
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive  
times. This is the reasonwhythe TestReset(TRST)pinis optional.  
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif  
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself  
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic  
intheICis idles otherwise.  
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe  
DataPathortheSelect-IR-Scanstateismade.  
Select-IR-Scan This is a controller state where the decision to enter the  
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate  
otherwise.  
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COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
JTAG INSTRUCTION REGISTER  
THE INSTRUCTION REGISTER  
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice  
whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto  
performthefollowing:  
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe  
processor at the rising edge of TCLK.  
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata  
registertobeaccessed,orboth.Theinstructionshiftedintotheregisterislatched  
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-  
IRstate.  
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis  
current.Theothertestdataregistersshouldnotinterferewithchip  
operationandtheselecteddataregister.  
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween  
Theinstructionregistermustcontain4bitinstructionregister-basedcells  
whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe  
serialoutputstheyaretheleastsignificantbits.  
TDI and TDO during data register scanning.  
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode  
16differentpossibleinstructions.Instructionsaredecodedasfollows.  
TESTDATAREGISTER  
Hex  
Value  
00  
01  
02  
03  
0F  
Instruction  
Function  
TheTestDataregistercontainsthreetestdataregisters:theBypass,the  
Boundary Scan register and Device ID register.  
Theseregistersareconnectedinparallelbetweenacommonserialinput  
andacommonserialdataoutput.  
Thefollowingsections provideabriefdescriptionofeachelement.Fora  
completedescription,refertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
EXTEST  
SAMPLE/PRELOAD  
IDCODE  
HIGH-IMPEDANCE  
BYPASS  
SelectBoundaryScanRegister  
SelectBoundaryScanRegister  
SelectChipIdentificationdataregister  
JTAG  
SelectBypassRegister  
JTAG INSTRUCTION REGISTER DECODING  
TEST BYPASS REGISTER  
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI  
toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.  
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage  
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in  
theCapture-DRstate.  
Thefollowingsectionsprovideabriefdescriptionofeachinstruction.For  
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification  
(IEEEStd. 1149.1-1990).  
EXTEST  
The operation of the bypass register should not have any effect on the  
operationofthedeviceinresponsetotheBYPASSinstruction.  
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-  
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI  
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto  
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip  
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof  
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts  
andoflogicclusterfunction.  
THE BOUNDARY-SCAN REGISTER  
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread  
outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart  
oftheIEEE1149.1-1990StandardJTAGImplementation.  
THE DEVICE IDENTIFICATION REGISTER  
IDCODE  
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto  
specify the manufacturer, part number and version of the processor to be  
determinedthroughtheTAPinresponsetotheIDCODEinstruction.  
IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis  
droppedinthe11-bitManufacturerIDfield.  
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode  
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween  
TDI and TDO. The device identification register is a 32-bit shift register  
containinginformationregardingtheICmanufacturer,devicetype,andversion  
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe  
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe  
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe  
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise  
movingtotheTest-Logic-Resetstate.  
For the IDT72P51767/72P51777, the Part Number field contains the  
followingvalues:  
Device  
Part# Field (HEX)  
IDT72P51767  
IDT72P51777  
048f  
048e  
SAMPLE/PRELOAD  
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina  
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected  
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan  
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata  
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata  
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.  
31(MSb)  
28 27  
12 11  
1 0(LSB)  
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)  
0X0  
0X33  
1
JTAG DEVICE IDENTIFICATION REGISTER  
JANUARY18,2006  
85  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128QUEUES)40BITWIDECONFIGURATION5,898,240 and11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
HIGH-IMPEDANCE  
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state  
BYPASS  
The required BYPASS instruction allows the IC to remain in a normal  
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected  
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be  
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof  
toTDOwithoutaffectingtheconditionoftheICoutputs.  
theIC.  
JANUARY18,2006  
86  
IDT72P51767/72P517771.8V,MULTI-QUEUEFLOW-CONTROLDEVICES  
(128 QUEUES) 40BITWIDECONFIGURATION 5,898,240 and 11,796,480 bits  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tTCK  
t4  
t1  
t2  
TCK  
t3  
TDI/  
TMS  
tDS  
tDH  
TDO  
TDO  
tDO  
t6  
TRST  
6724 drw78  
Notes to diagram:  
t1 = tTCKLOW  
t2 = tTCKHIGH  
t5  
t3 = tTCKFALL  
t4 = tTCKRISE  
t5 = tRST (reset pulse width)  
t6 = tRSR (reset recovery)  
Figure 65. Standard JTAG Timing  
JTAG  
ACELECTRICALCHARACTERISTICS  
(VDD = 2.5V ± 5%; Tcase = 0°C to +85°C)  
Parameter  
Symbol  
Test  
Conditions  
IDT72P51767  
IDT72P51777  
Min. Max. Units  
JTAGClockInputPeriod tTCK  
-
-
-
-
-
-
-
100  
40  
40  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SYSTEMINTERFACEPARAMETERS  
IDT72P51767  
IDT72P51777  
JTAGClockHIGH  
JTAGClockLow  
tTCKHIGH  
tTCKLOW  
tTCKRISE  
tTCKFALL  
tRST  
-
5(1)  
5(1)  
-
Parameter  
Symbol Test Conditions Min. Max. Units  
JTAGClockRiseTime  
JTAGClockFallTime  
JTAGReset  
(1)  
DataOutput  
tDO  
-
20  
-
ns  
ns  
ns  
-
(1)  
DataOutputHold tDOH  
0
50  
50  
DataInput  
tDS  
tDH  
trise=3ns  
tfall=3ns  
10  
10  
-
-
JTAG Reset Recovery  
tRSR  
-
NOTE:  
1. Guaranteed by design.  
NOTE:  
1. 50pf loading on external output signals.  
JANUARY18,2006  
87  
ORDERINGINFORMATION  
X
IDT  
XXXXX  
X
XX  
X
X
Process /  
Temperature  
Range  
Device Type  
Power  
Speed  
Package  
BLANK  
I(1)  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
Green  
G
Ball Grid Array (BGA, BB376-1)  
BB  
Clock Cycle Time (tCLK  
Speed in Nanoseconds  
)
6
7-5  
Commercial Only  
Commercial and Industrial  
Low Power  
L
72P51767 5,898,240 bits 10G DDR Multi-Queue Flow-Control Device 1.8V  
72P51777 11,796,480 bits 10G DDR Multi-Queue Flow-Control Device 1.8V  
6724 drw79  
NOTES:  
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order.  
2. Green parts are available. For specific speeds contact your local sales office.  
DATASHEETDOCUMENTHISTORY  
01/18/2006  
pgs. 1, 17, 19, 20, 30, and 31.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
408-360-1533  
email:Flow-Controlhelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
88  

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