IDT72V05L25JI [IDT]
3.3 VOLT CMOS ASYNCHRONOUS FIFO; 3.3伏的CMOS异步FIFO
| 型号： | IDT72V05L25JI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS ASYNCHRONOUS FIFO |
| 文件： | 总12页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
IDT72V01, IDT72V02
IDT72V03, IDT72V04
IDT72V05, IDT72V06
8,192 x 9, 16,384 x 9
FEATURES:
DESCRIPTION:
• 3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/
7205/7206family
• 512 x 9 organization (72V01)
• 1,024 x 9 organization (72V02)
• 2,048 x 9 organization (72V03)
• 4,096 X 9 organization (72V04)
• 8,192 x 9 organization (72V05)
• 16,384 X 9 organization (72V06)
• Functionally compatible with 720x family
• Low-power consumption
— Active: 180 mW (max.)
— Power-down: 18 mW (max.)
• 15 ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO
memoriesthatoperateatapowersupplyvoltage(Vcc)between3.0Vand3.6V.
Theirarchitecture,functionaloperationandpinassignmentsareidenticalto
those ofthe IDT7201/7202/7203/7204/7205/7206. These devices loadand
emptydataonafirst-in/first-outbasis.TheyuseFullandEmptyflagstoprevent
data overflow and underflow and expansion logic to allow for unlimited
expansioncapabilityinbothwordsize anddepth.
The reads and writes are internally sequential through the use of ring
pointers,withnoaddressinformationrequiredtoloadandunloaddata.Data
istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead
(R)pins. The devices have a maximumdata access time as fastas 25ns.
Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits
attheuser’soption.Thisfeatureisespeciallyusefulindatacommunications
applicationswhereitisnecessarytouseaparitybitfortransmission/reception
errorchecking.TheyalsofeatureaRetransmit(RT)capabilitythatallowsfor
resetofthereadpointertoitsinitialpositionwhenRTispulsedLOWtoallowfor
retransmissionfromthebeginningofdata.AHalf-FullFlagisavailableinthe
singledevicemodeandwidthexpansionmodes.
• Available in 32-pin PLCC
•
Industrial temperature range (–40
°
C to +85
°
C) is available
TheseFIFOsarefabricatedusingIDT’shigh-speedCMOStechnology.It
hasbeendesignedforthoseapplicationsrequiringasynchronousandsimul-
taneousread/writesinmultiprocessingandratebufferapplications.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D0-D8)
WRITE
CONTROL
W
RAM
ARRAY
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
WRITE
POINTER
READ
POINTER
THREE-
STATE
BUFFERS
RS
DATA OUTPUTS
READ
CONTROL
(Q0-Q8)
RESET
LOGIC
R
FLAG
LOGIC
EF
FF
FL/RT
EXPANSION
LOGIC
XI
XO/HF
3033 drw 01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
MAY 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3033/3
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTEMAXIMUMRATINGS
PINCONFIGURATION
Symbol
Rating
TerminalVoltage
Com'l & Ind'l
Unit
VTERM
–0.5 to +7.0
V
INDEX
with Respect to GND
StorageTemperature
DCOutputCurrent
TSTG
IOUT
–55to+125
–50to+50
°C
mA
4
3
2
32 31 30
1
NOTE:
D2
5
29
28
27
26
25
24
23
22
21
D6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
D1
6
D7
D0
7
NC
XI
8
FL/RT
RS
FF
9
EF
Q0
10
11
12
13
RECOMMENDEDDCOPERATING
CONDITIONS
Q1
XO/HF
NC
Q7
Symbol
Rating
SupplyVoltage
Min. Typ. Max.
Unit
V
Q2
Q6
VCC
3.0
0
3.3
0
3.6
0
14 15 16 17 18 19 20
GND SupplyVoltage
V
(1)
VIH
InputHighVoltage
2.0
—
0
—
—
—
—
VCC+0.5
0.8
V
(2)
VIL
TA
InputLowVoltage
V
3033 drw 02b
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
70
°C
°C
TA
–40
85
NOTES:
PLCC (J32-1, order code: J)
TOP VIEW
1. For RT/RS/XI input, VIH = 2.6V (commercial).
For RT/RS/XI input, VIH = 2.8V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = –40°C to +85°C)
IDT72V01
IDT72V02
IDT72V03
IDT72V04
IDT72V05
IDT72V06
Commercial & Industrial(1)
tA = 15, 25, 35 ns
Commercial & Industrial(1)
tA = 15, 25, 35 ns
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Max.
1
Min.
–1
Max.
1
Unit
(2)
ILI
µ A
µ A
V
(3)
ILO
–10
2.4
—
10
—
0.4
60
5
–10
2.4
—
10
—
0.4
75
5
VOH
Output Logic “1” Voltage IOH = –2mA
Output Logic “0” Voltage IOL = 8mA
Active Power Supply Current
VOL
V
ICC1(4,5)
ICC2(4,6)
—
—
mA
mA
StandbyCurrent(R=W=RS=FL/RT=VIH)
—
—
NOTES:
1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. All Inputs = VCC - 0.2V or GND + 0.2V.
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
Parameter(1)
InputCapacitance
OutputCapacitance
Condition
Max.
Unit
pF
CIN
VIN = 0V
8
8
COUT
VOUT = 0V
pF
NOTE:
1. Characterized values, not currently tested.
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
(1)
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = –40°C to +85°C)
(2)
Commercial
IDT72V01L15
Com'l and Ind'l
IDT72V01L25
Commercial
IDT72V01L35
IDT72V02L15
IDT72V03L15
IDT72V04L15
IDT72V05L15
IDT72V06L15
IDT72V02L25
IDT72V03L25
IDT72V04L25
IDT72V05L25
IDT72V06L25
IDT72V02L35
IDT72V03L35
IDT72V04L35
IDT72V05L35
IDT72V06L35
Symbol
fS
Parameter
Min.
Max.
40
—
15
Min.
—
35
—
10
25
3
Max.
Min.
—
45
—
10
35
3
Max.
22.2
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
45
45
45
30
30
—
30
30
45
45
—
35
35
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ShiftFrequency
ReadCycleTime
AccessTime
—
25
—
10
15
3
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
35
35
35
25
25
—
25
25
35
35
—
25
25
—
—
—
tRC
tA
tRR
ReadRecoveryTime
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
(3)
tRPW
tRLZ
tWLZ
tDV
ReadPulseWidth
(4)
Read Pulse Low to Data Bus at Low Z
WritePulseHightoDataBusatLowZ
DataValidfromReadPulseHigh
(4,5)
5
5
5
5
5
5
(4)
tRHZ
tWC
ReadPulseHightoDataBus atHighZ
WriteCycleTime
—
25
15
10
11
0
—
35
25
10
15
0
—
45
35
10
18
0
(3)
tWPW
tWR
WritePulseWidth
WriteRecoveryTime
DataSetupTime
DataHoldTime
tDS
tDH
tRSC
tRS
ResetCycleTime
ResetPulseWidth
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
35
25
25
10
35
25
25
10
—
—
—
—
—
25
—
—
—
—
25
—
—
25
10
10
45
35
35
10
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
—
—
35
10
10
(3)
tRSS
tRSR
tRTC
tRT
ResetSetupTime(4)
ResetRecoveryTime
RetransmitCycleTime
RetransmitPulseWidth
RetransmitSetupTime(4)
(3)
tRTS
tRTR
tEFL
tHFH,FFH
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
RetransmitRecoveryTime
ResettoEmptyFlagLow
ResettoHalf-FullandFullFlagHigh
RetransmitLowtoFlagsValid
Read Low to Empty Flag Low
ReadHightoFullFlagHigh
ReadPulseWidthafterEFHigh
WriteHightoEmptyFlagHigh
WriteLowtoFullFlagLow
WriteLowtoHalf-FullFlagLow
ReadHightoHalf-FullFlagHigh
WritePulseWidthafterFFHigh
Read/WritetoXOLow
—
15
15
—
—
—
Read/WritetoXOHigh
(3)
XI PulseWidth
tXIR
XI Recovery Time
XI SetupTime
tXIS
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for the 25ns speed grade is available as a standard device.
All other speed grades are available by special order.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
3.3V
330Ω
D.U.T.
30pF*
ACTESTCONDITIONS
510Ω
InputPulseLevels
GND to 3.0V
5ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
3033 drw 03
1.5V
or equivalent circuit
1.5V
Figure 1. Output Load
* Includes scope and jig capacitances.
SeeFigure1
3
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNALDESCRIPTIONS
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
groundedtoindicatethatitisthefirstloaded(seeOperatingModes).IntheSingle
DeviceMode,thispinactsastheretransmitinput. TheSingleDeviceModeis
initiated by grounding the Expansion In (XI).
TheseFIFOscanbemadetoretransmitdatawhentheRetransmitEnable
control(RT)inputispulsedLOW. Aretransmitoperationwillsettheinternalread
pointertothefirstlocationandwillnotaffectthewritepointer.ReadEnable(R)
andWriteEnable(W)mustbeintheHIGHstateduringretransmit.Thisfeature
is useful when less than 512/1,024/2,048/4,096/8,192/16,384 writes are
performedbetweenresets.Theretransmitfeatureisnotcompatiblewiththe
DepthExpansionModeandwillaffecttheHalf-FullFlag(HF),dependingon
therelativelocationsofthereadandwritepointers.
INPUTS:
DATA IN (D0 – D8)
Datainputsfor9-bitwidedata.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputis takentoaLOW
state. During reset, both internal read and write pointers are set to the first
location. Aresetisrequiredafterpowerupbeforeawriteoperationcantake
place. Both the Read Enable (R) and Write Enable (W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., tRSS
before the rising edge of RS ) and should not change until tRSR after
the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after
Reset (RS).
EXPANSION IN (XI)
Thisinputisadual-purposepin.ExpansionIn(XI)isgroundedtoindicate
an operation in the single device mode. Expansion In (XI) is connected to
ExpansionOut(XO)ofthe previous device inthe DepthExpansionorDaisy
Chain Mode.
WRITE ENABLE (W)
AwritecycleisinitiatedonthefallingedgeofthisinputiftheFullFlag(FF)
isnotset. Datasetupandholdtimesmustbeadheredtowithrespecttotherising
edgeoftheWriteEnable(W). DataisstoredintheRAMarraysequentiallyand
independentlyofanyongoingreadoperation.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesettoLOWandwillremainsetuntilthe
differencebetweenthewritepointerandreadpointeris less thanorequalto
onehalfofthetotalmemoryofthedevice. TheHalf-FullFlag(HF)isthenreset
by the rising edge of the read operation.
OUTPUTS:
FULL FLAG (FF)
TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
writepointerisonelocationlessthanthereadpointer,indicatingthatthedevice
isfull. IfthereadpointerisnotmovedafterReset(RS),theFull-Flag(FF)will
goLOWafter512/1,024/2,048/4,096/8,192/16,384writestotheIDT72V01/
72V02/72V03/72V04/72V05/72V06.
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations.Uponthecompletionofavalidreadoperation,theFullFlag
(FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO
isfull,theinternalwritepointerisblockedfromW,soexternalchangesinWwill
notaffecttheFIFOwhenitisfull.
EMPTY FLAG (EF)
TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when
thereadpointerisequaltothewritepointer,indicatingthatthedeviceisempty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
Thisisadual-purposeoutput. Inthesingledevicemode,whenExpansion
In(XI)isgrounded,thisoutputactsasanindicationofahalf-fullmemory.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesetLOWandwillremainsetuntilthe
differencebetweenthewritepointerandreadpointeris less thanorequalto
onehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by using rising edge of the read operation.
IntheDepthExpansionMode,ExpansionIn(XI)isconnectedtoExpansion
Out(XO)ofthepreviousdevice.Thisoutputactsasasignaltothenextdevice
intheDaisyChainbyprovidingapulsetothenextdevicewhentheprevious
devicereachesthelastlocationofmemory.
READ ENABLE (R)
AreadcycleisinitiatedonthefallingedgeoftheReadEnable(R)provided
theEmptyFlag(EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,
independent of any ongoing write operations. After Read Enable (R) goes
HIGH,theDataOutputs(Q0–Q8)willreturntoahighimpedanceconditionuntil
thenextReadoperation. WhenalldatahasbeenreadfromtheFIFO,theEmpty
Flag(EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurtherread
operationswiththedataoutputsremaininginahighimpedancestate.Oncea
validwriteoperationhasbeenaccomplished,theEmptyFlag(EF)willgoHIGH
aftertWEFandavalidReadcanthenbegin. WhentheFIFOisempty,theinternal
readpointerisblockedfromRsoexternalchangesinRwillnotaffecttheFIFO
whenitisempty.
DATA OUTPUTS (Q0 – Q8)
Dataoutputsfor9-bitwidedata. Thisdataisinahighimpedancecondition
whenever Read (R) is in a HIGH state.
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
tRSC
tRS
RS
W
tRSR
tRSS
tRSS
R
tEFL
EF
tHFH, tFFH
HF, FF
3033 drw 04
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
tRC
tRPW
tRR
tA
tA
R
tDV
tRHZ
tRLZ
Q0-Q8
DATA OUT VALID
DATA OUT VALID
tWC
tWR
tWPW
W
tDS
tDH
D0-D8
DATA IN VALID
DATA IN VALID
3033 drw 05
Figure 3. Asynchronous Write and Read Operation
FIRST
WRITE
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
R
W
RFF
t
tWFF
3033 drw 06
FF
Figure 4. Full Flag From Last Write to First Read
5
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
R
WEF
t
REF
t
EF
A
t
DATA OUT
VALID
VALID
3033 drw 07
Figure 5. Empty Flag From Last Read to First Write
t
RTC
RT
t
RT
RTS
RTR
t
t
W,R
t
RTF
HF, EF, FF
FLAG VALID
3033 drw 08
Figure 6. Retransmit
W
WEF
t
EF
RPE
t
R
3033 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
FF
W
RFF
t
WPF
t
3033 drw 10
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
W
R
RHF
t
WHF
t
HALF-FULL OR LESS
3033 drw 11
HALF-FULL OR LESS
MORE THAN HALF-FULL
HF
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
W
R
XOH
t
XOH
t
XOL
XOL
t
t
3033 drw 12
XO
Figure 10. Expansion Out
XIR
t
XI
t
XI
XIS
t
WRITE TO
FIRST PHYSICAL
LOCATION
W
R
XIS
t
READ FROM
FIRST PHYSICAL
LOCATION
3033 drw 13
Figure 11. Expansion In
7
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OPERATINGMODES:
USAGEMODES:
Caremustbetakentoassurethattheappropriateflagismonitoredbyeach
system(i.e. FF is monitoredonthe device whereWis used; EF is monitored
onthedevicewhereRisused).Foradditionalinformation,refertoTechNote
8: OperatingFIFOsonFullandEmptyBoundaryConditions andTechNote
WIDTH EXPANSION
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlsignalsofmultipledevices. Statusflags(EF,FFandHF)canbedetected
fromanyonedevice. Figure13demonstrates an18-bitwordwidthbyusing
twoIDT72V01/72V02/72V03/72V04/72V05/72V06s. Anywordwidthcanbe
attainedbyaddingadditionalIDT72V01/72V02/72V03/72V04/72V05/72V06s
(Figure 13).
6: Designing with FIFOs.
SINGLE DEVICE MODE
A single IDT72V01/72V02/72V03/72V04/72V05/72V06 may be used
when the application requirements are for 512/1,024/2,048/4,096/8,192/
16,384wordsorless.ThesedevicesareinaSingleDeviceConfigurationwhen
the Expansion In (XI ) control input is grounded (see Figure 12).
TheseFIFOscaneasilybeadaptedtoapplicationswhentherequirements
are forgreaterthan512/1,024/2,048/4,096/8,192/16,384words. Figure 14
demonstratesDepthExpansionusingthreeIDT72V01/72V02/72V03/72V04/
72V05/72V06s. Any depth can be attained by adding additional IDT72V01/
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT72V01/72V02/72V03/72V04/72V05/72V06sasshowninFigure16.Both
DepthExpansionandWidthExpansionmaybeusedinthis mode.
72V02/72V03/72V04/72V05/72V06s. These devices operate in the Depth DATAFLOW-THROUGH
Expansionmodewhenthefollowingconditionsaremet:
Twotypesofflow-throughmodesarepermitted,areadflow-throughand
writeflow-throughmode. Forthereadflow-throughmode(Figure17),theFIFO
permitsareadingofasinglewordafterwritingonewordofdataintoanempty
FIFO. Thedataisenabledonthebusin(tWEF +tA)nsaftertherisingedgeof
W,calledthefirstwriteedge,anditremainsonthebusuntiltheRlineisraised
fromLOW-to-HIGH,afterwhichthebuswouldgointoathree-statemodeafter
tRHZ ns.TheEF linewouldhaveapulseshowingtemporarydeassertionand
thenwouldbeasserted.
Inthewriteflow-throughmode(Figure18),theFIFOpermitsthewritingof
asinglewordofdataimmediatelyafterreadingonewordofdatafromafullFIFO.
The Rlinecauses theFF tobe deassertedbutthe WlinebeingLOWcauses
ittobeassertedagaininanticipationofanewdataword. Ontherisingedge
ofW,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhenFF
isnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer.
1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(FL)control
input.
2. Allotherdevices musthave FL inthe HIGHstate.
3. TheExpansionOut(XO)pinofeachdevicemustbetiedtotheExpansion
In ( XI ) pin of the next device. See Figure 14.
4. ExternallogicisneededtogenerateacompositeFullFlag(FF)andEmpty
Flag (EF ). This requires the ORing of all EFs and ORing of all FFs (i.e.
allmustbesettogeneratethecorrectcompositeFForEF). SeeFigure14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available
inthe DepthExpansionMode.
Foradditionalinformation,refertoTechNote9: CascadingFIFOsorFIFO
Modules.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
(HALF-FULL FLAG)
(HF)
WRITE (W)
IDT
READ (R)
72V01
72V02
72V03
72V04
72V05
72V06
9
9
DATA OUT (Q)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
EMPTY FLAG (EF)
RETRANSMIT (RT)
3033 drw 14
EXPANSION IN (XI)
Figure 12. Block Diagram of Single 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9 FIFO
HF
HF
18
9
9
IN
DATA (D)
IDT
IDT
72V01
72V02
72V03
72V04
72V05
72V06
72V01
72V02
72V03
72V04
72V05
72V06
WRITE (W)
FULL FLAG (FF)
RESET (RS)
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
9
9
XI
XI
18
OUT(Q)
DATA
3033 drw 15
Figure 13. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 and 16,384 x 18 FIFO Memory Used in Width Expansion Mode
TABLE 1 — RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
InternalStatus
Write Pointer
Outputs
Mode
RS
0
RT
X
0
XI
0
Read Pointer
LocationZero
LocationZero
EF
0
FF
1
HF
1
Reset
LocationZero
Unchanged
Retransmit
1
0
X
X
X
X
X
X
(1)
(1)
Read/Write
1
1
0
Increment
Increment
NOTE:
1. Pointer will increment if flag is HIGH
9
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
InternalStatus
Write Pointer
Outputs
Mode
ResetFirstDevice
Reset All Other Devices
Read/Write
RS
0
FL
0
XI
(1)
(1)
(1)
Read Pointer
LocationZero
LocationZero
X
EF
0
FF
1
LocationZero
LocationZero
X
0
1
0
1
1
X
X
X
NOTE:
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
XI = Expansion Input, HF = Half-Full Flag Output
XO
IDT
R
W
72V01
72V02
72V03
72V04
72V05
72V06
FF
EF
FL
9
9
9
Q
D
VCC
XI
XO
IDT
FF
EF
FL
72V01
72V02
72V03
72V04
72V05
72V06
EMPTY
FULL
9
9
XI
XO
IDT
FF
EF
FL
72V01
72V02
72V03
72V04
72V05
72V06
RS
XI
Figure 14. Block Diagram of 1,536 x 9, 3,072 x 9, 6,144 x 9, 12,288 x 9, 24,576 x 9 and 49,152 x 9 FIFO Memory (Depth Expansion)
Q0-Q
8
Q9-Q17
Q
(N-8)-QN
IDT
IDT
IDT
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
R, W, RS
EXPANSION
BLOCK
EXPANSION
BLOCK
EXPANSION
BLOCK
D0-D
8
D9-D17
D(N-8)-DN
D0-DN
3033 drw 17
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V063.3VASYNCHRONOUSFIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
IDT
72V01
WA
RB
EFB
HFB
72V02
72V03
72V04
FFA
72V05
72V06
A 0-8
D
B 0-8
Q
SYSTEM A
SYSTEM B
A 0-8
Q
B 0-8
D
IDT
72V01
72V02
72V03
72V04
72V05
RA
HFA
EFA
WB
72V06
3033 drw 18
FFB
Figure 16. Bidirectional FIFO Mode
IN
DATA
W
R
RPE
t
EF
REF
WEF
t
t
WLZ
t
A
t
OUT
OUT
DATA
DATA
VALID
3033 drw 19
Figure 17. Read Data Flow-Through Mode
R
W
WPF
t
RFF
t
FF
DH
t
WFF
t
IN
DATA
VALID
IN
DATA
A
t
DS
t
OUT
DATA
OUT
DATA
VALID
3033 drw 20
Figure 18. Write Data Flow-Through Mode
11
ORDERING INFORMATION
IDT
XXXXX
L
XXX
X
X
Device Type Power Speed Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
J
Plastic Leaded Chip Carrier (PLCC, J32-1)
15
25
35
Commercial Only
Com’l and Ind’l
Commercial Only
Access Time (tA)
Speed in Nanoseconds
L
Low Power
72V01
72V02
72V03
72V04
72V05
72V06
512 x 9 FIFO
1,024 x 9 FIFO
2,048 x 9 FIFO
4,096 x 9 FIFO
8,192 x 9 FIFO
16,384 x 9 FIFO
3033 drw 21
NOTE:
1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
08/29/2001
04/08/2003
05/05/2003
pg. 3.
pg. 2.
pg. 2.
CORPORATE HEADQUARTERS
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www.idt.com
12
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