IDT72V10071L15TFI [IDT]
FIFO, 512X8, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64;
| 型号： | IDT72V10071L15TFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 512X8, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64 先进先出芯片 |
| 文件： | 总10页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
IDT72V10071,IDT72V11071
IDT72V12071,IDT72V13071
IDT72V14071
FEATURES
DESCRIPTION
TheIDT72V10071/72V11071/72V12071/72V13071/72V14071aredual
Multimedia FIFOs. The device is functionallyequivalenttotwoindependent
FIFOs in a single package with all associated control, data, and flag lines
assignedtoseparatepins.
Eachofthe twoFIFOs (designatedFIFOAandFIFOB)has a 8-bitinput
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB),andaWriteEnablepin(WENA,WENB).Dataiswrittenintoeachof
thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)
whentheappropriateWriteEnablepinisasserted.
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin
(RCLKA,RCLKB)andReadEnablepin(RENA,RENB).TheReadClockcan
betiedtotheWriteClockforsingleclockoperationorthetwoclocks canrun
asynchronousofoneanotherfordualclockoperation.AnOutputEnablepin
(OEA,OEB)is providedonthe readportofeachFIFOforthree-state output
control.
• Memory organization:
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Dual 256 x 8
Dual 512 x 8
Dual 1,024 x 8
Dual 2,048 x 8
Dual 4,096 x 8
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• 15 ns read/write cycle time
• 5V input tolerant
• Separate control lines and data lines for each FIFO
• Separate Empty and Full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
• Industrial temperature range (–40°C to +85°C)
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,
FFB).
• Green parts available, see ordering information
This FIFOis fabricatedusingIDT's high-performancesubmicronCMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
RCLKA
READ
CONTROL
WRITE
CONTROL
WENA
RENA
OEA
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
D
A0 - DA7
Data In
Q
A0 - QA7
Data Out
x8
x8
RESET LOGIC
FLAG OUTPUTS
RSA
EFA
FFA
WCLKB
RCLKB
READ
CONTROL
WRITE
CONTROL
WENB
RENB
OEB
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
D
B0 - DB7
Data In
Q
B0 - QB7
Data Out
x8
x8
RESET LOGIC
FLAG OUTPUTS
6360 drw01
RSB
EFB
FFB
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
DECEMBER 2004
INDUSTRIAL TEMPERATURE RANGE
1
2004 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DSC-6360/3
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
QB
7
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QA
6
5
4
FFB
QA
EFB
QA
OEB
DNC(1)
GND
QA
QA
QA
QA
V
3
2
1
0
RCLKB
RENB
GND
9
Vcc
VCCCC
WCLKA
WENA
RSA
10
11
12
13
14
15
16
DNC(1)
DNC(1)
DB
DB
DB
DB
7
6
5
4
DA
0
DA
1
2
GND
DA
6360 drw02
NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTIONS
The IDT72V10071/72V11071/72V12071/72V13071/72V14071's two
FIFOs, referred to as FIFO A and FIFO B, are identical in every respect.
FIFOAandFIFOBoperate completelyindependentfromeachother.
Symbol
DA0-DA7
DB0-DB7
RSA,RSB
Name
ADataInputs
BDataInputs
Reset
I/O
Description
I
I
I
8-bit data inputs to FIFO array A.
8-bit data inputs to FIFO array B.
WhenRSA(RSB)is setLOW, the associatedinternalreadandwrite pointers ofarrayA(B)are settothe first
location; FFA (FFB) go as HIGH and EFA (EFB) go as LOW. After power-up, a reset of both FIFOs A and B
is requiredbeforeaninitialWRITE.
WCLKA
WCLKB
WriteClock
I
I
Data is writtenintothe FIFOA(B)ona LOW-to-HIGHtransitionofWCLKA(WCLKB)whenthe write enable
isasserted.
WENA
WENB
WriteEnable
WhenWENA (WENB)is LOW, data A(B)is writtenintothe FIFOoneveryLOW-to-HIGHtransition WCLKA
(WCLKB). Data will not be written into the FIFO ifFFA (FFB)is LOW.
QA0-QA7
ADataOutputs
BDataOutputs
Read Clock
O 8-bitdata outputs fromFIFOarrayA.
QB0-QB7
O 8-bitdata outputs fromFIFOarrayB.
RCLKA
RCLKB
I
I
I
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA (RENB) is
asserted.
RENA
RENB
OEA
OEB
EFA
EFB
FFA
FFB
Read Enable
OutputEnable
EmptyFlag
Full Flag
When RENA (RENB) is LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA
(RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
WhenOEA(OEB)is LOW,outputs DA0-DA7(DB0-DB7)are active.IfOEA(OEB)is HIGH,outputs
DA0-DA7 (DB0-DB7) will be in a high-impedance state.
O WhenEFA (EFB)is LOW, FIFOA(B)is emptyandfurtherdata reads fromthe outputare inhibited. When
EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. WhenFFA
(FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
VCC
Power
+3.3V power supply pin.
0V ground pin.
GND
Ground
3
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDOPERATING
CONDITIONS
Symbol
Rating
Industrial
Unit
VTERM
TerminalVoltagewith
Respect to GND
StorageTemperature
DCOutputCurrent
–0.5 to +5
V
Symbol
Parameter
Min
Typ.
Max
Unit
VCC
SupplyVoltage(Industrial)
SupplyVoltage(Industrial)
InputHighVoltage(Industrial)
InputLowVoltage(Industrial)
3.0
3.3
3.6
V
TSTG
IOUT
–55to+125
–50to+50
°C
mA
GND
VIH
VIL
0
0
—
5.0
0.8
85
V
V
V
2.0
—
-40
—
—
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
OperatingTemperature
Industrial
°
C
NOTE:
1. Outputs are not 5V tolerant.
DCELECTRICALCHARACTERISTICS
(Industrial :VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Industrial
tCLK = 15 ns
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Typ.
—
Max.
Unit
µ A
µ A
V
(1)
ILI
–1
10
—
0.4
40
10
(2)
ILO
–10
2.4
—
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current (both FIFOs)
StandbyCurrent
—
—
V
(3,4,5)
ICC1
—
—
mA
mA
(2,6)
ICC2
—
—
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OEA, OEB ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs disabled (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 2[0.17 + 0.48*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25
°
C, f = 1.0MHz)
Conditions
VIN = 0V
Symbol
Parameter
Max.
Unit
(2)
CIN
InputCapacitance
10
pF
(1,2)
COUT
Output Capacitance
VOUT = 0V
10
pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
4
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
(1)
ACELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
Industrial
IDT72V10071L15
IDT72V11071L15
IDT72V12071L15
IDT72V13071L15
IDT72V14071L15
Symbol
fS
Parameter
Min.
—
2
Max.
66.7
10
Unit
MHz
ns
Clock Cycle Frequency
DataAccessTime
Clock Cycle Time
Clock High Time
tA
tCLK
tCLKH
tCLKL
tDS
15
6
—
—
—
—
—
—
—
—
—
—
15
ns
ns
Clock Low Time
6
ns
DataSet-upTime
DataHoldTime
4
ns
tDH
1
ns
tENS
tENH
tRS
EnableSet-upTime
EnableHoldTime
ResetPulseWidth(1)
ResetSet-upTime
ResetRecoveryTime
4
ns
1
ns
15
10
10
—
0
ns
tRSS
tRSR
tRSF
tOLZ
tOE
ns
ns
ResettoFlagTimeandOutputTime
ns
(2)
OutputEnabletoOutputinLow-Z
—
8
ns
OutputEnabletoOutputValid
3
ns
(2)
tOHZ
tWFF
tREF
tSKEW1
OutputEnabletoOutputinHigh-Z
3
8
ns
Write Clock to Full Flag
—
—
6
10
ns
Read Clock to Empty Flag
10
ns
Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
ACTESTCONDITIONS
In Pulse Levels
30pF*
510Ω
GND to 3.0V
3ns
InputRise/FallTimes
6360 drw03
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
1.5V
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
See Figure 1
5
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
Read Enable (RENA, RENB) — When Read Enable, RENA, (RENB) is
LOW,dataisreadfromArrayA(B)totheoutputregisterontheLOW-to-HIGH
transitionofthe ReadClock, RCLKA(RCLKB).
When Read Enable, RENA, (RENB) for FIFO A (B) is HIGH, the output
registerholdsthepreviousdataandnonewdataisallowedtobeloadedinto
theregister.
SIGNALDESCRIPTIONS
FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS
When all the data has been read from FIFO A (B), the Empty Flag, EFA
(EFB) will go LOW, inhibiting further read operations. Once a valid write
operationhas beenaccomplished, EFA(EFB)willgoHIGHaftertREF anda
validreadcanbegin.TheReadEnable,RENA,(RENB)isignoredwhenFIFO
A (B) is empty.
Data In (DA0 – DA7, DB0 – DB7) — DA0 - DA7 are the eight data inputs
formemoryarrayA.DB0 -DB7 aretheeightdatainputs formemoryarrayB.
CONTROLS
Reset(RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(RSB)inputistakentoaLOWstate.Duringreset,theinternalreadandwrite
pointersassociatedwiththeFIFOaresettothefirstlocation.Aresetisrequired
after power-up before a write operation can take place. The Full Flag, FFA
(FFB)willberesettoHIGHaftertRSF.TheEmptyFlag,EFA(EFB)willbereset
toLOWaftertRSF.Duringreset,theoutputregisterisinitializedtoallzeros.
Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is
enabled(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheir
respective output register. When Output Enable, OEA (OEB) is disabled
(HIGH), the QA(QB)outputdata bus is ina high-impedance state.
OUTPUTS
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA(FFB)willgoLOWafter256writestotheIDT72V10071'sFIFOA(B),512
writestotheIDT72V11071'sFIFOA(B),1,024writestotheIDT72V12071's
FIFOA(B),2,048writestotheIDT72V13071'sFIFOA(B),and4,096writes
to the IDT72V14071's FIFO A (B).
WriteClock(WCLKA,WCLKB)—AwritecycletoArrayA(B)isinitiated
ontheLOW-to-HIGHtransitionofWCLKA(WCLKB).Dataset-upandhold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag, FFA (FFB) is synchronized with respect to the
LOW-to-HIGHtransitionoftheWriteClock,WCLKA(WCLKB).
The Write and Read clock can be asynchronous or coincident.
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionof
theWriteClockWCLKA(WCLKB).
WriteEnable(WENA,WENB)—WhenWENA(WENB)isLOW,datacan
be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH
transitionofeveryWriteClock,WCLKA(WCLKB).Datais storedinArrayA
(B) sequentially and independently of any on-going read operation.
WhenWENA(WENB)isHIGH,theinputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
Topreventdataoverflow,FFA(FFB)willgoLOW,inhibitingfurtherwrite
operations.Uponthe completionofa validreadcycle,the FFA (FFB)willgo
HIGHaftertWFF,allowingavalidwritetobegin.WENA(WENB)isignoredwhen
FIFO A (B) is full.
EmptyFlag(EFA,EFB)—EFA(EFB)willgoLOW,inhibitingfurtherread
operations,whenthereadpointerisequaltothewritepointer,indicatingthat
Array A (B) is empty.
EFA(EFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 –QA7, QB0 –QB7)—QA0 -QA7are the eightdata
outputsformemoryarrayA,QB0-QB7aretheeightdataoutputsformemory
array B.
Read Clock (RCLKA, RCLKB) —
Data can be read from Array A (B) on the LOW-to-HIGH transition of
RCLKA(RCLKB).TheEmptyFlag,EFA(EFB)issynchronizedwithrespect
totheLOW-to-HIGHtransitionofRCLKA(RCLKB).
The Write and Read Clock can be asynchronous or coincident.
6
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
tRS
RSA (RSB)
t
RSS
t
RSR
RSR
REN A (REN B)
t
t
RSS
WEN A (WEN B)
t
RSF
RSF
EF A
(EF B)
t
F F A
(F F B)
tRSF
OEA (OEB) = 1(1)
QA0
- QA
7
(QB
0
- QB7)
6360 drw04
OEA (OEB) = 0
NOTES:
1. After reset, QA0 - QA7 (QB0 - QB7) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
2. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 2. Reset Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDH
tDS
(DA
DB
0
- DA
7
0
- DB7)
DATA IN VALID
tENH
tENS
WEN A (WEN B)
F F A (F F B)
NO OPERATION
tWFF
tWFF
(1)
SKEW1
t
RCLKA (RCLKB)
REN A (REN B)
6360 drw05
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
Figure 3. Write Cycle Timing
7
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENH
tENS
NO OPERATION
REN A (REN B)
tREF
tREF
EF A (EF B)
tA
QA
0
0
- QA
7
VALID DATA
(QB
- QB7)
tOLZ
tOHZ
tOE
OEA (OEB)
(1)
SKEW1
t
WCLKA, WCLKB
WEN A (WEN B)
6360 drw06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
Figure 4. Read Cycle Timing
WCLKA (WCLKB)
tDS
DA
0
- DA
7
D1
D2
D3
(DB
0
- DB7)
tENS
D0 (First Valid Write)
WEN A (WEN B)
(1)
FRL
t
tSKEW1
RCLKA (RCLKB)
tREF
EF A (EF B)
tENS
REN A (REN B)
tA
tA
QA
0
- QA
7
D0
D1
(QB
0
- QB7)
tOLZ
tOE
OEA (OEB)
6360 drw07
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 5. First Data Word Latency Timing
8
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIALTEMPERATURERANGE
NO WRITE
NO WRITE
NO WRITE
WCLKA
(WCLKB)
tSKEW1
tSKEW1
tDS
tDH
DA
0
- DA
7
(DB
0
- DB7)
tWFF
tWFF
tWFF
FFA (FFB)
tENS
tENS
tENH
WENA
(WENB)
RCLKA
(RCLKB)
tENH
tENH
tENS
tENS
RENA
(RENB)
tA
LOW
OEA
(OEB)
tA
QA
0
- QA
7
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB7)
6360 drw08
Figure 6. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA
(DB
0
- DA
7
DATA WRITE 1
DATA WRITE 2
0
- DB7)
tENS
tENH
tENS
tENH
WENA, (WENB)
(1)
FRL
(1)
FRL
t
t
tSKEW1
tSKEW1
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA
(RENB)
LOW
OEA (OEB)
tA
QA
0
- QA
7
DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB7)
6360 drw09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. Empty Flag Timing
9
ORDERING INFORMATION
IDT
XXXXX
X
XX
XX
XX
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
Industrial (-40°C to +85°C)
Green
I
G
TF
Plastic Quad Flatpack (STQFP, PP64-1)
Clock Cycle Time (tCLK),
Industrial
15
L
speed in Nanoseconds
Low Power
256 x 8 3.3 Volt DUAL Multimedia FIFO
512 x 8 3.3 Volt DUAL Multimedia FIFO
1,024 x 8 3.3 Volt DUAL Multimedia FIFO
2,048 x 8 3.3 Volt DUAL Multimedia FIFO
72V10071
72V11071
72V12071
72V13071
72V14071
4,096 x 8 3.3 Volt DUAL Multimedia FIFO
6360 drw10
NOTE:
1. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
11/17/2003
12/07/2004
pg. 1.
pg. 10.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
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