IDT72V13165L15TFGI8 [IDT]
FIFO, 1KX16, 10ns, Synchronous, PQFP64, STQFP-64;
| 型号： | IDT72V13165L15TFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 1KX16, 10ns, Synchronous, PQFP64, STQFP-64 先进先出芯片 |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT MULTIMEDIA FIFO
256 x 16, 512 x 16,
1,024 x 16, 2,048 x 16,
and 4,096 x 16
IDT72V11165, IDT72V12165
IDT72V13165, IDT72V14165
IDT72V15165
FEATURES
DESCRIPTION
• 256 x 16-bit organization array (IDT72V11165)
• 512 x 16-bit organization array (IDT72V12165)
• 1,024 x 16-bit organization array (IDT72V13165)
• 2,048 x 16-bit organization array (IDT72V14165)
• 4,096 x 16-bit organization array (IDT72V15165)
• 15 ns read/write cycle time
TheIDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
areFirst-In,First-Out(FIFO)memorieswithclockedreadandwritecontrols.
TheseFIFOshave16-bitinputandoutputports. Theinputportiscontrolled
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataiswritten
intotheMultimediaFIFOoneveryclockwhenWENisasserted.Theoutputport
iscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).The
ReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperationor
thetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.
AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol
oftheoutput.
• 5V input tolerant
• Independent Read and Write Clocks
• Empty/Full and Half-Full flag capability
• Output enable puts output data bus in high-impedance state
• Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)
TheseMultimediaFIFOs supportthreefixedflags:EmptyFlag(EF),Full
Flag (FF), and Half Full Flag (HF).
• Industrial temperature range (–40°C to +85°C)
FUNCTIONAL BLOCK DIAGRAM
WCLK
RCLK
READ
CONTROL
WRITE
CONTROL
WEN
REN
OE
FIFO ARRAY
D0
- D15
Q0 - Q15
Data In
x16
Data Out
x16
RESET LOGIC
FLAG OUTPUTS
EF
HF
FF
RS
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IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
NOVEMBER 2003
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6359/2
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
PIN CONFIGURATIONS
PIN 1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D1
D2
D3
1
2
3
Q
Q
GND
2
3
48
47
46
D
D
D
D
D
D
4
5
6
7
8
9
4
5
6
7
8
9
10
11
12
13
14
15
16
Q
Q
VCC
Q
Q
GND
4
5
45
44
43
42
41
40
39
38
37
36
6
7
D10
D11
D12
D13
D14
D15
Q
Q
Q
Q
8
9
10
11
GND
35
34
33
Q12
GND
VCC
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NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
PINDESCRIPTION
Symbol
Name
I/O
I
Description
D0–D15 DataInputs
Datainputs foran16-bitbus.
EF
FF
HF
OE
EmptyFlag
Full Flag
O
O
O
I
EF indicates whetherornotthe FIFOmemoryis empty.
FF indicates whetherornotthe FIFOmemoryis full.
The device is more than half full when HF is LOW.
Half-FullFlag
OutputEnable
WhenOEisLOW,thedataoutputbusisactive.IfOEisHIGH,theoutputdatabuswillbeinahigh-impedance
state.
Q0–Q15 DataOutputs
O
I
Dataoutputsforan16-bitbus.
RCLK
ReadClock
WhenRENisLOW,dataisreadfromtheFIFOonaLOW-to-HIGHtransitionofRCLK,iftheFIFOisnotempty.
REN
ReadEnable
I
WhenRENisLOW,dataisreadfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK. WhenRENisHIGH,
the outputregisterholds the previous data. Data willnotbe readfromthe FIFOiftheEF is LOW.
RS
Reset
I
WhenRS is setLOW, internalreadandwrite pointers are settothe firstlocationofthe RAMarray,FF
goes HIGH, and EF goes LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I
I
WhenWENisLOW,dataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLK,iftheFIFOisnotfull.
WEN
WriteEnable
WhenWENis LOW,datais writtenintotheFIFOonevery LOW-to-HIGHtransitionofWCLK.WhenWENis
HIGH, the FIFOholds the previous data. Data willnotbe writtenintothe FIFOifthe FF is LOW.
VCC
Power
I
I
+3.3V power supply pins.
Groundpins.
GND
Ground
2
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Industrial
Unit
Symbol
VCC
Parameter
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Unit
V
(2)
VTERM
TerminalVoltage
with respect to GND
–0.5to+5
V
SupplyVoltageIndustrial
SupplyVoltage
GND
VIH
V
TSTG
Storage
Temperature
–55to+125
–50to+50
°C
InputHighVoltageIndustrial
InputLowVoltageIndustrial
2.0
—
5.5
V
IOUT
DCOutputCurrent
mA
(1)
VIL
-0.5
-40
—
0.8
85
V
NOTES:
TA
OperatingTemperature
Industrial
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2. VCC terminal only.
DCELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Industrial
tCLK = 15 ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
1
Unit
(1)
ILI
InputLeakageCurrent(anyinput)
OutputLeakageCurrent
µA
µA
V
(2)
ILO
–10
2.4
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
—
V
(3,4,5)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
—
—
30
5
mA
mA
(3,6)
ICC2
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs disabled (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
5. Typical ICC1 = 2.04 + 0.88*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
ACELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Industrial
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
—
2
Max.
66.7
10
Unit
MHz
ns
tA
DataAccessTime
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
tCLK
tCLKH
tCLKL
tDS
15
6
—
—
—
—
—
—
—
—
—
—
15
ns
ns
6
ns
DataSet-upTime
4
ns
tDH
DataHoldTime
1
ns
tENS
tENH
tRS
EnableSet-upTime
EnableHoldTime
ResetPulseWidth(2)
ResetSet-upTime
ResetRecoveryTime
ResettoFlagandOutputTime
4
ns
1
ns
15
10
10
—
0
ns
tRSS
tRSR
tRSF
tOLZ
tOE
ns
ns
ns
(3)
OutputEnabletoOutputinLow-Z
OutputEnabletoOutputValid
—
8
ns
3
ns
(3)
tOHZ
tWFF
tREF
tHF
OutputEnabletoOutputinHigh-Z
Write Clock to Full Flag
3
8
ns
—
—
—
6
10
ns
Read Clock to Empty Flag
10
ns
ClocktoHalf-FullFlag
20
ns
tSKEW1
Skew time between Read Clock & Write Clock for FF and EF
—
ns
NOTES:
1. Industrial temperature range product for the 15ns speed grade available.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
30pF*
510Ω
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
1.5V
1.5V
SeeFigure1
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Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
Figure 1. Output Load
* Includes jig and scope capacitances.
4
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.
Uponthecompletionofavalidreadcycle,FF willgoHIGHallowingawriteto
occur. The FF flag is updated on the rising edge of WCLK.
FUNCTIONALDESCRIPTION
WRITE/READ AND FLAG FUNCTION
To write data into to the FIFO, Write Enable (WEN) must be LOW. Data
presentedtothe DATAINlines willbe clockedintothe FIFOonsubsequent
transitionsoftheWriteClock(WCLK).Afterthefirstwriteisperformed,theEmpty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-FullFlag(HF)wouldtoggletoLOWonce
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK),whenOutputEnable(OE)is setLOW.
The Write andReadClocks canbe asynchronous orcoincident.
the 129th (72V11165), 257th (72V12165), 513th (72V13165), 1,025th READ ENABLE (REN)
(72V14165),and2,049th(72V15165)wordrespectivelywaswrittenintothe
FIFO.
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
totheFIFO. D=256writesfortheIDT72V11165,512fortheIDT72V12165, the previous data value.
1,024 for the IDT72V13165, 2,048 for the IDT72V14165 and 4,096 for the
IDT72V15165,respectively.
EverywordaccessedatQn,includingthefirstwordwrittentoanemptyFIFO,
mustberequestedusingREN. WhenthelastwordhasbeenreadfromtheFIFO,
If the FIFO is full, the first read operation will cause FF to go HIGH. the Empty Flag (EF) will go LOW, inhibiting further read operations. RENis
Subsequent read operations will cause the Half-Full Flag (HF) to go HIGH. ignoredwhentheFIFOisempty. Onceawriteisperformed,EFwillgoHIGH
ContinuingreadoperationswillcausetheFIFOtobeempty.Whenthelastword allowingareadtooccur. TheEFflagis updatedontherisingedgeofRCLK.
has been read from the FIFO, the EF will go LOW inhibiting further read
operations. REN is ignored when the FIFO is empty.
OUTPUTENABLE(OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
SIGNALDESCRIPTIONS
INPUTS
DATA IN (D0 - D15)
Datainputsfor16-bitwidedata.
OUTPUTS
FULL FLAG/INPUT READY (FF)
WhentheFIFOisfull,FF willgoLOW,inhibitingfurtherwriteoperations.
WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwritestotheFIFO. D=256writesfortheIDT72V11165,
512 for the IDT72V12165, 1,024 for the IDT72V13165, 2,048 for the
IDT72V14165 and 4,096 for the IDT72V15165.
CONTROLS
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputis takentoaLOW
state. During reset, both internal read and write pointers are set to the first
location.Aresetisrequiredafterpower-upbeforeawriteoperationcantake
place.TheHalf-FullFlag(HF) toHIGHaftertRSF. TheFullFlag (FF)willreset
toHIGH. TheEmptyFlag(EF)willresettoLOW.Duringreset,theoutputregister
isinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
FF is synchronous and updated on the rising edge of WCLK.
EMPTYFLAG/OUTPUTREADY(EF)
WhentheFIFOisempty,EFwillgoLOW,inhibitingfurtherreadoperations.
When EF is HIGH, the FIFOis notempty.
WRITE CLOCK (WCLK)
EF is synchronous and updated on the rising edge of RCLK.
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
HALF-FULL FLAG (HF)
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference
betweenthewritepointerandreadpointeris less thanorequaltoonehalfof
thetotalmemoryofthedevice.TheHalf-FullFlag(HF)is thenresettoHIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
The Write andReadClocks canbe asynchronous orcoincident.
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
DATAOUTPUTS(Q0-Q15)
Dataoutputsfor16-bitwidedata.
5
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
tRS
RS
tRSR
REN, WEN
RCLK, WCLK(1)
FF
t
RSF
IDT Standard Mode
IDT Standard Mode
tRSF
EF
HF
t
RSF
RSF
t
(2)
OE = 1
Q0 - Q15
6359 drw04
OE = 0
NOTES:
1. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
2. After reset, the outputs will be LOW if OE = 0 and high-impedanced if OE = 1.
Figure 2. Reset Timing(1)
NO WRITE
NO WRITE
2
1
WCLK
1
2
DATA WRITE
(1)
SKEW1
(1)
SKEW1
tDS
tDS
t
t
Wd
D0
- D15
FF
tWFF
tWFF
tWFF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
t
A
NEXT DATA READ
DATA IN OUTPUT REGISTER
DATA READ
Q0
- Q15
6359 drw24
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
Figure 3. Full Flag Timing
6
INDUSTRIAL
TEMPERATURERANGE
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
tCLK
tCLKH
tCLKL
1
2
WCLK
tDS
tDH
D
0
-
D15
DATA IN VALID
ENS
tENH
t
NO OPERATION
WEN
FF
tWFF
tWFF
(1)
SKEW1
t
RCLK
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REN
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
Figure 4. Write Cycle Timing
tCLK
tCLKH
tCLKL
1
2
RCLK
tENH
tENS
NO OPERATION
REN
EF
tREF
tREF
tA
Q0
-
Q
15
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
SKEW1
t
WCLK
tENH
tENS
WEN
tDH
tDS
FIRST WORD
D0
-
D15
6359 drw26
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
Figure 5. Read Cycle Timing
7
ORDERING INFORMATION
XXXXX
Device Type
X
XX
Speed
X
X
IDT
Power
Package
Process /
Temperature
Range
I
Industrial (-40°C to +85°C)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
TF
Clock Cycle Time (tCLK
)
Industrial
15
L
Speed in Nanoseconds
Low Power
256 x 16 3.3V Multimedia FIFO
512 x 16 3.3V Multimedia FIFO
1,024 x 16 3.3V Multimedia FIFO
72V11165
72V12165
72V13165
72V14165 2,048 x 16 3.3V Multimedia FIFO
72V15165 4,096 x 16 3.3V Multimedia FIFO
6359 drw32
DATASHEETDOCUMENTHISTORY
11/17/2003
pg. 1.
CORPORATEHEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
forSALES:
for TECH SUPPORT:
(408) 330-1753
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
FIFOhelp@idt.com
8
相关型号：
IDT72V13165L15TFI
3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
IDT
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