IDT72V2111L15PF9 [IDT]
FIFO, 512KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64;
| 型号： | IDT72V2111L15PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 512KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64 先进先出芯片 |
| 文件： | 总27页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT HIGH DENSITY CMOS
SUPERSYNC FIFO™
262,144 x 9
IDT72V2101
IDT72V2111
524,288 x 9
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
FEATURES:
• Choose among the following memory organizations:
IDT72V2101
IDT72V2111
⎯
⎯
262,144 x 9
524,288 x 9
DESCRIPTION:
•
Pin-compatible with the IDT72V261/72V271 and the IDT72V281/
72V291 SuperSync FIFOs
The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
includingthefollowing:
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• 5V input tolerant
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• SelectIDTStandardtiming(usingEFandFFflags)orFirstWordFall
Through timing (using OR and IR flags)
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
itis nolongernecessarytoselectwhichofthe twoclockinputs, RCLKor
WCLK, is runningatthe higherfrequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clockcyclecountingdelayassociatedwiththelatencyperiodfound on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu-
nications,datacommunicationsandotherapplicationsthatneedtobufferlarge
amountsofdata.
•
Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
FUNCTIONAL BLOCK DIAGRAM
D0 -D8
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
RAM ARRAY
262,144 x 9
524,288 x 9
FWFT/SI
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0 -Q8
4669 drw 01
OE
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
DECEMBER 2008
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
DSC-4669/4
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequentwords writtentotheFIFOdorequireaLOWonRENforaccess.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFand
FFfunctionsareselectedinIDTStandardmode. TheIRandORfunctionsare
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
DESCRIPTION (CONTINUED)
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor
three-statecontroloftheoutputs.
The frequencies ofboththe RCLKandthe WCLKsignals mayvaryfrom
0 to fMAX with complete independence. There are no restrictions on the
frequency of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsistsofactivatingRENandenablinga
risingRCLKedge,willshiftthewordfrominternalmemorytothedataoutputlines.
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC(1)
2
3
VCC
4
VCC
5
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
6
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
7
8
9
10
11
12
13
14
15
16
Q7
Q6
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4669 drw 02
TQFP (PN64-1, order code: PF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag anddefaultoffsetsselected.
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two
The Partial Reset (PRS) also sets the read and write pointers to the first
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127 location of the memory. However, the timing mode, partial flag program-
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset ming method, and default or programmed offset settings existing before
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith Partial Reset remain unchanged. The flags are updated according to the
the LD pinduringMasterReset.
For serial programming, SEN together with LD on each rising edge of operation, when reprogramming partial flags would be undesirable.
WCLK, are used to load the offset registers via the Serial Input (SI). For
The Retransmitfunctionallows data tobe rereadfromthe FIFO. ALOW
timingmodeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-
parallelprogramming,WENtogetherwithLDoneachrisingedgeofWCLK, on the RT input during a rising RCLK edge initiates a retransmit operation
are used to load the offset registers via Dn. REN together with LD on each by setting the read pointer to the first location of the memory array.
rising edge of RCLK can be used to read the offsets in parallel from Qn
If,atanytime,theFIFOis notactivelyperforminganoperation,thechipwill
regardless of whether serial or parallel offset loading has been selected. automatically power down. Once in the power down state, the standby supply
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
pointers are set to the first location of the FIFO. The FWFT pin selects IDT inputs) will immediately take the device out of the power down state.
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
The IDT72V2101/72V2111 are fabricated using IDT’s high speed submi-
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023 cron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72V2101
72V2111
SERIAL ENABLE(SEN)
RETRANSMIT (RT)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4669 drw 03
Figure 1. Block Diagram of Single 262,144 x 9 and 524,288 x 9 Synchronous FIFO
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
PIN DESCRIPTION
Symbol
D0–D8
MRS
Name
I/O
I
Description
Data Inputs
Data inputs for a 9-bit bus.
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
RCLK
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
OE
SEN
LD
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or
1,023) and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
Programmable
Almost-Full Flag
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Q0–Q8
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bus
VCC
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
(2)
VTERM
TerminalVoltage
–0.5to+4.5
V
Symbol
Parameter
Min.
3.15
0
Typ. Max. Unit
with respect to GND
(1)
VCC
Supply Voltage (Com'l & Ind'l)
3.3
0
3.45
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND Supply Voltage (Com'l & Ind'l)
VIH
Input High Voltage (Com'l & Ind'l)
Input Low Voltage (Com'l & Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
5.5
0.8
+70
+85
V
DCOutputCurrent
mA
(2)
VIL
TA
V
NOTES:
° C
° C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
-40
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. 1.5V undershoots are allowed for 10ns once per cycle.
2. VCC terminal only.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V2101L
IDT72V2111L
Commercial and Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
1
µ A
µA
V
(3)
ILO
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
55
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = XX + XX*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
(1)
Commercial
IDT72V2101L10
IDT72V2111L10
Com’l & Ind’l
IDT72V2101L15
IDT72V2111L15
Commercial
IDT72V2101L20
IDT72V2111L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
Max.
Min.
—
2
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
tA
DataAccessTime
Clock Cycle Time
Clock High Time
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
20
8
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
5
0.5
3
1
1
4
5
tLDH
tRS
LoadHoldTime
0.5
10
15
10
—
0
1
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
—
—
—
6
3
4
5
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
0
0
0
2
2
2
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
OutputEnabletoOutputinHighZ
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
2
6
2
8
2
—
—
—
—
—
8
6.5
6.5
6.5
6.5
16
—
—
—
—
—
9
10
10
10
10
20
—
—
—
—
—
—
10
Read Clock to PAE
Clock to HF
tSKEW1
Skew time between RCLK and WCLK
—
for EF/OR and FF/IR
tSKEW2
Skew time between RCLK and WCLK
12
—
14
—
15
—
ns
for PAE and PAF
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
3. Pulse widths less than minimum values are not allowed.
3.3V
4. Values guaranteed by design, not currently tested.
330Ω
D.U.T.
510Ω
AC TEST CONDITIONS
30pF*
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
4669 drw 04
1.5V
Figure 2. Output Load
* Includes jig and scope capacitances.
See Figure 2
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable1.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72V2101/72V2111supporttwodifferenttimingmodesofoperation:
IDTStandardmodeorFirstWordFallThrough(FWFT)mode. Theselection
ofwhichmodewilloperateisdeterminedduringMasterReset,bythestateof
theFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicatewhetherornottheFIFOhasanyfreespaceforwriting. IntheFWFT
mode, the first word written to an empty FIFO goes directly to Qn after three
RCLKrisingedges, REN =LOWis notnecessary. Subsequentwords must
be accessed using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
131,074thwordfortheIDT72V2101and 262,146thwordfortheIDT72V2111,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (262,145-m) writes for the IDT72V2101 and
(524,289-m)writesfortheIDT72V2111,wheremisthefulloffsetvalue. The
default setting for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
furtherwriteoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGH
afterDwritestotheFIFO. D = 262,145writesfortheIDT72V2101and524,289
writesfortheIDT72V2111,respectively.NotethattheadditionalwordinFWFT
mode is due to the capacity of the memory plus output register.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
theFIFO,ORwillgoHIGHinhibitingfurtherreadoperations.RENisignored
when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable1.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the EmptyFlag(EF)willgoHIGH. Subsequentwrites willcontinue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The defaultsettingforthis value is statedinthe footnote ofTable 1. This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 131,073th word for IDT72V2101 and 262,145th word for
IDT72V2111 respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (PAF) to
go LOW. Again, if no reads are performed, the PAF will go LOW after
(262,144-m) writes for the IDT72V2101 and (524,288-m) writes for the
IDT72V2111. The offset “m” is the full offset value. The default setting for
this value is stated in the footnote of Table 1. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
afterDwritestotheFIFO. D = 262,144writesfortheIDT72V2101and524,288
fortheIDT72V2111,respectively.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
PROGRAMMING FLAG OFFSETS
offsetvalue of07FH(a threshold127words fromthe emptyboundary), and
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V2101/ a default PAF offset value of 07FH (a threshold 127 words from the full
72V2111hasinternalregistersfortheseoffsets.Defaultsettingsarestatedinthe boundary). See Figure 3, Offset Register Location and Default Values.
InadditiontoloadingoffsetvaluesintotheFIFO,italsopossibletoreadthe
currentoffsetvalues.It isonlypossibletoreadoffsetvaluesviaparallelread.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizesthecontrolpinsandsequenceforbothserialandparallelprogramming
modes. For a more detailed description, see discussion that follows.
The offsetregisters maybe programmed(andreprogrammed)anytime
after Master Reset, regardless of whether serial or parallel programming
has been selected.
footnotesofTable1andTable2.OffsetvaluescanbeprogrammedintotheFIFO
inoneoftwoways;serialorparallelloadingmethod.Theselectionoftheloading
methodisdoneusingtheLD(Load)pin.DuringMasterReset,thestateofthe
LD input determines whether serial or parallel flag offset programming is
enabled. AHIGHon LD duringMasterResetselects serialloadingofoffset
valuesandinaddition,setsadefaultPAEoffsetvalueof3FFH(athreshold1,023
words from the empty boundary), and a defaultPAF offsetvalue of3FFH(a
threshold1,023words fromthe fullboundary). ALOWonLD duringMaster
Resetselectsparallelloadingofoffsetvalues,andinaddition,setsadefaultPAE
TABLE I ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IDT72V2101
IDT72V2111
FF PAF HF PAE EF
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
0
0
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 131,072
131,073 to (262,144-(m+1))
(n+1) to 262,144
262,145 to (524,288-(m+1))
(262,144-m) (2) to 262,143
262,144
(524,288-m)
to 524,287
(2)
L
L
L
524,288
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE II ⎯ STATUS FLAGS FOR FWFT MODE
IDT72V2101
IDT72V2111
0
IR PAF HF PAE OR
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
1 to n+1(1)
Number of
Words in
FIFO
H
H
H
H
(n+2) to 262,145
(n+2) to 131,073
131,074 to (262,145-(m+1))
(2)
(2)
262,146 to (524,289-(m+1))
L
(524,289-m)
(262,145-m)
to 524,288
524,289
to 262,144
L
L
262,145
4669 drw 05
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
IDT72V2101 (262,144 x 9⎯BIT)
IDT72V2111 (524,288 x 9⎯BIT)
8
8
7
7
0
0
8
8
7
7
0
EMPTY OFFSET (LSB) REGISTER
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0
EMPTY OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
2 1
0
0
0
0
8
3 2
EMPTY OFFSET
(MSB) REGISTER
EMPTY OFFSET
(MSB) REGISTER
DEFAULT
0H
DEFAULT
0H
8
8
7
7
7
8
8
FULL OFFSET (LSB) REGISTER
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0
0
0
7
FULL OFFSET (MID-BYTE) REGISTER
FULL OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
2 1
0
8
3 2
FULL OFFSET
(MSB) REGISTER
FULL OFFSET
(MSB) REGISTER
DEFAULT
0H
DEFAULT
0H
4669 drw 06
Figure 3. Offset Register Location and Default Values
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
IDT72V2101
IDT72V2111
LD WEN REN SEN
WCLK
RCLK
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
0
0
0
0
1
1
1
0
1
1
1
0
X
Serial shift into registers:
X
36 bits for the 72V2101
38 bits for the 72V2111
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with FUll Offset (MSB)
No Operation
Write Memory
X
X
X
X
1
1
0
1
1
X
X
X
X
1
1
X
1
0
1
X
X
Read Memory
X
No Operation
4669 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
SERIAL PROGRAMMING MODE
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
togglingWEN.
Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduringthe
programmingprocess. Fromthetimeparallelprogramminghasbegun,apartial
flagoutputwillnotbevaliduntiltheappropriateoffsetwordhasbeenwrittento
theregister(s)pertainingtothatflag.MeasuringfromtherisingWCLKedgethat
achievestheabovecriteria;PAFwillbevalidaftertwomorerisingWCLKedges
plustPAF,PAEwillbevalidafterthenexttworisingRCLKedgesplustPAEplus
tSKEW2.
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then
programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: whenLD andSEN are setLOW, data onthe
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 36 bits
for the IDT72V2101 and 38 bits for the IDT72V2111. See Figure 13, Serial
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written
toFIFOmemoryviaDn bytogglingWEN. WhenWEN is broughtHIGHwith
LD and SEN restored to a LOW, the next offset bit in sequence is written
to the registers via SI. If an interruption of serial programming is desired,
it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW
and deactivate LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-
Qn pins when LD is set LOW and REN is set LOW.
For the IDT72V2101/72V2111, data is read via Qn from the Empty Offset
LSB Register on the firstLOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGHtransitionofRCLK, dataarereadfromtheEmptyOffsetMid-Byte
Register. UponthethirdLOW-to-HIGHtransitionofRCLK,dataarereadfrom
the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transition of
RCLK, data are read from the Full Offset LSB Register. Upon the fifth LOW-
to-HIGHtransitionofRCLK,dataarereadfromtheFullOffsetMid-ByteRegister.
Upon the sixth LOW-to-HIGH transition of RCLK, data are read from the Full
OffsetMSBRegister. TheseventhtransitionofRCLKreads,onceagain,from
theEmptyOffsetLSBRegister.SeeFigure15,ParallelReadofProgrammable
Flag Registers, for the timing diagram for this mode.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
Parallelreadingofthe offsetregisters is always permittedregardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
of the LD, WCLK , WEN and Dn input pins.
ProgrammingPAEandPAFproceedsasfollows: whenLDandWENare
setLOW,dataontheinputsDnarewrittenintotheEmptyOffsetLSBRegister
onthefirstLOW-to-HIGHtransitionofWCLK. UponthesecondLOW-to-HIGH
transitionofWCLK,dataarewrittenintotheEmptyOffsetMid-ByteRegister.
UponthethirdLOW-to-HIGHtransitionofWCLK,data arewrittenintotheEmpty
OffsetMSBRegister. UponthefourthLOW-to-HIGHtransitionofWCLK,data
are written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH
transitionofWCLK,dataarewrittenintotheFullOffsetMid-ByteRegister. Upon
thesixthLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffset
MSBRegister. The seventhtransitionofWCLKwrites, once again, intothe
EmptyOffsetLSBRegister.SeeFigure14,ParallelLoadingofProgrammable
FlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer.Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
RETRANSMITOPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
whichconsistsofreadingoutthememorycontents,startingatthebeginning
of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. Atleast two
words, but no more than D - 2 words should have been written into the FIFO
and read from the FIFO between Reset (Master or Partial) and the time of
Retransmitsetup. D = 262,144fortheIDT72V2101andD = 524,288forthe
IDT72V2111 in IDT Standard mode. In FWFT mode, D = 262,145 for the
IDT72V2101 and D = 524,289 for the IDT72V2111.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations ReadingallsubsequentwordsrequiresaLOWonRENtoenabletherisingedge
may begin starting with the first location in memory. Since IDT Standard of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant
mode is selected, every word read including the first word following timingdiagram.
RetransmitsetuprequiresaLOWonRENtoenabletherisingedgeofRCLK.
SeeFigure11,RetransmitTiming(IDTStandardMode),fortherelevanttiming and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
diagram. synchronized to RCLK, thus on the second rising edge of RCLK after RT is
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
If FWFT mode is selected, the FIFO will mark the beginning of the setup, the PAE flag will be updated. HF is asynchronous, thus the rising
Retransmit setup by setting OR HIGH. During this period, the internal read edge of RCLK that RT is setup will update HF. PAF is synchronized to
pointer is set to the first location of the RAM array.
WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
When OR goes LOW, Retransmit setup is complete; at the same time, rising edge of RCLK that RT is setup will update PAF. RT is synchronized
the contents of the first location appear on the outputs. Since FWFT mode to RCLK.
isselected,thefirstwordappearsontheoutputs,noLOWonRENisnecessary.
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
REN and WEN must be HIGH before bringing RT LOW.
SIGNALDESCRIPTION
INPUTS:
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
Retransmit setup requires a LOW on REN to enable the rising edge of
RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array. PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH.
IfFWFTisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
IfLDisLOWduringMasterReset,thenPAEisassignedathreshold127
words fromtheemptyboundaryandPAFis assignedathreshold127words
from the full boundary; 127 words corresponds to an offset value of 07FH.
Following Master Reset, parallel loading of the offsets is permitted, but not
serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whetherornotthereareanywordspresentintheFIFOmemory. Italsouses
the Full Flag function (FF) to indicate whether or not the FIFO memory has
anyfree space forwriting. InIDTStandardmode, everywordreadfromthe
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
modeis active,thenFFwillgoHIGHandEFwillgoLOW. IftheFirstWordFall only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup
and hold times must be met with respect to the LOW-to-HIGH transition of
theWCLK.Itis permissibletostoptheWCLK. NotethatwhileWCLKis idle,
the FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capableofupdatingHFflagtoLOW.) TheWriteandReadClockscaneither
be independentorcoincident.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
WRITE ENABLE (WEN)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
WhenWEN isHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK LOAD (LD)
cycle.
This is a dual purpose pin. During Master Reset, the state of the LD input
To prevent data overflow in the IDT Standard mode, FF will go LOW, determines one oftwodefaultoffsetvalues (127or1,023)forthe PAE and PAF
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle, flags, along with the method by which these offset registers can be pro-
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK grammed, parallel or serial. After Master Reset, LD enables write operations
cycles + tSKEW after the RCLK cycle.
to and read operations from the offset registers. Only the offset loading method
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting currently selected can be used to write to the registers. Offset registers can be
further write operations. Upon the completion of a valid read cycle, IR will read only in parallel. A LOW on LD during Master Reset selects a default PAE
go LOW allowing a write to occur. The IR flag is updated by two WCLK offsetvalueof07FH(athreshold127wordsfromtheemptyboundary),adefault
cycles + tSKEW after the valid RCLK cycle.
PAF offset value of 07FH (a threshold 127 words from the full boundary), and
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode. parallel loading of other offset values. A HIGH on LD during Master Reset
selects a default PAE offset value of 3FFH (a threshold 1,023 words from the
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can from the full boundary), and serial loading of other offset values.
bereadontheoutputs,ontherisingedgeoftheRCLKinput. Itispermissible After Master Reset, the LD pin is used to activate the programming
empty boundary), a default PAF offset value of 3FFH (a threshold 1,023 words
to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF process of the flag offset values PAE and PAF. Pulling LD LOW will begin
flags will not be updated. (Note that RCLK is only capable of updating the a serial loading or parallel load or read of these offset values. See Figure 4,
HF flag to HIGH.) The Write and Read Clocks can be independent or Programmable Flag Offset Programming Sequence.
coincident.
OUTPUTS:
READ ENABLE (REN)
FULL FLAG (FF/IR)
When Read Enable is LOW, data is loaded from the RAM array into the
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
output register on the rising edge of every RCLK cycle if the device is not
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
empty.
write operations. When FF is HIGH, the FIFO is not full. If no reads are
When the REN input is HIGH, the output register holds the previous data
performed after a reset (either MRS or PRS), FF will go LOW after D writes to
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
theFIFO(D = 262,144fortheIDT72V2101and 524,288fortheIDT72V2111).
SeeFigure7,WriteCycleandFullFlagTiming(IDTStandardMode),forthe
relevant timing information.
InFWFTmode, the InputReady(IR)functionis selected. IRgoes LOW
whenmemoryspace is available forwritingindata. Whenthere is nolonger
any free space left, IR goes HIGH, inhibiting further write operations. If no
reads areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafter
D writes to the FIFO (D = 262,145 for the IDT72V2101 and 524,289 for the
IDT72V2111) See Figure 9, Write Timing (FWFT Mode), for the relevant
timing information.
The IR status not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
doubleregister-bufferedoutputs.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN =
LOW), inhibiting further read operations. REN is ignored when the FIFO is
empty.
SERIAL ENABLE (SEN)
EMPTY FLAG (EF/OR)
The SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected during
MasterReset. SENisalwaysusedinconjunctionwithLD. Whentheselines
are both LOW, data at the SI input can be loaded into the program register
one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings andnooffsets areloaded. SENfunctions thesamewayinbothIDT
StandardandFWFTmodes.
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibitingfurtherreadoperations. WhenEFisHIGH,theFIFOisnotempty.See
Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT
StandardMode),fortherelevanttiminginformation.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
LOWatthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalid
ontheoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read(RCLKwithREN =LOW). The previous data stays atthe outputs,
indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
LOWagain.SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming
information.
OUTPUTENABLE(OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
data fromthe outputregister. When OE is HIGH, the outputdata bus (Q
into a high impedance state.
n)goes
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
EF/OR is synchronous and updated on the rising edge of RCLK.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT intheFIFO.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 2.
mode, OR is a triple register-buffered output.
SeeFigure17,ProgrammableAlmost-EmptyFlagTiming(IDTStandard
andFWFTMode),fortherelevanttiminginformation.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are HALF-FULL FLAG (HF)
PAE is synchronous and updated on the rising edge of RCLK.
performed after reset (MRS), PAF will go LOW after (D - m)words are written
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
totheFIFO.ThePAFwillgoLOWafter(262,144-m)writesfortheIDT72V2101 beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
and (524,288-m) writes for the IDT72V2111. The offset “m” is the full offset thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (262,145-m) writes for the HIGH.
IDT72V2101 and (524,289-m) writes for the IDT72V2111, where m is the
full offset value. The default setting for this value is stated in the footnote PRS), HF willgoLOWafter(D/2 + 1)writes tothe FIFO, where D=262,144
of Table 2.
SeeFigure16,ProgrammableAlmost-FullFlagTiming(IDTStandardand
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
In IDT Standard mode, if no reads are performed after reset (MRS or
for the IDT72V2101 and 524,288 for the IDT72V2111.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 262,145 for the
IDT72V2101 and 524,289 for the IDT72V2111.
FWFTMode),fortherelevanttiminginformation.
PAF is synchronous and updated on the rising edge of WCLK.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO and WCLK, it is considered asynchronous.
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset DATA OUTPUTS (Q0-Q8)
value. The default setting for this value is stated in the footnote of Table 1.
(Q0 - Q8) are data outputs for 9-bit wide data.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
tRS
MRS
REN
WEN
tRSS
tRSR
tRSR
tRSS
tRSR
t
FWFT
FWFT/SI
LD
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4669 drw 08
Figure 5. Master Reset Timing
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
t
RSS
RSS
t
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4669 drw 09
Figure 6. Partial Reset Timing
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
t
CLK
t
CLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4669 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW1(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4669 drw 11
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4669 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. D = 262,144
for the IDT72V2101 and 524,288 for the IDT72V2111.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 11. Retransmit Timing (IDT Standard Mode)
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
3
1
2
t
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENS
tRTS
REN
- Q
t
A
t
A
tA
A
(4)
(4)
(4)
Q0
n
Wx
Wx+1
W2
W
1
W
3
W4
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
tREF
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4669 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
t
LDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4669 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 17 for the IDT72V2101 and X = 18 for the IDT72V2111.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAF OFFSET
(MSB)
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
4669 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
RCLK
t
t
LDS
tLDH
t
LDH
LD
t
ENH
ENS
tENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
DATA IN OUTPUT REGISTER
Q0 - Q7
4669 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
tPAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4669 drw 19
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111.
In FWFT mode: D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
3.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
PAE
t
PAE
t
SKEW2
1
2
1
2
RCLK
t
ENS
tENH
4669 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
D-1
,
D-1
D-1
2
[
2
+ 2]
words in FIFO(2)
[
+ 1
]
words in FIFO(2)
[
2
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4669 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111.
2. For FWFT mode: D = maximum FIFO depth. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
problems canbe avoidedbycreatingcomposite flags, thatis, ANDingEF of
every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
compositeflags canbecreatedbyORingORofeveryFIFO,andseparately
ORing IR of every FIFO.
Figure 19 demonstrates a width expansion using two IDT72V2101/
72V2111devices. D0-D8fromeachdeviceforman18-bitwideinputbusand
Q0-Q8 fromeachdeviceforman18-bitwideoutputbus.Anywordwidthcan
beattainedbyaddingadditionalIDT72V2101/72V2111devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertiontovarybyonecyclebetweenFIFOs. InIDTStandardmode,such
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V2101
72V2111
IDT
72V2101
72V2111
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4669 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 262,144 x 18 and 524,288 x 18 Width Expansion
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
READ ENABLE
OR
WEN
REN
IDT
72V2101
72V2111
IDT
72V2101
72V2111
INPUT READY
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4669 drw 23
Figure 20. Block Diagram of 524,288 x 9 and 1,048,576 x 9 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
The IDT72V2101 can easily be adapted to applications requiring depths clock,fortheORflag.
greaterthan262,144and524,288fortheIDT72V2111witha9-bitbuswidth.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
InFWFTmode,theFIFOscanbeconnectedinseries(thedataoutputsofone depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
FIFOconnectedtothedatainputsofthenext)withnoexternallogicnecessary. wordswrittentotheconfiguration.
Theresultingconfigurationprovidesatotaldepthequivalenttothesumofthe
depthsassociatedwitheachsingleFIFO. Figure20 showsadepthexpansion configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
usingtwoIDT72V2101/72V2111devices. movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
The first free location created by reading from a full depth expansion
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
in the depth expansion configuration. The first word written to an empty towriteawordtofillit.
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
appears at the outputs of the last FIFO in the chain–no read operation is FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
necessarybutthe RCLKofeachFIFOmustbe free-running. Eachtime the the sumofthe delays foreachindividualFIFO:
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's where N is the number of FIFOs in the expansion and TWCLK is the WCLK
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
for each individual FIFO:
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1 endofthechainandfreelocations tothebeginningofthechain.
26
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Green
G
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Commercial Only
PF
10
15
20
Clock Cycle Time (tCLK
)
Com'l & Ind'l
Speed in Nanoseconds
Commercial Only
Low Power
L
72V2101 262,144 x 9 — 3.3V SuperSyncFIFO
72V2111 524,288 x 9 — 3.3V SuperSyncFIFO
4669 drw24
NOTE:
1. Industrial temperature range product for the 15ns is available as a standard device.
DATASHEETDOCUMENTHISTORY
9/14/2000
12/18/2000
03/27/2001
12/01/2008
pgs. 5.
pgs. 5, 6 and 27.
pgs. 6 and 27.
pg. 27.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
27
相关型号：
©2020 ICPDF网 联系我们和版权申明