IDT72V261LA20PF9 [IDT]
FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, TQFP-64;
| 型号： | IDT72V261LA20PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, TQFP-64 先进先出芯片 |
| 文件： | 总27页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SuperSync FIFO™
16,384 x 9
32,768 x 9
IDT72V261LA
IDT72V271LA
FEATURES:
• Program partial flags by either serial or parallel means
• Choose among the following memory organizations:
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
IDT72V261LA
IDT72V271LA
—
—
16,384 x 9
32,768 x 9
• Pin-compatible with the IDT72V281/72V291 and IDT72V2101/
72V2111SuperSync FIFOs
• Functionally compatible with the 5 Volt IDT72261/72271 family
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• 5V input tolerant
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
DESCRIPTION:
The IDT72V261LA/72V271LA are functionally compatible versions of
the IDT72261/72271 designed to run off a 3.3V supply for very low power
consumption. The IDT72V261LA/72V271LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and
FUNCTIONAL BLOCK DIAGRAM
D0 -D8
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
16,384 x 9
32,768 x 9
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0 -Q8
4673 drw 01
OE
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2002
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4673/2
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SuperSync FIFOs are particularly appropriate for network, video, tele-
communications, data communications and other applications that need to
buffer large amounts of data.
DESCRIPTION (CONTINUED)
write controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output
Enable (OE) input is provided for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from
0 to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
• The limitation of the frequency of one clock input with respect to the
other has been removed. The Frequency Select pin (FS) has been
removed, thus it is no longer necessary to select which of the two clock
inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short.
(The variable clock cycle counting delay associated with the latency
period found on previous SuperSync devices has been eliminated on
this SuperSync family.)
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
WEN
SEN
DC(1)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
VCC
4
VCC
5
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
6
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
7
8
9
10
11
12
13
14
15
16
Q7
Q6
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4673 drw 02
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
2
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn. REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and
write pointers are set to the first location of the FIFO. The FWFT pin
selects IDT Standard mode or FWFT mode. The LD pin selects either a
partial flag default setting of 127 with parallel programming or a partial flag
default setting of 1,023 with serial programming. The flags are updated
according to the timing mode and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
DESCRIPTION (CONTINUED)
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to
the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked
directly to the data output lines after three transitions of the RCLK signal. A
REN does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is re-
quired.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF
and FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by acti-
vating control inputs) will immediately take the device out of the power
down state.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table 1 and Table 2.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.
The IDT72V261LA/72V271LA are fabricated using IDT’s high speed
submicron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72V261LA
72V271LA
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4673 drw 03
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
3
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D8
Name
Data Inputs
I/O
I
Description
Data inputs for a 9-bit bus.
MRS
PRS
RT
Master Reset
Partial Reset
Retransmit
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.
I
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel),
and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the first
physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN
RCLK
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets
from the programmable registers.
REN
OE
SEN
LD
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
DuringMasterReset, LD selects one oftwopartialflagdefaultoffsets (127or1,023)anddetermines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO
memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there
is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not
there is valid data available at the outputs.
Programmable
Almost-Full Flag
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of
the FIFO minus the full offset value m, which is stored in the Full Offset register. There are two
possible default values for m: 127 or 1,023.
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored
in the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
Q0–Q8
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bus
VCC
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
4
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with respect to GND
–0.5 to +5
V
Symbol
VCC
Parameter
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Unit
V
Supply Voltage (Com’l/Ind’l)
Supply Voltage (Com’l/Ind’l)
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
GND
VIH
V
Input High Voltage (Com’l/Ind’l) 2.0
5.0
0.8
70
V
DC Output Current
mA
(1)
VIL
Input Low Voltage (Com’l/Ind’l)
0
V
TA
TA
Operating Temperature
Commercial
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Operating Temperature
Industrial
0
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 03.V, TA = 0°C to + 70°C; Industrial: VCC = 3.3V ± 03.V, TA = -40°C to +85°C)
IDT72V261LA
IDT72V271LA
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
Input Leakage Current
Output Leakage Current
–1
1
µA
µA
V
(3)
ILO
–10
2.4
—
10
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
0.4
V
(4,5,6)
ICC1
Active Power Supply Current
Standby Current
—
—
55
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 10 + 0.95*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
IDT72V261LA10
IDT72V271LA10
Com’l & Ind’l(2)
IDT72V261LA15
IDT72V271LA15
Commercial
IDT72V261LA20
IDT72V271LA20
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Min.
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6
Min.
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
Min.
—
2
Max.
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
tA
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
20
8
Clock High Time
Clock Low Time
6
8
Data Setup Time
4
5
tDH
Data Hold Time
0.5
3
1
1
tENS
tENH
tLDS
tLDH
tRS
Enable Setup Time
Enable Hold Time
Load Setup Time
4
5
0.5
3
1
1
4
5
Load Hold Time
0.5
10
10
10
—
0
1
1
Reset Pulse Width(3)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
Retransmit Setup Time
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
3
4
5
(4)
Output Enable to Output in Low Z
Output Enable to Output Valid
0
0
0
2
3
3
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
Output Enable to Output in High Z
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
10
Read Clock to PAE
Clock to HF
tSKEW1
Skew time between RCLK and WCLK for
FF/IR
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
Skew time between RCLK and WCLK for
12
60
—
—
15
60
—
—
20
60
—
—
ns
ns
tSKEW3
EF/OR
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns speed grade is available as a standard device.
All other speed grades are available by special order.
3.3V
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
330Ω
D.U.T.
AC TEST CONDITIONS
30pF*
510Ω
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4673 drw 04
1.5V
1.5V
* Includes jig and scope capacitances.
See Figure 1
Figure 2. Output Load
6
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause
the FIFO to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations. REN is
ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in
Figure 7, 8 and 11.
FUNCTIONAL DESCRIPTION
TIMING MODES:
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
The IDT72V261LA/72V271LA support two different timing modes of
operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during Master
Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO. It also uses the
Full Flag function (FF) to indicate whether or not the FIFO has any free
space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable
(REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode
will be selected. This mode uses Output Ready (OR) to indicate whether
or not there is valid data at the data outputs (Qn). It also uses Input
Ready (IR) to indicate whether or not the FIFO has any free space for
writing. In the FWFT mode, the first word written to an empty FIFO
goes directly to Qn after three RCLK rising edges, REN = LOW is not
necessary. Subsequent words must be accessed using the Read En-
able (REN) and RCLK.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in
the manner outlined in Table 2. To write data into to the FIFO, WEN
must be LOW. Data presented to the DATA IN lines will be clocked into
the FIFO on subsequent transitions of WCLK. After the first write is
performed, the Output Ready (OR) flag will go LOW. Subsequent writes
will continue to fill up the FIFO. PAE will go HIGH after n + 2 words
have been loaded into the FIFO, where n is the empty offset value. The
default setting for this value is stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no
read operations were taking place, the HF would toggle to LOW once
the 8,194th word for the IDT72V261LA and 16,386th word for the
IDT72V271LA, respectively was written into the FIFO. Continuing to
write data into the FIFO will cause the PAF to go LOW. Again, if no
reads are performed, the PAF will go LOW after (16,385-m) writes for
the IDT72V261LA and (32,769-m) writes for the IDT72V271LA, where
m is the full offset value. The default setting for this value is stated in
the footnote of Table 2.
Various signals, both input and output signals operate differently
depending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in
the manner outlined in Table 1. To write data into to the FIFO, Write
Enable (WEN) must be LOW. Data presented to the DATA IN lines will
be clocked into the FIFO on subsequent transitions of the Write Clock
(WCLK). After the first write is performed, the Empty Flag (EF) will go
HIGH. Subsequent writes will continue to fill up the FIFO. The Program-
mable Almost-Empty flag (PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where n is the empty offset value. The
default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable
Flag Offset Loading.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibit-
ing further write operations. If no reads are performed after a reset, IR
will go HIGH after D writes to the FIFO. D = 16,385 writes for the
IDT72V261LA and 32,769 writes for the IDT72V271LA, respectively.
Note that the additional word in FWFT mode is due to the capacity of
the memory plus output register.
If one continued to write data into the FIFO, and we assumed no
read operations were taking place, the Half-Full flag (HF) would toggle
to LOW once the 8,193th word for IDT72V261LA and 16,385th word for
IDT72V271LA respectively was written into the FIFO. Continuing to
write data into the FIFO will cause the Programmable Almost-Full flag
(PAF) to go LOW. Again, if no reads are performed, the PAF will go
LOW after (16,384-m) writes for the IDT72V261LA and (32,768-m) writes
for the IDT72V271LA. The offset “m” is the full offset value. The default
setting for this value is stated in the footnote of Table 1. This parameter
is also user programmable. See section on Programmable Flag Offset
Loading.
If the FIFO is full, the first read operation will cause the IR flag to go
LOW. Subsequent read operations will cause the PAF and HF to go
HIGH at the conditions described in Table 2. If further read operations
occur, without write operations, the PAE will go LOW when there are n
+ 1 words in the FIFO, where n is the empty offset value. Continuing
read operations will cause the FIFO to become empty. When the last
word has been read from the FIFO, OR will go HIGH inhibiting further
read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9,
10 and 12.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting
further write operations. If no reads are performed after a reset, FF will
go LOW after D writes to the FIFO. D = 16,384 writes for the
IDT72V261LA and 32,768 for the IDT72V271LA, respectively.
7
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
values, and in addition, sets a default PAE offset value of 07FH (a
threshold 127 words from the empty boundary), and a default PAF
offset value of 07FH (a threshold 127 words from the full boundary).
See Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read
the currentoffsetvalues. Itis onlypossible toreadoffsetvalues via parallel
read.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming
has been selected.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The
IDT72V261LA/72V271LA has internal registers for these offsets. De-
fault settings are stated in the footnotes of Table 1 and Table 2. Offset
values can be programmed into the FIFO in one of two ways; serial or
parallel loading method. The selection of the loading method is done
using the LD (Load) pin. During Master Reset, the state of the LD input
determines whether serial or parallel flag offset programming is en-
abled. A HIGH on LD during Master Reset selects serial loading of
offset values and in addition, sets a default PAE offset value of 3FFH (a
threshold 1,023 words from the empty boundary), and a default PAF
offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on LD during Master Reset selects parallel loading of offset
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72V261LA
IDT72V261LA
FF PAF HF PAE EF
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
(n + 1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m)(2) to 16,383
16,384
(n + 1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) (2) to 32,767
32,768
H
H
H
H
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72V271LA
IDT72V271LA
FF PAF HF PAE EF
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to n+1 (1)
1 to n+1 (1)
Number of
Words in
FIFO(1)
(n + 2) to 8,193
8,194 to (16,385-(m+1))(2)
(16,385-m) to 16,384
16,385
(n + 2) to 16,385
16,386 to (32,769-(m+1)) (2)
(32,769-m) (2) to 32,768
32,769
H
H
H
H
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA 16,384 x 9 − BIT
IDT72V271LA 32,768 x 9 − BIT
7
8
7
0
8
0
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
0
0
8
8
8
8
5
0
0
6
EMPTY OFFSET (MSB) REG.
00H
EMPTY OFFSET (MSB) REG.
00H
7
7
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
0
5
8
0
6
FULL OFFSET (MSB) REG.
00H
FULL OFFSET (MSB) REG.
00H
4673 drw 06
Figure 3. Offset Register Location and Default Values
WCLK
RCLK
Selection
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72V261LA
30 bits for the 72V271LA
X
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
No Operation
Write Memory
X
1
1
0
1
1
X
X
X
X
Read Memory
No Operation
1
1
X
1
0
1
X
X
X
4673 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
Write operations to the FIFO are allowed before and during the paral-
If Serial Programming mode has been selected, as described above, lel programming sequence. In this case, the programming of all offset
then programming of PAE and PAF values can be achieved by using a registers does not have to occur at one time. One, two or more offset
combination of the LD, SEN, WCLK and SI input pins. Programming registers can be written and then by bringing LD HIGH, write operations
PAE and PAF proceeds as follows: when LD and SEN are set LOW, can be redirected to the FIFO memory. When LD is set LOW again,
data on the SI input are written, one bit for each WCLK rising edge, and WEN is LOW, the next offset register in sequence is written to. As
starting with the Empty Offset LSB and ending with the Full Offset MSB. an alternative to holding WEN LOW and toggling LD, parallel program-
A total of 28 bits for the IDT72V261LA and 30 bits for the IDT72V271LA. ming can also be interrupted by setting LD LOW and toggling WEN.
See Figure 13, Serial Loading of Programmable Flag Registers, for the
timing diagram for this mode.
Note that the status of a partial flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming
Using the serial method, individual registers cannot be programmed has begun, a partial flag output will not be valid until the appropriate
selectively. PAE and PAF can show a valid status only after the com- offset word has been written to the register(s) pertaining to that flag.
plete set of bits (for all offset registers) has been entered. The registers Measuring from the rising WCLK edge that achieves the above criteria;
can be reprogrammed as long as the complete set of new offset bits is PAF will be valid after two more rising WCLK edges plus tPAF, PAE will
entered. When LD is LOW and SEN is HIGH, no serial write to the be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
registers can occur.
The act of reading the offset registers employs a dedicated read
Write operations to the FIFO are allowed before and during the serial offset register pointer. The contents of the offset registers can be read
programming sequence. In this case, the programming of all offset bits on the Q0-Qn pins when LD is set LOW and REN is set LOW. For the
does not have to occur at once. A select number of bits can be written IDT72V261LA and IDT72V271LA, data are read via Qn from the Empty
to the SI input and then, by bringing LD and SEN HIGH, data can be Offset LSB Register on the first LOW-to-HIGH transition of RCLK. Upon
written to FIFO memory via Dn by toggling WEN. When WEN is brought the second LOW-to-HIGH transition of RCLK, data are read from the
HIGH with LD and SEN restored to a LOW, the next offset bit in se- Empty Offset MSB Register. Upon the third LOW-to-HIGH transition of
quence is written to the registers via SI. If an interruption of serial RCLK, data are read from the Full Offset LSB Register. Upon the
programming is desired, it is sufficient either to set LD LOW and deacti- fourth LOW-to-HIGH transition of RCLK, data are read from the Full
vate SEN or to set SEN LOW and deactivate LD. Once LD and SEN Offset MSB Register. The fifth transition of RCLK reads, once again,
are both restored to a LOW level, serial offset programming continues.
from the Empty Offset LSB Register. See Figure 15, Parallel Read of
From the time serial programming has begun, neither partial flag will Programmable Flag Registers for the IDT72V261LA, for the timing dia-
be valid until the full set of bits required to fill all the offset registers has gram for this mode.
been written. Measuring from the rising WCLK edge that achieves the
It is permissible to interrupt the offset register read sequence with
above criteria; PAF will be valid after two more rising WCLK edges plus reads or writes to the FIFO. The interruption is accomplished by
tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE deasserting REN, LD, or both together. When REN and LD are restored
plus tSKEW2.
to a LOW level, reading of the offset registers continues where it left
off. It should be noted, and care should be taken from the fact that
when a parallel read of the flag offsets is performed, the data word that
was present on the output lines Qn will be overwritten.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
Parallel reading of the offset registers is always permitted regardless
of which timing mode (IDT Standard or FWFT modes) has been se-
lected.
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. For the
IDT72V261LA and the IDT72V271LA, programming PAE and PAF pro-
ceeds as follows: when LD and WEN are set LOW, data on the inputs RETRANSMIT OPERATION
Dn are written into the Empty Offset LSB Register on the first LOW-to-
The Retransmit operation allows data that has already been read to
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of be accessed again. There are two stages: first, a setup procedure that
WCLK, data are written into the Empty Offset MSB Register. Upon the resets the read pointer to the first location of memory, then the actual
third LOW-to-HIGH transition of WCLK, data are written into the Full retransmit, which consists of reading out the memory contents, starting
Offset LSB Register. Upon the fourth LOW-to-HIGH transition of WCLK, at the beginning of memory.
data are written into the Full Offset MSB Register. The fifth transition of
Retransmit setup is initiated by holding RT LOW during a rising RCLK
WCLK writes, once again, to the Empty Offset LSB Register. See Fig- edge. REN and WEN must be HIGH before bringing RT LOW. At least
ure 14, Parallel Loading of Programmable Flag Registers for the one word, but no more than D - 2 words should have been written into
IDT72V261LA, for the timing diagram for this mode.
the FIFO between Reset (Master or Partial) and the time of Retransmit
The act of writing offsets in parallel employs a dedicated write offset setup. D = 16,384 for the IDT72V261LA and D = 32,768 for the
register pointer. The act of reading offsets employs a dedicated read IDT72V271LA in IDT Standard mode. In FWFT mode, D = 16,385 for
offset register pointer. The two pointers operate independently; how- the IDT72V261LA and D = 32,769 for the IDT72V271LA.
ever, a read and a write should not be performed simultaneously to the
If IDT Standard mode is selected, the FIFO will mark the beginning of
offset registers. A Master Reset initializes both pointers to the Empty the Retransmit setup by setting EF LOW. The change in level will only
Offset (LSB) register. A Partial Reset has no effect on the position of be noticeable if EF was HIGH before setup. During this period, the
these pointers.
internal read pointer is initialized to the first location of the RAM array.
10
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
When EF goes HIGH, Retransmit setup is complete and read opera- on REN is necessary. Reading all subsequent words requires a LOW
tions may begin starting with the first location in memory. Since IDT on REN to enable the rising edge of RCLK. See Figure 12, Retransmit
Standard mode is selected, every word read including the first word Timing (FWFT Mode), for the relevant timing diagram.
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), HF and PAF flags begin with the rising edge of RCLK that RT is setup.
for the relevant timing diagram. PAE is synchronized to RCLK, thus on the second rising edge of RCLK
For either IDT Standard mode or FWFT mode, updating of the PAE,
If FWFT mode is selected, the FIFO will mark the beginning of the after RT is setup, the PAE flag will be updated. HF is asynchronous,
Retransmit setup by setting OR HIGH. During this period, the internal thus the rising edge of RCLK that RT is setup will update HF. PAF is
read pointer is set to the first location of the RAM array.
synchronized to WCLK, thus the second rising edge of WCLK that
When OR goes LOW, Retransmit setup is complete; at the same occurs tSKEW after the rising edge of RCLK that RT is setup will update
time, the contents of the first location appear on the outputs. Since PAF. RT is synchronized to RCLK.
FWFT mode is selected, the first word appears on the outputs, no LOW
11
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RETRANSMIT (RT)
SIGNAL DESCRIPTION
The Retransmit operation allows data that has already been read to
be accessed again. There are two stages: first, a setup procedure that
resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting
at the beginning of the memory.
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only
be noticeable if EF was HIGH before setup. During this period, the
internal read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode),
for the relevant timing diagram.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to
a LOW state. This operation sets the internal read and write pointers to
the first location of the RAM array. PAE will go LOW, PAF will go
HIGH, and HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go
HIGH. If FWFT is HIGH, then the First Word Fall Through mode
(FWFT), along with IR and OR, are selected. OR will go HIGH and IR
will go LOW.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal
read pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same
time, the contents of the first location appear on the outputs. Since
FWFT mode is selected, the first word appears on the outputs, no LOW
on REN is necessary. Reading all subsequent words requires a LOW
on REN to enable the rising edge of RCLK. See Figure 12, Retransmit
Timing (FWFT Mode), for the relevant timing diagram.
If LD is LOW during Master Reset, then PAE is assigned a threshold
127 words from the empty boundary and PAF is assigned a threshold
127 words from the full boundary; 127 words corresponds to an offset
value of 07FH. Following Master Reset, parallel loading of the offsets
is permitted, but not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a thresh-
old 1,023 words from the empty boundary and PAF is assigned a thresh-
old 1,023 words from the full boundary; 1,023 words corresponds to an
offset value of 3FFH. Following Master Reset, serial loading of the
offsets is permitted, but not parallel loading.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
This is a dual purpose pin. During Master Reset, the state of the
FWFT/SI input determines whether the device will operate in IDT Stan-
dard mode or First Word Fall Through (FWFT) mode. If, at the time of
Master Reset, FWFT/SI is LOW, then IDT Standard mode will be se-
lected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing.
During a Master Reset, the output register is initialized to all zeroes.
A Master Reset is required after power up, before a write operation can
take place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to
a LOW state. As in the case of the Master Reset, the internal read and
write pointers are set to the first location of the RAM array, PAE goes
LOW, PAF goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard
mode or First Word Fall Through, that mode will remain selected. If the
IDT Standard mode is active, then FF will go HIGH and EF will go
LOW. If the First Word Fall Through mode is active, then OR will go
HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently ac-
tive at the time of Partial Reset is also retained. The output register is
initialized to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
In IDT Standard mode, every word read from the FIFO, including the
first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode
will be selected. This mode uses Output Ready (OR) to indicate whether
or not there is valid data at the data outputs (Qn). It also uses Input
Ready (IR) to indicate whether or not the FIFO memory has any free
space for writing. In the FWFT mode, the first word written to an empty
FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is
n
o
t
necessary. Subsequent words must be accessed using the Read En-
able (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE
and PAF offsets into the programmable registers. The serial input
function can only be used when the serial loading method has been
selected during Master Reset. Serial programming using the FWFT/SI
pin functions the same way in both IDT Standard and FWFT modes.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
12
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial programming of the
setup and hold times must be met with respect to the LOW-to-HIGH offset registers. The serial programming method must be selected
transition of the WCLK. It is permissible to stop the WCLK. Note that during Master Reset. SEN is always used in conjunction with LD.
while WCLK is idle, the FF/IR, PAF and HF flags will not be updated. When these lines are both LOW, data at the SI input can be loaded into
(Note that WCLK is only capable of updating HF flag to LOW.) The the program register one bit for each LOW-to-HIGH transition of WCLK.
Write and Read Clocks can either be independent or coincident.
(See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in
both IDT Standard and FWFT modes.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO
RAM array on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAM array sequentially and independently of OUTPUT ENABLE (OE)
any ongoing read operation.
When Output Enable is enabled (LOW), the parallel output buffers
When WEN is HIGH, no new data is written in the RAM array on receive data from the output register. When OE is HIGH, the output
each WCLK cycle.
data bus (Qn) goes into a high impedance state.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF is updated by
two WCLK cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH,
inhibiting further write operations. Upon the completion of a valid read
cycle, IR will go LOW allowing a write to occur. The IR flag is updated
by two WCLK cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD
input determines one of two default offset values (127 or 1,023) for the
PAE and PAF flags, along with the method by which these offset regis-
ters can be programmed, parallel or serial. After Master Reset, LD
enables write operations to and read operations from the offset regis-
ters. Only the offset loading method currently selected can be used to
write to the registers. Offset registers can be read only in parallel.
A
LOW on LD during Master Reset selects a default PAE offset value of
07FH (a threshold 127 words from the empty boundary), a default PAF
offset value of 07FH (a threshold 127 words from the full boundary),
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data and parallel loading of other offset values. A HIGH on LD during
can be read on the outputs, on the rising edge of the RCLK input. It is Master Reset selects a default PAE offset value of 3FFH (a threshold
permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, 1,023 words from the empty boundary), a default PAF offset value of
PAE and HF flags will not be updated. (Note that RCLK is only capable 3FFH (a threshold 1,023 words from the full boundary), and serial load-
of updating the HF flag to HIGH.) The Write and Read Clocks can be ing of other offset values.
independent or coincident.
After Master Reset, the LD pin is used to activate the programming
process of the flag offset values PAE and PAF. Pulling LD LOW will
begin a serial loading or parallel load or read of these offset values.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into See Figure 4, Programmable Flag Offset Programming Sequence.
the output register on the rising edge of every RCLK cycle if the device
is not empty.
OUTPUTS:
When the REN input is HIGH, the output register holds the previous
FULL FLAG (FF/IR)
data and no new data is loaded into the output register. The data
outputs Q0-Qn maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the
first word written to an empty FIFO, must be requested using REN.
When the last word has been read from the FIFO, the Empty Flag (EF)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no
reads are performed after a reset (either MRS or PRS), FF will go LOW
after D writes to the FIFO (D = 16,384 for the IDT72V261LA and 32,768
will go LOW, inhibiting further read operations. REN is ignored when
for the IDT72V271LA). See Figure 7, Write Cycle and Full Flag Timing
the FIFO is empty. Once a write is performed, EF will go HIGH allowing
(IDT Standard Mode), for the relevant timing information.
a read to occur. The EF flag is updated by two RCLK cycles + tSKEW
In FWFT mode, the Input Ready (IR) function is selected. IR goes
LOW when memory space is available for writing in data. When there
after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automati-
cally goes to the outputs Qn, on the third valid LOW to HIGH transition
of RCLK + tSKEW after the first write. REN does not need to be
asserted LOW. In order to access all other words, a read must be
is no longer any free space left, IR goes HIGH, inhibiting further write
operations. If no reads are performed after a reset (either MRS or
PRS), IR will go HIGH after D writes to the FIFO (D = 16,385 for the
IDT72V261LA and 32,769 for the IDT72V271LA) See Figure 9, Write
executed using REN. The RCLK LOW to HIGH transition after the last
Timing (FWFT Mode), for the relevant timing information.
word has been read from the FIFO, Output Ready (OR) will go HIGH
The IR status not only measures the contents of the FIFO memory,
but also counts the presence of a word in the output register. Thus, in
with a true read (RCLK with REN = LOW), inhibiting further read opera-
tions. REN is ignored when the FIFO is empty.
13
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT mode, the total number of writes necessary to deassert IR is one
greater than needed to assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/
IR are double register-buffered outputs.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
EMPTY FLAG (EF/OR)
The Programmable Almost-Empty flag (PAE) will go LOW when the
This is a dual purpose pin. In the IDT Standard mode, the Empty FIFO reaches the almost-empty condition. In IDT Standard mode, PAE
Flag (EF) function is selected. When the FIFO is empty, EF will go will go LOW when there are n words or less in the FIFO. The offset “n”
LOW, inhibiting further read operations. When EF is HIGH, the FIFO is is the empty offset value. The default setting for this value is stated in
not empty. See Figure 8, Read Cycle, Empty Flag and First Word the footnote of Table 1.
Latency Timing (IDT Standard Mode), for the relevant timing informa-
tion.
In FWFT mode, the PAE will go LOW when there are n+1 words or
less in the FIFO. The default setting for this value is stated in the
In FWFT mode, the Output Ready (OR) function is selected. OR footnote of Table 2.
goes LOW at the same time that the first word written to an empty FIFO
See Figure 17, Programmable Almost-Empty Flag Timing (IDT
appears valid on the outputs. OR stays LOW after the RCLK LOW to Standard and FWFT Mode), for the relevant timing information.
HIGH transition that shifts the last word from the FIFO memory to the
outputs. OR goes HIGH only with a true read (RCLK with REN =
LOW). The previous data stays at the outputs, indicating the last word
was read. Further data reads are inhibited until OR goes LOW again.
See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In
FWFT mode, OR is a triple register-buffered output.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills
the FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or
equal to half of the total depth of the device; the rising RCLK edge that
accomplishes this condition sets HF HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where
D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
In FWFT mode, if no reads are performed after reset (MRS or PRS),
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the
FIFO reaches the almost-full condition. In IDT Standard mode, if no HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385
reads are performed after reset (MRS), PAF will go LOW after (D - m) for the IDT72V261LA and 32,769 for the IDT72V271LA.
words are written to the FIFO. The PAF will go LOW after (16,384-m)
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
writes for the IDT72V261LA and (32,768-m) writes for the IDT72V271LA. for the relevant timing information. Because HF is updated by both
The offset “m” is the full offset value. The default setting for this value is RCLK and WCLK, it is considered asynchronous.
stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (16,385-m) writes for DATA OUTPUTS (Q0-Q8)
the IDT72V261LA and (32,769-m) writes for the IDT72V271LA, where
m is the full offset value. The default setting for this value is stated in
the footnote of Table 2.
(Q0 - Q8) are data outputs for 9-bit wide data.
14
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
REN
t
RSS
RSS
tRSR
tRSR
tRSR
tRSR
t
WEN
FWFT/SI
LD
t
FWFT
t
RSS
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4673 drw 08
Figure 5. Master Reset Timing
15
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
t
RSS
RSS
t
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4673 drw 09
Figure 6. Partial Reset Timing
16
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
tDS
tDH
tDS
tDH
D
X
DX+1
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
tA
t
A
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4673 drw10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW3(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4673 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
18
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
2
RCLK
t
ENH
t
ENS
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4673 drw 14
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
tRTS
REN
- Q
t
A
tA
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
(5)
tREF
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4673 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. Nomore thanD-2words maybe writtentothe FIFObetweenReset(MasterorPartial)andRetransmitsetup. Therefore, IR willbe LOWthroughoutthe Retransmitsetupprocedure.
D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4673 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 13 for the IDT72V261LA and X = 14 for the IDT72V271LA.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
tCLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4673 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
LDH
LD
t
ENS
tENH
t
ENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT
REGISTER
PAE OFFSET
(MSB)
Q0 - Q7
4673 drw 18
NOTE:
1. OE = LOW.
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
22
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
t
PAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4673 drw 19
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
In FWFT mode: D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
PAE
t
PAE
t
SKEW2
1
2
1
2
RCLK
t
ENS
tENH
4673 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D-1
[
+ 2]
words in FIFO(2)
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4673 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
composite flags, that is, ANDing EF of every FIFO, and separately
ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 21 demonstrates a width expansion using two IDT72V261LA/
72V271LA devices. D0 - D8 from each device form a 18-bit wide input
bus and Q0-Q8 from each device form a 18-bit wide output bus. Any
word width can be attained by adding additional IDT72V261LA/72V271LA
devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the EF and FF functions in IDT
Standard mode and the IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs.
In IDT Standard mode, such problems can be avoided by creating
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72V261LA
72V271LA
PROGRAMMABLE (PAE)
72V261LA
72V271LA
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4673 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
24
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
that the tSKEW3 specification is not met between WCLK and transfer
The IDT72V261LA can easily be adapted to applications requiring clock, or RCLK and transfer clock, for the OR flag.
depths greater than 16,384 and 32,768 for the IDT72V271LA with a 9-
The "ripple down" delay is only noticeable for the first word written to
bit bus width. In FWFT mode, the FIFOs can be connected in series an empty depth expansion configuration. There will be no delay evi-
(the data outputs of one FIFO connected to the data inputs of the next) dent for subsequent words written to the configuration.
with no external logic necessary. The resulting configuration provides
The first free location created by reading from a full depth expansion
a total depth equivalent to the sum of the depths associated with each configuration will "bubble up" from the last FIFO to the previous one
single FIFO. Figure 22 shows a depth expansion using two until it finally moves into the first FIFO of the chain. Each time a free
IDT72V261LA/72V271LA devices.
Care should be taken to select FWFT mode during Master Reset for LOW, enabling the preceding FIFO to write a word to fill it.
all FIFOs in the depth expansion configuration. The first word written For a full expansion configuration, the amount of time it takes for IR
location is created in one FIFO of the chain, that FIFO's IR line goes
to an empty configuration will pass from one FIFO to the next ("ripple of the first FIFO in the chain to go LOW after a word has been read from
down") until it finally appears at the outputs of the last FIFO in the the last FIFO is the sum of the delays for each individual FIFO:
chain–no read operation is necessary but the RCLK of each FIFO must
be free-running. Each time the data word appears at the outputs of
one FIFO, that device's OR line goes LOW, enabling a write to the next
FIFO in line.
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the
For an empty expansion configuration, the amount of time it takes for WCLK period. Note that extra cycles should be added for the possibility
OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on that the tSKEW1 specification is not met between RCLK and transfer
the last FIFO's outputs) after a word has been written to the first FIFO clock, or WCLK and transfer clock, for the IR flag.
is the sum of the delays for each individual FIFO:
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly
as possible, to the end of the chain and free locations to the beginning
of the chain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the
RCLK period. Note that extra cycles should be added for the possibility
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
RCLK
WRITE ENABLE
INPUT READY
OR
WEN
REN
IDT
72V261LA
72V271LA
IDT
72V261LA
72V271LA
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4673 drw 23
Figure 20. Block Diagram of 32,768 x 9 and 65,536 x 9 Depth Expansion
25
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BLANK
I(1)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Commercial Only
10
15
20
Clock Cycle Time (tCLK
)
Com’l & Ind’l
Speed in Nanoseconds
Commercial Only
Low Power
LA
72V261
72V271
16,384 x 9 3.3V SuperSync FIFO
32,768 x 9 3.3V SuperSync FIFO
4673 drw 24
NOTE:
1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEET DOCUMENT HISTORY
04/25/2001
04/22/2002
pgs. 1, 5, 6 and 26.
pg. 17.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
26
3.3 VOLT CMOS SuperSync FIFO™
16,384 x 9
IDT72V261LA
IDT72V271LA
32,768 x 9
ADDENDUM
DIFFERENCES BETWEEN THE IDT72V261LA/72V271LA AND IDT72V261L/72V271L
IDT has improved the performance of the IDT72V261/72V271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA
part is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
Item
NEW PART
OLD PART
Comments
IDT72V261LA
IDT72V271LA
IDT72V261L
IDT72V271L
Pin #3
DC (Don’t Care) - There is
no restriction on WCLK and
RCLK. See note 1.
FS (Frequency Select)
In the LA part this pin must be tied
to either VCC or GND and must
not toggle after reset.
(4)
(3)
(4)
First Word Latency
60ns(2) + tREF + 1 TRCLK
tFWL = 10*Tf + 2TRCLK (ns) First word latency in the LA part is
1
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
First Word Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tFWL = 10*Tf + 3TRCLK (ns) First word latency in the LA part is
2
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(IDT Standard Mode)
60ns(2) + tREF + 1 TRCLK
tRTF1 = 14*Tf + 3TRCLK (ns) Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tRTF2 = 14*Tf + 4TRCLK (ns) Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
ICC1
55mA
20mA
150mA
15mA
Active supply current
Standby current
ICC2
Typical ICC1(5)
10 + 0.95*fS + 0.02*CL*fS(mA) Not Given
Typical ICC1 Current calculation
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is tSKEW3.
3. Tf is the period of the ‘selected clock’.
4. TRCLK is the cycle period of the read clock.
5. Typical ICC1 is based on VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).
IDT and the IDT logo are registered trademarks. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
27
2002 Integrated Device Technology, Inc.
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