IDT72V265LA10PFI [IDT]
3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18; 3.3伏的CMOS SuperSync FIFO 8,192 ×18 16,384 ×18
| 型号： | IDT72V265LA10PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| 文件： | 总27页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18
16,384 x 18
IDT72V255LA
IDT72V265LA
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and
writing simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
IDT72V255LA
IDT72V265LA
8,192 x 18
16,384 x 18
• Pin-compatible with the IDT72V275/72V285 and IDT72V295/
72V2105 SuperSync FIFOs
• Functionally compatible with the 5 Volt IDT72255/72265 family
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
DESCRIPTION:
• 5V input tolerant
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
TheIDT72V255LA/72V265LAarefunctionallycompatibleversionsofthe
IDT72255/72265 designed to run off a 3.3V supply for very low power
consumption. TheIDT72V255LA/72V265LAareexceptionallydeep,high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and
writecontrols. TheseFIFOsoffernumerousimprovementsoverprevious
SuperSyncFIFOs,includingthefollowing:
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother
has beenremoved. TheFrequencySelectpin(FS)has beenremoved,
thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK
or WCLK, is running at the higher frequency.
FUNCTIONAL BLOCK DIAGRAM
D0 -D17
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
FLAG
LOGIC
WRITE CONTROL
LOGIC
PAE
HF
FWFT/SI
RAM ARRAY
8,192 x 18
16,384 x 18
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
4672 drw 01
Q0 -Q17
OE
TheIDTlogoisaregisteredtrademarkandtheSuperSyncFIFOisatrademark ofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2001
1
2001 Integrated Device Technology, Inc
DSC-4672/1
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
and Read Enable (REN) input. Data is read from the FIFO on every rising
edgeofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovided
forthree-statecontroloftheoutputs.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
to fMAX with complete independence. There are no restrictions on the
frequencyofoneclockinputwithrespecttotheother.
DESCRIPTION (CONTINUED)
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento
anemptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync
family.)
SuperSync FIFOs are particularly appropriate for networking, video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
bufferlargeamountsofdata.
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
DC(1)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q17
Q16
GND
Q15
Q14
2
3
4
VCC
5
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
6
VCC
7
Q13
Q12
Q11
GND
Q10
Q9
8
9
10
11
12
13
14
15
16
Q8
Q7
Q6
D8
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4672 drw 02
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
NOTE:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For serial programming, SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
of RCLK can be used to read the offsets in parallel from Qn regardless of
whetherserialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
The Partial Reset (PRS) also sets the read and write pointers to the first
locationofthememory. However,thetimingmode,partialflagprogramming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand
offsetsineffect. PRSisusefulforresettingadeviceinmid-operation,when
reprogrammingpartialflagswouldbeundesirable.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V255LA/72V265LA are fabricated using IDT’s high speed
submicron CMOS technology.
DESCRIPTION (CONTINUED)
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOis clockeddirectly
tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted foraccessingthe first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFand
FF functions are selectedinIDTStandardmode. The IR and OR functions
areselectedinFWFTmode. HF,PAEandPAFarealwaysavailableforuse,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith
the LD pin during Master Reset.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72V255LA
72V265LA
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4672 drw 03
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
3
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
I/O
I
Description
DataInputs
MasterReset
Datainputsfora18-bitbus.
I
MRSinitializes the readandwrite pointers tozeroandsets the outputregisterto allzeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program
mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
RT
PartialReset
Retransmit
I
I
PRS initializes the readandwrite pointers tozeroandsets the outputregistertoallzeroes. During
PartialReset, the existingmode (IDTorFWFT), programmingmethod(serialorparallel), and
programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings. RT is useful to reread data from the first
physical location of the FIFO.
FWFT/SI
WCLK
FirstWordFall
Through/Serial In
I
I
DuringMasterReset, selects FirstWordFallThroughorIDTStandardmode. AfterMasterReset,
thispinfunctionsasaserialinputforloadingoffsetregisters
WriteClock
WhenenabledbyWEN, the risingedge ofWCLKwrites data intothe FIFOand offsets intothe
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN
RCLK
Write Enable
ReadClock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
WhenenabledbyREN, the risingedge ofRCLKreads data fromthe FIFOmemoryandoffsetsfrom
theprogrammableregisters.
REN
OE
SEN
LD
ReadEnable
OutputEnable
SerialEnable
Load
I
I
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
DuringMasterReset,LD selects one oftwopartialflagdefaultoffsets (127or1,023)anddetermines
the flagoffsetprogrammingmethod, serialorparallel. AfterMasterReset, this pinenables writingto
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pinmustbe tiedtoeitherVCC orGNDandmustnottoggle afterMasterReset.
FF/IR
Full Flag/
Input Ready
O
Inthe IDT Standard mode, the FF function is selected. FF indicates whetherornotthe FIFO
memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not
there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
OutputReady
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
memoryis empty. InFWFTmode, theOR functionis selected. OR indicates whetherornotthereis
validdataavailableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOWifthe numberofwords inthe FIFOmemoryis more thantotalwordcapacityofthe
FIFOminusthefulloffsetvaluem,whichisstoredintheFullOffsetregister. Therearetwopossible
default values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAEgoes LOWifthe numberofwords inthe FIFOmemoryis less thanoffsetn, whichis storedin
the EmptyOffsetregister. There are twopossible defaultvalues forn:127or1,023. Othervalues
forncanbe programmedintothe device.
HF
Q0–Q17
VCC
Half-FullFlag
DataOutputs
Power
O
O
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
Dataoutputsforan18-bitbus.
+3.3 Volt power supply pins.
GND
Ground
Groundpins.
4
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with respect to GND
–0.5 to +5
V
Symbol
VCC
Parameter
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Unit
V
Supply Voltage (Com’l/Ind’l)
Supply Voltage (Com’l/Ind’l)
Input High Voltage (Com’l/Ind’l)
Input Low Voltage (Com’l/Ind’l)
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
GND
VIH
V
2.0
5.0
0.8
70
V
DC Output Current
mA
(1)
VIL
V
NOTE:
TA
TA
OperatingTemperature
Commercial
0
0
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Industrial
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V255LA
IDT72V265LA
Com’l & Ind’l(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
–1
–10
2.4
—
1
µ A
µA
V
(3)
ILO
OutputLeakageCurrent
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
55
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 10 + 1.1*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data
switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC –0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC 3.3V ± 0.3V,TA = -40°C to +85°C)
Commercial
Com’l & Ind’l(2)
Commercial
IDT72V255LA10
IDT72V265LA10
IDT72V255LA15
IDT72V265LA15
IDT72V255LA20
IDT72V265LA20
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Min.
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
Min.
—
2
Max.
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
tA
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
20
8
Clock Low Time
6
8
Data Setup Time
4
5
tDH
Data Hold Time
0.5
3
1
1
tENS
tENH
tLDS
tLDH
tRS
Enable Setup Time
Enable Hold Time
Load Setup Time
4
5
0.5
3
1
1
4
5
Load Hold Time
Reset Pulse Width(3)
0.5
10
10
10
—
0
1
1
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
Retransmit Setup Time
—
—
—
6
3
4
5
(4)
Output Enable to Output in Low Z
Output Enable to Output Valid
0
0
0
2
3
3
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
Output Enable to Output in High Z
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
10
Read Clock to PAE
Clock to HF
tSKEW1
Skew time between RCLK and WCLK
—
for FF/IR
tSKEW2
tSKEW3
Skew time between RCLK and WCLK
for PAE and PAF
Skew time between RCLK and WCLK
12
60
—
—
15
60
—
—
20
60
—
—
ns
ns
for EF/OR
NOTES:
3.3V
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
330Ω
D.U.T.
AC TEST CONDITIONS
30pF*
Input Pulse Levels
GND to 3.0V
3ns
510Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
4672 drw 04
1.5V
Figure 2. Output Load
See Figure 2
* Includes jig and scope capacitances.
6
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause the
FIFO to become empty. When the last word has been read from the FIFO,
the EF will go LOW inhibiting further read operations. REN is
ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in
Figure 7, 8 and 11.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V255LA/72V265LA support two different timing modes of
operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during Master Re-
set, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depend-
ing on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the
FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 4,098th
word for the IDT72V255LA and 8,194th word for the IDT72V265LA,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (8,193-m) writes for the IDT72V255LA and (16,385-m)
writes for the IDT72V265LA, where m is the full offset value. The default
setting for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 8,193 writes for the IDT72V255LA
and 16,385 writes for the IDT72V265LA, respectively. Note that the addi-
tional word in FWFT mode is due to the capacity of the memory plus output
register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is ig-
nored when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty flag
(PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 4,097th word for IDT72V255LA and 8,193th word for
IDT72V265LA respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go
LOW. Again, if no reads are performed, the PAF will go LOW after (8,192-m)
writes for the IDT72V255LA and (16,384-m) writes for the IDT72V265LA.
The offset “m” is the full offset value. The default setting for this value is
stated in the footnote of Table 1. This parameter is also user programmable.
See section on Programmable Flag Offset Loading.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 8,192 writes for the IDT72V255LA and
16,384 for the IDT72V265LA, respectively.
7
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
value of 07FH (a threshold 127 words from the empty boundary), and a
Full and Empty Flag offset values are user programmable. The default PAF offset value of 07FH (a threshold 127 words from the full
IDT72V255LA/72V265LA has internal registers for these offsets. Default boundary). See Figure 3, Offset Register Location and Default Values.
settings are stated in the footnotes of Table 1 and Table 2. Offset values can
In addition to loading offset values into the FIFO, it also possible to read
be programmed into the FIFO in one of two ways; serial or parallel loading the current offset values. It is only possible to read offset values via parallel
method. The selection of the loading method is done using the LD (Load) read.
pin. During Master Reset, the state of the LD input determines whether
Figure 4, Programmable Flag Offset Programming Sequence, summa-
serial or parallel flag offset programming is enabled. A HIGH on LD during rizes the control pins and sequence for both serial and parallel program-
Master Reset selects serial loading of offset values and in addition, sets a ming modes. For a more detailed description, see discussion that follows.
default PAE offset value of 3FFH (a threshold 1,023 words from the empty
The offset registers may be programmed (and reprogrammed) any time
boundary), and a default PAF offset value of 3FFH (a threshold 1,023 after Master Reset, regardless of whether serial or parallel programming
words from the full boundary). A LOW on LD during Master Reset selects has been selected.
parallel loading of offset values, and in addition, sets a default PAE offset
TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE
72V255LA
72V265LA
FF PAF HF PAE EF
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
(n + 1) to 4,096
4,097 to (8,192–(m+1))
(n + 1) to 8,192
8,193 to (16,384–(m+1))
H
H
H
H
(8,192
–
m)(2) to 8,191
8,192
(16,384
–
m) (2) to 16,383
16,384
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 STATUS FLAGS FOR FWFT MODE
72V255LA
72V265LA
FF PAF HF PAE EF
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to n+1 (1)
1 to n+1 (1)
Number of
Words in
FIFO (1)
(n + 2) to 4,097
4,098 to (8,193–(m+1))(2)
(n + 2) to 8,193
8,194 to (16,385–(m+1)) (2)
H
H
H
H
(8,193
–
m) to 8,192
(16,385
–
m)(2) to16,384
16,385
8,193
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
4672 drw 05
8
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V255LA
8,192 x 18 - BIT
IDT72V265LA
16,384 x 18 - BIT
17
12
0
17
17
13
0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
17
12
0
13
0
FULL OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
4672 drw 06
Figure 3. Offset Register Location and Default Values
Selection
LD
WEN
SEN
WCLK
REN
RCLK
X
Parallel write to registers:
Empty Offset
0
0
1
1
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
0
0
1
1
1
0
X
0
1
Serial shift into registers:
26 bits for the 72V255LA
X
28 bits for the 72V265LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
X
1
1
1
1
0
X
1
1
X
X
X
X
1
X
0
1
X
X
X
X
X
4672 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
registers can be written and then by bringing LD HIGH, write operations
If Serial Programming mode has been selected, as described above, then can be redirected to the FIFO memory. When LD is set LOW again, and
programming of PAE and PAF values can be achieved by using a combi- WEN is LOW, the next offset register in sequence is written to. As an
nation of the LD, SEN, WCLK and SI input pins. Programming PAE and alternative to holding WEN LOW and toggling LD, parallel programming can
PAF proceeds as follows: when LD and SEN are set LOW, data on the SI also be interrupted by setting LD LOW and toggling WEN.
input are written, one bit for each WCLK rising edge, starting with the Empty
Note that the status of a partial flag (PAE or PAF) output is invalid during
Offset LSB and ending with the Full Offset MSB. A total of 26 bits for the the programming process. From the time parallel programming has
IDT72V255LA and 28 bits for the IDT72V265LA. See Figure 13, Serial begun, a partial flag output will not be valid until the appropriate offset word
Loading of Programmable Flag Registers, for the timing diagram for this has been written to the register(s) pertaining to that flag. Measuring from
mode.
Using the serial method, individual registers cannot be programmed se- after two more rising WCLK edges plus tPAF, PAE will be valid after the
lectively. PAE and PAF can show a valid status only after the complete set next two rising RCLK edges plus tPAE plus tSKEW2
of bits (for all offset registers) has been entered. The registers can be The act of reading the offset registers employs a dedicated read offset
reprogrammed as long as the complete set of new offset bits is entered. register pointer. The contents of the offset registers can be read on the
the rising WCLK edge that achieves the above criteria; PAF will be valid
.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Q
0
-Qn pins when LD is set LOW and REN is set LOW. Data are read via
Qn from the Empty Offset Register on the first LOW-to-HIGH transition of
Write operations to the FIFO are allowed before and during the serial RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are read
programming sequence. In this case, the programming of all offset bits from the Full Offset Register. The third transition of RCLK reads, once
does not have to occur at once. A select number of bits can be written to again, from the Empty Offset Register. See Figure 15, Parallel Read of
the SI input and then, by bringing LD and SEN HIGH, data can be written Programmable Flag Registers, for the timing diagram for this mode.
to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH
It is permissible to interrupt the offset register read sequence with reads
with LD and SEN restored to a LOW, the next offset bit in sequence is writ- or writes to the FIFO. The interruption is accomplished by deasserting
ten to the registers via SI. If an interruption of serial programming is de- REN, LD, or both together. When REN and LD are restored to a LOW level,
sired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN reading of the offset registers continues where it left off. It should be noted,
LOW and deactivate LD. Once LD and SEN are both restored to a LOW and care should be taken from the fact that when a parallel read of the flag
level, serial offset programming continues.
offsets is performed, the data word that was present on the output lines Qn
From the time serial programming has begun, neither partial flag will be will be overwritten.
valid until the full set of bits required to fill all the offset registers has been
Parallel reading of the offset registers is always permitted regardless of
written. Measuring from the rising WCLK edge that achieves the above which timing mode (IDT Standard or FWFT modes) has been selected.
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2
.
RETRANSMIT OPERATION
It is not possible to read the flag offset values in a serial mode.
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, which consists of reading out the memory contents, starting at the
then programming of PAE and PAF values can be achieved by using a beginning of memory.
combination of the LD, WCLK , WEN and Dn input pins. ProgrammingPAE
Retransmit setup is initiated by holding RT LOW during a rising RCLK
and PAF proceeds as follows: when LD and WEN are set LOW, data on edge. REN and WEN must be HIGH before bringing RT LOW. At least one
the inputs Dn are written into the Empty Offset Register on the first LOW-to- word, but no more than D –2 words should have been written into the
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, FIFO between Reset (Master or Partial) and the time of Retransmit setup.
data are written into the Full Offset Register. The third transition of WCLK D = 8,192 for the IDT72V255LA and D = 16,384 for the IDT72V265LA.
writes, once again, to the Empty Offset Register. See Figure 14, Parallel In FWFT mode, D = 8,193 for the IDT72V255LA and D = 16,385 for the
Loading of Programmable Flag Registers, for the timing diagram for this IDT72V265LA.
mode.
If IDT Standard mode is selected, the FIFO will mark the beginning of
The act of writing offsets in parallel employs a dedicated write offset the Retransmit setup by setting EF LOW. The change in level will only be
register pointer. The act of reading offsets employs a dedicated read offset noticeable if EF was HIGH before setup. During this period, the internal
register pointer. The two pointers operate independently; however, a read read pointer is initialized to the first location of the RAM array.
and a write should not be performed simultaneously to the offset registers.
A Master Reset initializes both pointers to the Empty Offset (LSB) register. may begin starting with the first location in memory. Since IDT Standard
A Partial Reset has no effect on the position of these pointers. mode is selected, every word read including the first word following
When EF goes HIGH, Retransmit setup is complete and read operations
Write operations to the FIFO are allowed before and during the parallel Retransmit setup requires a LOW on REN to enable the rising edge of RCLK.
programming sequence. In this case, the programming of all offset See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
registers does not have to occur at one time. One, two or more offset timing diagram.
10
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is
setup, the PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
rising edge of RCLK that RT is setup will update PAF. RT is synchronized to
RCLK.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
11
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at beginning of
the memory.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following Re-
transmit setup requires a LOW on REN to enable the rising edge of RCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Re-
transmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is neces-
sary. Reading all subsequent words requires a LOW on REN to enable the
rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for
the relevant timing diagram.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF
will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO memory. It also uses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a
LOW state. As in the case of the Master Reset, the internal read and write
pointers are set to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT
Standard mode is active, then FF will go HIGH and EF will go LOW. If the
First Word Fall Through mode is active, then OR will go HIGH, and IR will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
12
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
lines are both LOW, data at the SI input can be loaded into the program
register one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF is updated by two
WCLK cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH,
inhibiting further write operations. Upon the completion of a valid read
cycle, IR will go LOW allowing a write to occur. The IR flag is updated by
two WCLK cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output buffers
receive data from the output register. When OE is HIGH, the output data
bus (Qn) goes into a high impedance state.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD
input determines one of two default offset values (127 or 1,023) for the PAE
and PAF flags, along with the method by which these offset registers can be
programmed, parallel or serial. After Master Reset, LD enables write op-
erations to and read operations from the offset registers. Only the offset
loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on LD during Master
Reset selects a default PAE offset value of 07FH (a threshold 127 words
from the empty boundary), a default PAF offset value of 07FH (a threshold
127 words from the full boundary), and parallel loading of other offset
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a
default PAF offset value of 3FFH (a threshold 1,023 words from the full
boundary), and serial loading of other offset values.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can
be read on the outputs, on the rising edge of the RCLK input. It is permis-
sible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and
HF flags will not be updated. (Note that RCLK is only capable of updating
the HF flag to HIGH.) The Write and Read Clocks can be independent or
coincident.
After Master Reset, the LD pin is used to activate the programming
process of the flag offset values PAE and PAF. Pulling LD LOW will begin a
serial loading or parallel load or read of these offset values. See Figure 4,
Programmable Flag Offset Programming Sequence.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
OUTPUTS:
FULL FLAG (FF/IR)
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK
cycle.
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D writes
to the FIFO (D = 8,192 for the IDT72V255LA and 16,384 for the
IDT72V265LA). See Figure 7, Write Cycle and Full Flag Timing (IDT
Standard Mode), for the relevant timing information.
In the FWFT mode, the first word written to an empty FIFO automatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK +
tSKEW after the first write. REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
is empty.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write operations.
If no reads are performed after a reset (either MRS or PRS), IR will go
HIGH after D writes to the FIFO (D = 8,193 for the IDT72V255LA and
16,385 for the IDT72V265LA) See Figure 9, Write Timing (FWFT Mode),
for the relevant timing information.
The IR status not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected during
Master Reset. SEN is always used in conjunction with LD. When these
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
are double register-buffered outputs.
13
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
(EF) function is selected. When the FIFO is empty, EF will go LOW, reaches the almost-empty condition. In IDT Standard mode, PAE will go
inhibiting further read operations. When EF is HIGH, the FIFO is not empty. LOW when there are n words or less in the FIFO. The offset “n” is the
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing empty offset value. The default setting for this value is stated in the footnote
(IDT Standard Mode), for the relevant timing information.
of Table 1.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
In FWFT mode, the PAE will go LOW when there are n+1 words or less
LOW at the same time that the first word written to an empty FIFO appears in the FIFO. The default setting for this value is stated in the footnote of
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition Table 2.
that shifts the last word from the FIFO memory to the outputs. OR goes
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
HIGH only with a true read (RCLK with REN = LOW). The previous data dard and FWFT Mode), for the relevant timing information.
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (HF)
EF/OR is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, EF is a double register-buffered output. In FWFT FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-
mode, OR is a triple register-buffered output.
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets HF HIGH.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or
reaches the almost-full condition. In IDT Standard mode, if no reads are PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 8,192
performed after reset (MRS), PAF will go LOW after (D - m) words are for the IDT72V255LA and 16,384 for the IDT72V265LA.
written to the FIFO. The PAF will go LOW after (8,192-m) writes for the
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
IDT72V255LA and (16,384-m) writes for the IDT72V265LA. The offset “m” will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 8,193 for the
is the full offset value. The default setting for this value is stated in the IDT72V255LA and 16,385 for the IDT72V265LA.
footnote of Table 1.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
In FWFT mode, the PAF will go LOW after (8,193-m) writes for the for the relevant timing information. Because HF is updated by both RCLK
IDT72V255LA and (16,385-m) writes for the IDT72V265LA, where m is the and WCLK, it is considered asynchronous.
full offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
DATA OUTPUTS (Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
14
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
FWFT/SI
LD
t
RSR
t
FWFT
tRSS
t
RSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4672 drw 08
Figure 5. Master Reset Timing
15
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4672 drw 09
Figure 6. Partial Reset Timing
16
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4672 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENS
tENS
tENH
tENH
tENS
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW3(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4672 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
18
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4672 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 8,192 for IDT72V255LA and 16,384 for IDT72V265LA.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
1
2
4
RCLK
t
ENH
t
ENS
tENH
t
ENH
tRTS
REN
- Q
t
A
tA
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENH
t
ENS
RT
OR
(5)
tREF
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4672 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
tLDH
tLDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4672 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 12 for the IDT72V255LA and X = 13 for the IDT72V265LA.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
t
LDH
ENH
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAE
OFFSET
PAF
OFFSET
D0
- D15
4672 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
LDH
LD
t
ENS
t
ENH
t
ENH
REN
t
A
t
A
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
Q0
- Q15
4672 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
t
PAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4672 drw 19
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
In FWFT mode: D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
SKEW2
t
t
PAE
t
PAE
1
2
1
2
RCLK
t
ENS
tENH
4672 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D-1
[
+ 2]
words in FIFO(2)
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4672 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT Standard mode, such problems can be avoided by creating composite
flags, that is, ANDing EF of every FIFO, and separately ANDing FF of
every FIFO. In FWFT mode, composite flags can be created by ORing
OR of every FIFO, and separately ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72V255LA/
72V265LA devices. D0 - D17 from each device form a 36-bit wide input
bus and Q0-Q17 from each device form a 36-bit wide output bus. Any
word width can be attained by adding additional IDT72V255LA/72V265LA
devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the EF and FF functions in IDT
Standard mode and the IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs. In
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72V255LA
72V265LA
PROGRAMMABLE (PAE)
72V255LA
72V265LA
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4672 drw 22
Q0
- Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion
24
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
that the tSKEW3 specification is not met between WCLK and transfer clock,
The IDT72V255LA can easily be adapted to applications requiring depths or RCLK and transfer clock, for the OR flag.
greater than 8,192 and 16,384 for the IDT72V265LA with an 18-bit bus
The "ripple down" delay is only noticeable for the first word written to an
width. In FWFT mode, the FIFOs can be connected in series (the data empty depth expansion configuration. There will be no delay evident for
outputs of one FIFO connected to the data inputs of the next) with no subsequent words written to the configuration.
external logic necessary. The resulting configuration provides a total
The first free location created by reading from a full depth expansion
depth equivalent to the sum of the depths associated with each single configuration will "bubble up" from the last FIFO to the previous one until it
FIFO. Figure 24 shows a depth expansion using two IDT72V255LA/ finally moves into the first FIFO of the chain. Each time a free location is
72V265LA devices.
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling
Care should be taken to select FWFT mode during Master Reset for all the preceding FIFO to write a word to fill it.
FIFOs in the depth expansion configuration. The first word written to an
For a full expansion configuration, the amount of time it takes for IR of the
empty configuration will pass from one FIFO to the next ("ripple down") first FIFO in the chain to go LOW after a word has been read from the last
until it finally appears at the outputs of the last FIFO in the chain–no read FIFO is the sum of the delays for each individual FIFO:
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the
WCLK period. Note that extra cycles should be added for the possibility
that the tSKEW1 specification is not met between RCLK and transfer clock,
or WCLK and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, which-
ever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the
RCLK period. Note that extra cycles should be added for the possibility
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
RCLK
WRITE ENABLE
INPUT READY
OR
WEN
REN
IDT
72V255LA
72V265LA
IDT
72V255LA
72V265LA
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4672 drw 23
Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion
25
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (0°C to +70°C)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Commercial Only
10
15
20
Clock Cycle Time (tCLK
)
Com’l & Ind’l
Speed in Nanoseconds
Commercial Only
LA
Low Power
72V255
72V265
8,192 x 18 3.3V SuperSync FIFO
16,384 x 18 3.3V SuperSync FIFO
4672 drw 24
NOTE:
1. Industrial temperature range product for 15ns speed grade is available as a standard device.
DATASHEETDOCUMENTHISTORY
04/25/2001
pgs. 1, 5, 6 and 26.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
www.idt.com*
PFPkg: www.idt.com/docs/PSC4036.pdf
TFPkg: www.idt.com/docs/PSC4046.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark and the SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
26
3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18
16,384 x 18
IDT72V255LA
IDT72V265LA
ADDENDUM
DIFFERENCES BETWEEN THE IDT72V255LA/72V265LA AND IDT72V255L/72V265L
IDT has improved the performance of the IDT72V255/72V265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part
is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
Item
NEW PART
OLD PART
Comments
IDT72V255LA
IDT72V265LA
IDT72V255L
IDT72V265L
Pin #3
DC (Don’t Care) - There is
no restriction on WCLK and
RCLK. See note 1.
FS (Frequency Select)
In the LA part this pin must be tied
to either VCC or GND and must
not toggle after reset.
(4)
(3)
(4)
First Word Latency
60ns(2) + tREF + 1 TRCLK
tFWL = 10*Tf + 2TRCLK (ns) First word latency in the LA part is
1
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
First Word Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tFWL = 10*Tf + 3TRCLK (ns) First word latency in the LA part is
2
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(IDT Standard Mode)
60ns(2) + tREF + 1 TRCLK
tRTF1 = 14*Tf + 3TRCLK (ns) Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
(4)
(3)
(4)
Retransmit Latency
(FWFT Mode)
60ns(2) + tREF + 2 TRCLK
tRTF2 = 14*Tf + 4TRCLK (ns) Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
ICC1
55mA
100mA
10mA
Active supply current
Standby current
ICC2
20mA
Typical ICC1(5)
10 + 1.1*fS + 0.02*CL*fS(mA)
Not Given
Typical ICC1 Current calculation
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is tSKEW3.
3. Tf is the period of the ‘selected clock’.
4. TRCLK is the cycle period of the read clock.
5. Typical ICC1 is based on VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).
The IDT logo is a registered trademark and the SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
27
2001 Integrated Device Technology, Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
©2020 ICPDF网 联系我们和版权申明