IDT72V36110L15PFGI [IDT]
FIFO, 128KX36, 10ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128;
| 型号： | IDT72V36110L15PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 128KX36, 10ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总48页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT HIGH-DENSITY SUPERSYNC II™
36-BIT FIFO
65,536 x 36
131,072 x 36
IDT72V36100
IDT72V36110
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic
Ball Grid Array (PBGA) (with additional features)
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690)family
FEATURES:
• Choose among the following memory organizations:
IDT72V36100 ⎯ 65,536 x 36
IDT72V36110 ⎯ 131,072 x 36
• Higher density, 2Meg and 4Meg SuperSync II FIFOs
• Up to 166 MHz Operation of the Clocks
• UserselectableAsynchronous readand/orwriteports (PBGAOnly)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• Partial Reset clears data, but retains programmable settings
FUNCTIONALBLOCKDIAGRAM
*Available on the PBGA package only.
D0 -Dn (x36, x18 or x9)
LD SEN
WEN
WCLK/WR
*
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
FLAG
LOGIC
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
*
RAM ARRAY
65,536 x 36
131,072 x 36
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
RT
RM
ASYR
READ
CONTROL
LOGIC
BM
IW
OW
OUTPUT REGISTER
BUS
*
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK/RD
*
REN
TCK
*
*
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
6117 drw01
*
Q0 -Qn (x36, x18 or x9)
OE
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2008
1
©
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6117/14
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Bus-MatchingSyncFIFOsareparticularlyappropriatefornetwork,video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
bufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera36-bit, 18-bitora9-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
DESCRIPTION:
TheIDT72V36100/72V36110areexceptionallydeep,highspeed,CMOS
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrolsanda
flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key
userbenefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Asynchronous/Synchronous translationonthereadorwriteports
• Highdensityofferingsupto4Mbit
PIN CONFIGURATIONS
INDEX
WEN
SEN
DNC(1)
OE
1
2
3
4
102
VCC
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
VCC
DNC(1)
IW
D35
D34
D33
D32
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
VCC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
VCC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
VCC
VCC
Q15
Q14
Q13
Q12
VCC
GND
Q11
Q10
D12
GND
D11
6117 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128-1, order code: PF)
TOP VIEW
2
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,andtheOE inputused
toprovidethree-statecontroloftheoutputs,Qn.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
DESCRIPTION(CONTINUED)
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
PINCONFIGURATIONS(CONTINUED)
A1 BALL PAD CORNER
A
ASYW
SEN
WEN
PAF
LD
HF
BM
EF
ASYR
BE
REN
OE
RT
WCLK
FF/IR
RCLK
IP
Q35
Q34
B
C
D
E
PRS
MRS
IW
FS0
FS1
PFM
PAE
D35
D32
D29
D34
D31
D28
D33
D30
D27
FWFT/SI
OW
VCC
VCC
RM
Q29
Q26
Q32
Q30
Q27
Q3
3
VCC
VCC
GND
GND
GND
GND
VCC
VCC
Q31
Q28
VCC
GND
GND
VCC
F
Q23
Q22
Q19
Q16
Q13
D26
D21
D18
D15
D12
D25
D22
D19
D16
D13
D11
D24
D23
D20
D17
D14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Q24
Q21
Q18
Q15
Q12
Q25
Q20
Q17
Q14
Q11
V
CC
VCC
G
VCC
VCC
H
J
VCC
VCC
V
CC
VCC
VCC
VCC
K
L
D3
D0
VCC
VCC
TDO
Q2
D1
TCK
D10
D9
1
D6
D7
3
D4
TMS
TRST
6
Q0
Q1
8
Q3
Q4
9
Q5
Q6
10
Q10
Q7
Q9
Q8
M
D5
D8
D2
TDI
2
4
5
7
11
12
6117 drw02b
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
3
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DESCRIPTION (CONTINUED)
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
(x36, x18 or x9) DATA OUT (Q
RETRANSMIT (RT)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
72V36100
72V36110
(x36, x18 or x9) DATA IN (D
0
- Dn)
0 - Qn)
SERIAL ENABLE(SEN)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
PROGRAMMABLE ALMOST-FULL (PAF)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
6117 drw03
INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW- thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW- bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
transitionofRCLK.
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is Figure 4 for Bus-Matching Byte Arrangement.
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag to select the parity bit in the word loaded into the parallel port (D0-Dn) when
Mode (PFM) pin. programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
operationbysettingthereadpointertothefirstlocationofthememoryarray. Paritymode is selected, thenD8, D17andD26are assumedtobe validbits
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit andD32,D33,D34andD35areignored. IPmodeisselectedduring Master
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an
latency retransmit. A HIGH on RM during Master Reset will select normal effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
latency.
If zero latency retransmit operation is selected, the first data word to be
writtentoandreadfromthe FIFO.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
RefertoFigure11and12forRetransmitTimingwithnormallatency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
BoundaryScanArchitecture.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
shown in Table 1.
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V36100/72V36110 are fabricated using IDT’s high speed
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread submicronCMOStechnology.
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
NOTE:
1. Pin status during Master Reset.
5
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION (TQFP AND PBGA PACKAGES)
Symbol
Name
I/O
Description
(1)
BM
Bus-Matching
I
I
BMworkswithIWandOWtoselectthebussizesforbothwriteandreadports. SeeTable1forbussizeconfiguration.
(1)
BE
Big-Endian/
Little-Endian
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
selectLittle-Endianformat.
D0–D35
DataInputs
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
EF/OR
EmptyFlag/
OutputReady
O
IntheIDTStandardmode, theEF functionis selected. EF indicates whetherornotthe FIFOmemoryis empty.
InFWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
FF/IR
Full Flag/
Input Ready
O
Inthe IDTStandardmode, theFF functionis selected. FF indicates whetherornotthe FIFOmemoryis full. Inthe
FWFTmode,theIRfunctionisselected.IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFO
memory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. Thereareuptoeightpossiblesettings available.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
HF
IP(1)
Half-FullFlag
O
I
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.A HIGHwillselectInterspersedParity
mode.InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnot
effectthedatawrittentoandreadfromtheFIFO.
InterspersedParity
(1)
IW
InputWidth
Load
I
I
This pin, alongwithOWandMB, selects the bus widthofthe write port. See Table 1forbus size configuration.
LD
Thisisadualpurposepin.DuringMasterReset,thestateoftheLD inputalongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
OE
OW
OutputEnable
OutputWidth
MasterReset
I
I
I
OEcontrolstheoutputimpedanceofQn.
This pin, alongwithIWandBM, selects the bus widthofthe readport. See Table 1forbus size configuration.
(1)
MRS
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringMasterReset,
theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
PAE
PAF
Programmable
O
O
I
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAFgoes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister. PAF goes LOWifthenumberoffreelocations intheFIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
Almost-EmptyFlag
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettingsareall
retained.
Q0–Q35
DataOutputs
O
I
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state.Outputsarenot5VtolerantregardlessofthestateofOE.
If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intothe offsetregisters is outputona risingedge ofRCLK. IfAsynchronous operationofthe readporthas been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operationofthe RCLK/RDinputis onlyavailable inthe PBGApackage.
RCLK/
RD
ReadClock/
ReadStrobe
REN
RM
ReadEnable
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
(1)
RetransmitTiming
Mode
RT
Retransmit
I
RTassertedontherisingedgeofRCLKinitializes theREADpointertozero,sets theEFflagtoLOW(ORtoHIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
NOTE:
1. Inputs should not change state after Master Reset.
6
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION-CONTINUED(TQFP&PBGAPACKAGES)
Symbol
Name
I/O
Description
SEN
WCLK/
WR
SerialEnable
I
I
SENenablesserialloadingofprogrammableflagoffsets.
WriteClock/
WriteStrobe
If Synchronous operation of the write port has been selected, when enabled by WEN, the risingedge ofWCLK
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdataintotheFIFO
ona risingedge inanAsynchronous manner, (WEN shouldbe tiedtoits active state). Asynchronous operationof
theWCLK/WRinputisonlyavailableinthePBGApackage.
WEN
VCC
WriteEnable
+3.3VSupply
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
These are VCC supply inputs and must be connected to the 3.3V supply rail.
NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (PBGA PACKAGE ONLY)
Symbol
Name
I/O
Description
ASYR(1)
Asynchronous
ReadPort
I
AHIGHonthis inputduringMasterResetwillselectSynchronous readoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ASYW(1)
Asynchronous
WritePort
I
I
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
(2)
TCK
JTAGClock
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
onthefallingedgeofTCK.IftheJTAGfunctionis notusedthis signalneeds tobetiedtoGND.
(2)
TDI
JTAGTestData
Input
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register.This outputis highimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(2)
JTAGMode
JTAGReset
I
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerwillautomaticallyresetupon
power-up.IftheJTAGfunctionis notusedthenthis signalshouldtobetiedtoGND.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 43-47 and Figures 31-33.
7
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
(2)
VTERM
TerminalVoltage
–0.5to+4.5
V
Symbol
Parameter
Min.
Typ.
Max. Unit
with respect to GND
(1)
VCC
SupplyVoltageCom’l/Ind’l
SupplyVoltageCom’l/Ind’l
InputHighVoltageCom’l/Ind’l
InputLowVoltageCom’l/Ind’l
3.15
0
3.3
0
3.45
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND
(2)
VIH
2.0
—
0
—
—
—
5.5
0.8
70
V
DCOutputCurrent
mA
(3)
VIL
V
NOTES:
TA
TA
OperatingTemperature
Commercial
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Industrial
-40
—
85
°C
NOTES:
2. VCC terminal only.
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V36100L
IDT72V36110L
Commercial and Industrial(1)
tCLK = 6, 7-5, 10, 15 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
—
—
1
µ A
µA
V
(3)
ILO
10
—
0.4
40
15
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
V
ICC1(4,5,6)
ICC2(4,7)
mA
mA
NOTES:
1. Industrial temperature range product for the 7-5ns and 15ns speed grade are available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 4.2 + 1.4*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
8
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
(2)
(2)
Commercial
Com’l & Ind’l
Commercial
TQFP Only
Com’l & Ind’l
TQFP Only
PBGA & TQFP
PBGA & TQFP
IDT72V36100L6 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L15
IDT72V36110L6 IDT72V36110L7-5 IDT72V36110L10 IDT72V36110L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
DataAccessTime(5)
Clock Cycle Time
Clock High Time
Clock Low Time
—
166
—
133.3
—
1(5)
100
—
66.7
MHz
tA
1
6
4
1(5)
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
1(5)
15
6
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
4
10
2.7
2.7
2
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
6
DataSetupTime
4
tDH
DataHoldTime
0.5
2
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
0.5
3
1
4
tLDH
tRS
LoadHoldTime
0.5
10
15
10
—
3
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
15
15
15
—
4
tRSS
tRSR
tRSF
tRTS
tOLZ
tOE
15
15
10
10
ResettoFlagandOutputTime
RetransmitSetupTime
—
3.5
0
—
3.5
0
—
—
6
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid(5)
0
0
1
1(5)
1(5)
—
—
—
—
—
—
—
5
1(5)
1(5)
—
—
—
—
—
—
—
7
1(5)
1(5)
—
—
—
—
—
—
—
9
(4,5)
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
OutputEnabletoOutputinHighZ
1
4
6
6
8
Write Clock to FF or IR
Read Clock to EF or OR
—
—
—
—
—
—
—
4
4
5
6.5
6.5
16
10
10
20
10
20
10
20
—
—
4
5
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
10
4
12.5
5
6.5
16
10
4
12.5
5
6.5
16
10
—
—
12.5
—
—
tSKEW1
tSKEW2
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
—
—
5
7
10
14
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 7-5ns and 15ns are available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
9
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)—ASYNCHRONOUSTIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com’l & Ind’l
IDT72V36100L6
IDT72V36110L6
IDT72V36100L7-5
IDT72V36110L7-5
Symbol
Parameter
Cycle Frequency (Asynchronous mode)
DataAccessTime
Min.
—
0.6
10
Max.
100
8
Min.
—
0.6
12
Max.
83
Unit
MHz
ns
(4)
fA
(4)
tAA
10
(4)
tCYC
Cycle Time
—
—
—
—
8
—
—
—
—
10
ns
(4)
tCYH
Cycle HIGH Time
4.5
4.5
8
5
ns
(4)
tCYL
Cycle LOW Time
5
ns
(4)
tRPE
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
10
—
—
—
—
ns
(4)
tFFA
—
—
—
—
ns
(4)
tEFA
8
10
ns
(4)
tPAFA
8
10
ns
(4)
tPAEA
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
8
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Parameters apply to the PBGA package only.
10
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
AC TEST LOADS - 6ns, 7.5ns Speed Grade
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
3ns(1)
InputRise/FallTimes
1.5V
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoadfortCLK =10ns,15ns
OutputLoadfortCLK =6ns,7.5ns
1.5V
1.5V
50
Ω
SeeFigure2a
See Figure 2b & 2c
Z0 = 50Ω
I/O
NOTE:
6117 drw04a
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
Figure 2b. AC Test Load
ACTESTLOADS-10ns,15nsSpeedGrades
6
5
4
3
2
1
3.3V
330Ω
D.U.T.
30pF*
510Ω
6117 drw04
20 30 50 80 100
Capacitance (pF)
200
6117 drw04b
Figure 2a. Output Load
* Includes jig and scope capacitances.
Figure 2c. Lumped Capacitive Load, Typical Derating
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
6117 drw04c
11
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tothe FIFO. D =65,536writes forthe IDT72V36100and131,072writes for
theIDT72V36110,respectively.
FUNCTIONALDESCRIPTION
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V36100/72V36110 support two different timing modes of
operation:IDTStandardmodeorFirstWordFallThrough(FWFT)mode. The
selectionofwhichmodewilloperateisdeterminedduringMasterReset,bythe
stateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe32,770th
wordfortheIDT72V36100and65,538thwordfortheIDT72V36110,respec-
tivelywaswrittenintotheFIFO. ContinuingtowritedataintotheFIFOwillcause
the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after(65,537-m)writes fortheIDT72V36100and(131,073-m)writes forthe
IDT72V36110, where m is the full offset value. The default setting for these
values arestatedinthefootnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
D writes to the FIFO. D = 65,537 writes for the IDT72V36100 and 131,073
writesfortheIDT72V36110,respectively.NotethattheadditionalwordinFWFT
modeisduetothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the32,769thwordfortheIDT72V36100and65,537thwordfortheIDT72V36110,
respectivelywaswrittenintotheFIFO. ContinuingtowritedataintotheFIFO
willcausetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifno
reads are performed, the PAF will go LOW after (65,536-m) writes for the
IDT72V36100and(131,072-m)writes fortheIDT72V36110. Theoffset“m”
isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 2. This parameter is also user programmable. See section on
ProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10,12,
and 14.
12
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
theLD(Load)pin.DuringMasterReset,thestateoftheLDinputdetermines
whetherserialorparallelflagoffsetprogrammingis enabled. AHIGHonLD
duringMasterResetselectsserialloadingofoffsetvalues. ALOWonLDduring
MasterResetselectsparallelloadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
selected. Validprogrammingranges are from0toD-1.
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72V36100, 72V36110
LD
L
L
FSEL1
FSEL0
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
H
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
255
127
LD
H
L
FSEL1
FSEL0
Program Mode
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
TheIDT72V36100/72V36110canbeconfiguredduringtheMasterReset
cycle witheither synchronousorasynchronoustimingforPAFandPAEflags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK. Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure17forsynchronous
PAFtimingandFigure18forsynchronous PAE timing.
(3)
X
X
X
X
Serial
(4)
Parallel
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
19forasynchronousPAFtimingandFigure20forasynchronousPAEtiming.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V36100/
72V36110haveinternalregistersfortheseoffsets.Thereareeightdefaultoffset
valuesselectableduringMasterReset. TheseoffsetvaluesareshowninTable
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial
orparallelloadingmethod.Theselectionoftheloadingmethodisdoneusing
13
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
FF PAF
PAE EF
HF
IDT72V36100
0
IDT72V36110
0
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
1 to n(1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
H
H
H
H
H
(n+1) to 32,768
32,769 to (65,536-(m+1))
(n+1) to 65,536
65,537 to (131,072-(m+1))
H
L
L
to 65,535
to 131,071
(65,536-m)
(131,072-m)
L
L
65,536
131,072
NOTE:
1. See table 2 for values for n, m.
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
IR PAF
PAE OR
HF
IDT72V36100
IDT72V36110
H
H
H
L
L
H
0
0
L
L
L
L
H
H
H
H
L
Number of
Words in
FIFO
1 to n+1
1 to n+1
L
L
H
H
H
H
L
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
L
L
L
L
L
H
L
L
6117 drw05
NOTE:
1. See table 2 for values for n, m.
14
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V36100
IDT72V36110
WCLK RCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
1
0
1
Full Offset (MSB)
Serial shift into registers:
0
1
1
0
1
X
32 bits for the 72V36100
34 bits for the 72V36110
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
No Operation
Write Memory
1
1
1
0
X
1
X
0
1
X
X
X
X
X
Read Memory
No Operation
X
6117 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
15
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1st Parallel Offset Write/Read Cycle
# of Bits Used:
D/Q35
D/Q19
D/Q0
D/Q17
D/Q8
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
1
1
15 14
9
17 16
16 15
13 12 11 10
13 12 11 10 9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
Interspersed
Parity
17
14
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
15 14
14
9
1
1
17 16
15
13 12 11 10
8
8
7
7
6
6
5
5
4
4
3 2
Interspersed
Parity
17
13 12 11 10 9
16
3 2
# of Bits Used
IDT72V36100/IDT72V36110 ⎯ x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
EMPTY OFFSET (LSB) REGISTER (PAE)
D/Q0
1st Parallel Offset Write/Read Cycle
D/Q17
Non-Interspersed
Parity
Data Inputs/Outputs
4
4
3
3
2
2
1
1
16 15 14 13 12 11 10
15 14 11
9
8
8
7
7
6
6
5
5
D/Q0
D/Q16
Interspersed
Parity
9
10
16
13 12
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
D/Q8
# of Bits Used
16 15 14 13 12 11 10
13 12 10
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2nd Parallel Offset Write/Read Cycle
16
Interspersed
Parity
15 14
11
9
8
D/Q17
D/Q8
D/Q16
# of Bits Used
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (MSB) REGISTER (PAE)
17
17
2nd Parallel Offset Write/Read Cycle
D/Q17
3rd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q17
D/Q16
D/Q0
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14
12 11
13
10
9
9
8
7
7
6
6
5
5
4
4
3
2
2
1
16 15 14
12 11
13
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
1
1
16 15
14 13 12 11 10
1
8
3
16 15
14 13 12 11 10
2
D/Q8
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (MSB) REGISTER (PAF)
17
17
IDT72V36100 ⎯ x18 Bus Width
IDT72V36110 ⎯ x18 Bus Width
6117 drw07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
16
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1st Parallel Offset Write/Read Cycle
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
1
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
7
6
5
4
3
2
10
2
7
6
5
4
3
2
8
8
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
2nd Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
3rd Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
15
13
D/Q0
17
EMPTY OFFSET REGISTER (PAE)
3rd Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
1
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
5
8
7
6
4
3
5
2
8
7
6
4
3
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
FULL OFFSET REGISTER (PAF)
4th Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
9
FULL OFFSET REGISTER (PAF)
6th Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
17
FULL OFFSET REGISTER (PAF)
IDT72V36100 ⎯ x9 Bus Width
IDT72V36110 ⎯ x9 Bus Width
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
6117 drw07a
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
17
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
SERIAL PROGRAMMING MODE
does nothavetooccuratonetime. One,twoormoreoffsetregisters canbe
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then writtenandthenbybringingLD HIGH, write operations canbe redirectedto
programmingofPAEandPAFvaluescanbeachievedbyusingacombination theFIFOmemory.WhenLDissetLOWagain,andWENisLOW,thenextoffset
oftheLD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds registerinsequenceiswrittento.AsanalternativetoholdingWENLOWand
as follows: whenLDandSEN aresetLOW,dataontheSIinputarewritten, togglingLD,parallelprogrammingcanalsobeinterruptedbysetting LDLOW
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending andtogglingWEN.
withtheFullOffsetMSB. Atotalof32bitsfortheIDT72V36100and34bitsfor
the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag during the programming process. From the time parallel programming has
Registers,forthetimingdiagramforthismode. begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
Using the serial method, individual registers cannot be programmed wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
selectively. PAEandPAFcanshowavalidstatusonlyafterthecompleteset therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
of bits (for all offset registers) has been entered. The registers can be twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When RCLK edges plus tPAE plus tSKEW2.
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
The act of reading the offset registers employs a dedicated read offset
Write operations to the FIFO are allowed before and during the serial registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoes pinswhenLDissetLOWandRENissetLOW.Forx36outputbuswidth,data
nothavetooccuratonce. AselectnumberofbitscanbewrittentotheSIinput are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
andthen,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemory transitionofRCLK.UponthesecondLOW-to-HIGHtransitionofRCLK,dataare
via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN readfromthe FullOffsetRegister. The thirdtransitionofRCLKreads, once
restoredtoaLOW,thenextoffsetbitinsequenceiswrittentotheregistersvia again,fromtheEmptyOffsetRegister.Forx18outputbuswidth,atotaloffour
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset readcyclesarerequiredtoobtainthevaluesoftheoffsetregisters.Startingwith
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. OnceLD theEmptyOffsetRegisterLSBandfinishingwiththeFullOffsetRegisterMSB.
andSENarebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues. Forx9outputbuswidth,atotalofsixreadcyclesmustbeperformedontheoffset
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag registers.SeeFigure3,ProgrammableFlagOffsetProgrammingSequence.
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen SeeFigure17, ParallelReadofProgrammableFlagRegisters,forthetiming
written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria; diagramforthismode.
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. orbothtogether.WhenREN andLDarerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
programmingofPAEandPAFvaluescanbeachievedbyusingacombination Parallelreadingofthe offsetregisters is always permittedregardless of
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
proceedsasfollows: LDandWENmustbesetLOW.Forx36bitinputbuswidth,
dataontheinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW- RETRANSMITOPERATION
to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
The Retransmit operation allows data that has already been read to be
WCLK,dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLK accessedagain. Thereare2modesofRetransmitoperation,normallatency
writes,onceagain,totheEmptyOffsetRegister. Forx18bitinputbuswidth, andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
dataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSBonthefirst that resets the read pointer to the first location of memory, then the actual
LOW-to-HIGHtransitionofWCLK.Uponthe2ndLOW-to-HIGHtransitionof retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
WCLKdataarewrittenintotheEmptyOffsetRegisterMSB.Thethirdtransition beginningofmemory.
ofWCLKwritestotheFullOffsetRegisterLSB,thefourthtransitionofWCLKthen
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
writestotheFullOffsetRegisterMSB.ThefifthtransitionofWCLKwritesonce RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
againtotheEmptyOffsetRegisterLSB. Atotaloffourwritestotheoffsetregisters utilized,RENdoesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwowords,
isrequiredtoloadvaluesusingax18inputbuswidth.Foraninputbuswidth butnomorethanD-2wordsshouldhavebeenwrittenintotheFIFO,andread
ofx9bits,atotalofsixwritecyclestotheoffsetregistersisrequiredtoloadvalues. fromtheFIFO,betweenReset(MasterorPartial)andthetimeofRetransmit
See Figure 3, Programmable Flag Offset Programming Sequence. See setup. D =65,537fortheIDT72V36100and131,073fortheIDT72V36110.
Figure 16, Parallel Loading of Programmable Flag Registers, for the timing
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
diagramforthismode.
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
pointer. The act of reading offsets employs a dedicated read offset register initializedtothefirstlocationoftheRAMarray.
pointer.Thetwopointersoperateindependently;however,areadandawrite
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
noeffectonthepositionofthesepointers.
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Write operations to the FIFO are allowed before and during the parallel Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
18
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
setupbysettingORHIGH.Duringthis period,theinternalreadpointeris set thePAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
tothefirstlocationoftheRAMarray.
thatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the risingedgeofWCLKthatoccurstSKEWaftertherisingedgeofRCLKthatRT
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected, is setup will update PAF. RT is synchronized to RCLK.
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
TheRetransmitfunctionhastheoptionoftwomodesofoperation,either
all subsequent words requires a LOW on REN to enable the rising edge of “normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
diagram.
latency”retransmitoperation.Zerolatencybasicallymeansthatthefirstdata
For either IDT Standard mode or FWFT mode, updating of the PAE, HF wordtoberetransmitted,isplacedontotheoutputregisterwithrespecttothe
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is RCLKpulsethatinitiatedtheretransmit.
19
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ASYNCHRONOUS READ (ASYR)
SIGNALDESCRIPTION
INPUTS:
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
Asynchronousoperationofthereadportwillbeselected.DuringAsynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronous readstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
DATA IN (D0 - Dn)
Datainputsfor36-bitwidedata(D0-D35),datainputsfor18-bitwidedata
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS:
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures25,26,27and28forrelevanttimingand
operationalwaveforms.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessedagain. Thereare2modesofRetransmitoperation,normallatency
andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
utilized,RENdoesnotneedtobeHIGHbeforebringingRT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH.Duringthis period,theinternalreadpointeris set
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 5, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET ( PRS )
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW. IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 6, PartialResetTiming, forthe relevanttimingdiagram.
ASYNCHRONOUS WRITE (ASYW)
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchronous
operation of the write port the WCLK input becomes WR input, this is the
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
basedinbothawriteoperationandreadoperation.Note,ifAsynchronousmode
is selected, FWFTis notpermissable. RefertoFigures 23, 24, 27and28for
relevanttimingandoperationalwaveforms.
In Retransmit operation, zero latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset. Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor
First Word Fall Through (FWFT) mode.
20
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode the HF flag to HIGH). The Write and Read Clocks can be independent or
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror coincident.
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag
If Asynchronous operation has been selected this input is RD (Read
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace Strobe) . Data is Asynchronously read from the FIFO via the output register
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including whenever there is a rising edge on RD. In this mode the REN input must be
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
tiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthethree-
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe stateQnoutputs.
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate READ ENABLE ( REN )
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK register on the rising edge of every RCLK cycle if the device is not empty.
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF maintainthepreviousdatavalue.
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset. wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
StandardandFWFTmodes.
furtherreadoperations. RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this
inputbehavesasWCLK.
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe allotherwords,areadmustbeexecutedusingREN. TheRCLKLOW-to-HIGH
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
updating HF flag to LOW). The Write and Read Clocks can either be operations. REN is ignored when the FIFO is empty.
independentorcoincident.
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). mustbeheldactive,(tiedLOW).
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK.
When SEN is HIGH, the programmable registers retains the previous
settings andnooffsets areloaded. SENfunctions thesamewayinbothIDT
StandardandFWFTmodes.
WRITE ENABLE ( WEN )
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
OUTPUT ENABLE ( OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
LOAD ( LD )
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD
enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
orparallelloadorreadofthese offsetvalues.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
mustbeheldactive,(tiedLOW).
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
21
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
BUS-MATCHING (BM, IW, OW)
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths. areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus totheFIFO(D = 65,537fortheIDT72V36100and131,073fortheIDT72V36110).
sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte SeeFigure9,WriteTiming(FWFTMode),fortherelevanttiminginformation.
sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure4forBus-
MatchingByteArrangement.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
During Master Reset, a LOW on BE will select Big-Endian operation. A
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction doubleregister-bufferedoutputs.
isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x36to
x18,x36tox9,x18tox36andx9tox36.IfBig-Endianmodeisselected,then EMPTY FLAG ( EF/OR )
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis Cycle,EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
configured during master reset by the state of the Big-Endian (BE) pin. See therelevanttiminginformation.
Figure 4 for Bus-Matching Byte Arrangement.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram- thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
flagtimingmode.IfasynchronousPAF/PAEconfigurationisselected(PFM, indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
LOWduringMRS),thePAEisassertedLOWontheLOW-to-HIGHtransition LOWagain.SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. information.
Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT
If synchronous PAE/PAF configuration is selected (PFM, HIGH during mode,ORisatripleregister-bufferedoutput.
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe
stateoftheProgrammableFlagMode(PFM)pin.
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(65,536-m)writesfortheIDT72V36100
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode. and(131,072-m)writes fortheIDT72V36110.Theoffset“m”is thefulloffset
A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
In FWFT mode, the PAF will go LOW after (65,537-m) writes for the
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe IDT72V36100and(131,073-m)writes fortheIDT72V36110,wheremis the
FIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26and fulloffsetvalue.Thedefaultsettingforthisvalueisstatedin Table2.
D35 duringthe parallelprogrammingofthe flagoffsets. IfNon-Interspersed
Paritymodeisselected,thenD8,D17andD28 areisassumedtobevalidbits StandardandFWFTMode),fortherelevanttiminginformation.
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
SeeFigure18,SynchronousProgrammableAlmost-FullFlagTiming(IDT
ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
writtentoandreadfromthe FIFO.
configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
Figure20,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
Mode).
OUTPUTS:
FULL FLAG ( FF/IR )
PROGRAMMABLEALMOST-EMPTYFLAG(PAE )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed
after a reset (eitherMRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110). See
Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevanttiminginformation.
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
SeeFigure19, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IRgoes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
22
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536 for the
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE IDT72V36100 and 131,072 for the IDT72V36110.
configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
Standard and FWFT Mode).
HALF-FULL FLAG ( HF )
IDT72V36100 and 131,073 for the IDT72V36110.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO WCLK,itisconsideredasynchronous.
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth DATAOUTPUTS(Q0-Qn)
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
(Q0-Q35)aredataoutputsfor36-bitwidedata,(Q0-Q17)aredataoutputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
23
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to FIFO
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
A
B
C
D
Read from FIFO
X
L
L
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
L
Q17-Q9
Q8-Q0
C
D
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
L
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
B
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
B
Q8-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Q35-Q27
Q35-Q27
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q17-Q9
Q17-Q9
Q8-Q0
BE BM IW
OW
H
D
1st: Read from FIFO
H
H
L
Q8-Q0
2nd: Read from FIFO
3rd: Read from FIFO
C
Q8-Q0
B
Q8-Q0
A
4th: Read from FIFO
6117 drw08
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement
24
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
D35-D27
D35-D27
D26-D18
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
1st: Write to FIFO
2nd: Write to FIFO
A
B
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
B
D
Read from FIFO
Read from FIFO
A
C
L
H
H
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to FIFO
2nd: Write to FIFO
D8-D0
B
D8-D0
3rd: Write to FIFO
4th: Write to FIFO
C
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
C
A
Read from FIFO
6117 drw09
D
B
H
H
H
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement (Continued)
25
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
t
RSR
RSR
tRSS
t
tRSS
WEN
tRSR
tRSS
FWFT/SI
tRSR
tRSS
tRSS
tRSS
LD
ASYW,
ASYR
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
BM,
OW, IW
BE
RM
PFM
tRSS
IP
RT
tRSS
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
t
RSF
FF/IR
PAE
tRSF
tRSF
PAF, HF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
6117 drw10
Figure 5. Master Reset Timing
26
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
6117 drw11
Figure 6. Partial Reset Timing
27
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
t
DH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
FF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
6117 drw12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
t
OLZ
tOHZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENH
tENH
tENS
tENS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
6117 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
28
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
29
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
30
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
tREF
tREF
EF
PAE
HF
t
PAES
tHF
t
PAFS
PAF
6117 drw16
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
31
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
3
1
2
t
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENS
tRTS
REN
- Q
t
A
t
A
tA
A
(4)
(4)
(4)
Q0
n
Wx
Wx+1
W
2
W4
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
tREF
tREF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
6117 drw17
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
32
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1
2
3
RCLK
t
ENS
tENH
REN
t
A
tA
t
A
t
A
t
A
(3)
3
(3)
(3)
W2
Q0 - Qn
W
4
W
Wx
W1
Wx+1
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
EF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
6117 drw18
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
33
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
4
1
2
5
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
t
A
tA
t
A
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W3
W1
W
2
W
4
W5
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
t
PAES
PAE
HF
tHF
t
PAFS
PAF
6117 drw19
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
tENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
6117 drw20
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 15 for the IDT72V36100 and X = 16 for the IDT72V36110.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
34
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
t
LDH
ENH
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0
- Dn
6117 drw 21
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
tCLKH
tCLKL
RCLK
tLDS
tLDH
tENH
tLDH
tENH
LD
tENS
REN
tA
PAE OFFSET
tA
DATA IN OUTPUT REGISTER
PAF OFFSET
Q0 - Qn
6117 drw 22
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
1
2
WCLK
WEN
PAF
2
1
tENS
tENH
t
PAFS
t
PAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
t
SKEW2(3)
RCLK
tENS
tENH
6117 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
35
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
SKEW2(4)
t
t
PAES
PAES
t
1
2
1
2
RCLK
tENS
tENH
6117 drw 24
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
6117 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
36
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
(2)
tPAEA
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
6117 drw26
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
]
words in FIFO(2)
2
tHF
RCLK
tENS
REN
6117 drw27
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
37
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RCLK
tENS
tENH
REN
Qn
tA
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
Dn
WD
WD+1
6117 drw28
NOTE:
1. OE = LOW and WEN = LOW.
Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
REN
tA
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
6117 drw29
NOTE:
1. OE = LOW and WEN = LOW.
Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
38
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
No Write
1
WCLK
WEN
Dn
2
D
F+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
6117 drw30
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
Qn
t
CYH
t
AA
Last Word in Output Register
W0
6117 drw31
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
39
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W
0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
6117 drw32
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
t
DH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
6117 drw33
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
40
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separatelyANDingFFofeveryFIFO. InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 29 demonstrates a width expansion using two IDT72V36100/
72V36110devices. D0-D35fromeachdeviceforma72-bitwideinputbusand
Q0-Q35 fromeachdevice forma 72-bitwide outputbus. Anywordwidthcan
beattainedbyaddingadditionalIDT72V36100/72V36110devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
72V36100
72V36110
IDT
72V36100
72V36110
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FIFO
#1
FIFO
#2
m + n
n
Qm+1 - Qn
DATA OUT
m
6117 drw34
Q0
- Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 29. Block Diagram of 65,536 x 72 and 131,072 x 72 Width Expansion
41
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
READ ENABLE
WRITE ENABLE
INPUT READY
OR
WEN
REN
IDT
72V36100
72V36110
IDT
72V36100
72V36110
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
6117 drw35
Figure 30. Block Diagram of 131,072 x 36 and 262,144 x 36 Depth Expansion
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towriteawordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
TheIDT72V36100caneasilybeadaptedtoapplicationsrequiringdepths
greaterthan65,536and131,072fortheIDT72V36110,withan36-bitbuswidth.
InFWFTmode,theFIFOscanbeconnectedinseries(thedataoutputsofone
FIFOconnectedtothedatainputsofthenext)withnoexternallogicnecessary.
Theresultingconfigurationprovidesatotaldepthequivalenttothesumofthe
depthsassociatedwitheachsingleFIFO. Figure30showsadepthexpansion
usingtwoIDT72V36100/72V36110devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
42
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
t
TCK
JTCKR
JTCKL
t
tJTCKF
t
tJTCKH
TCK
TDI/
TMS
tDH
tDS
TDO
TDO
tDO
tJRSR
6117 drw36
TRST(1)
tJRST
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
Figure 31. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
(VCC = 3.3V 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72V36100
IDT72V36110
JTAGClockHIGH
JTAGClockLow
tJTCKH
tJTCKL
tJTCKR
tJTCKF
tJRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
(1)
-
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tJRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
43
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V36100/72V36110
incorporatesthenecessarytapcontrollerandmodifiedpadcellstoimplement
theJTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6117 drw37
Figure 32. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
44
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
Exit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
6117 drw38
NOTE:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
Figure 33. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
45
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
•
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Hex
Instruction
Function
TESTDATAREGISTER
Value
0x00
0x02
0x01
0x03
0x0F
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SAMPLE/PRELOAD SelectBoundaryScanRegister
HIGH-IMPEDANCE JTAG
BYPASS
SelectBypassRegister
Table 6. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
For the IDT72V36100/72V36110, the Part Number field contains the
followingvalues:
Device
IDT72V36100
IDT72V36110
Part# Field
04DE
04DF
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
IDT72V36100/72V36110 JTAG Device Identification Register
28 27
12 11
1 0(LSB)
1
46
OCTOBER22, 2008
TM
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
47
OCTOBER22, 2008
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
BB
Thin Plastic Quad Flatpack (TQFP, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1)
Commercial Only, PBGA & TQFP
6
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Com‘l & Ind’l, PBGA & TQFP
Commercial, TQFP Only
Com'l & Ind'l, TQFP Only
7-5
10
15
L
Low Power
72V36100
72V36110
65,536 x 36
131,072 x 36
⎯
⎯
3.3V SuperSync II™ FIFO
3.3V SuperSync II™ FIFO
6117 drw39
NOTES:
1. Industrial temperature range product for 7-5ns and 15ns are available as standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact you sales office.
DATASHEETDOCUMENTHISTORY
05/25/2000
07/28/2000
12/14/2000
03/27/2001
04/06/2001
12/14/2001
12/16/2002
02/11/2003
06/26/2003
07/15/2003
07/21/2003
09/29/2003
11/02/2005
04/06/2006
10/22/2008
pgs. 1, 6, 7, 8, 34, and 35.
pgs. 13, 14, and 34.
pgs. 6, 7, and 8.
pg. 7.
pgs. 4, 5, and 18.
pgs. 1-36.
pgs. 1-11, 20, 21, 26, and 38-47.
pgs. 7, and 45.
pgs. 1, 3, 9, 10, and 47.
pgs. 3, 20, and 38-40.
pgs. 7, 43, and 45-47.
pg. 8.
pgs. 1, 8-10, and 48.
pg. 4.
pg. 48.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
48
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