IDT72V3626L10PF8 [IDT]
Bi-Directional FIFO, 256X36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128;型号: | IDT72V3626L10PF8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Bi-Directional FIFO, 256X36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片 |
文件: | 总36页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3 VOLT CMOS TRIPLE BUS
SyncFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3626
IDT72V3636
IDT72V3646
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
FEATURES:
• Memory storage capacity:
IDT72V3626–256 x 36 x 2
IDT72V3636–512 x 36 x 2
IDT72V3646–1,024 x 36 x 2
• Mailbox bypass registers for each FIFO
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of 5V operating
IDT723626/723636/723646
• Industrial temperature range (–40°C to +85°C) is available
• Programmable Almost-Empty and Almost-Full flags; each has
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
18
CSA
Port-A
B0-B17
W/RA
ENA
MBA
Control
RAM ARRAY
36
36
Logic
256 x 36
512 x 36
1,024 x 36
CLKB
RENB
CSB
Port-B
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
PRS1
MBB
Read
Pointer
Write
Pointer
SIZEB
36
Status Flag
Logic
FFA/IRA
EFB/ORB
AFA
AEB
FIFO1
FIFO2
Common
Port
SPM
FS0/SD
Control
Logic
Timing
Mode
BE
Programmable Flag
Offset Registers
FS1/SEN
(B and C)
A0-A35
10
FWFT
FFC/IRC
AFC
Status Flag
Logic
EFA/ORA
AEA
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
36
RAM ARRAY
256 x 36
18
36
36
C0-C17
512 x 36
1,024 x 36
CLKC
WENC
MBC
Port-C
Control
Logic
Mail 2
Register
SIZEC
4665 drw01
MBF2
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
AUGUST 2001
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.
DSC-4665/5
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
FIFOsonboardeachchipbufferdatabetweenabidirectional36-bitbus(Port
A)andtwounidirectional18-bitbuses(PortBtransmitsdata,PortCreceives
data.) FIFOdatacanbereadoutofPortBandwrittenintoPortCusingeither
18-bitor9-bitformatswithachoiceofBig-orLittle-Endianconfigurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface. Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
DESCRIPTION:
TheIDT72V3626/72V3636/72V3646arepinandfunctionallycompatible
versionsoftheIDT723626/723636/723646,designedtorunoffa3.3Vsupply
for exceptionally low-power consumption. These devices are a monolithic,
high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO
memorywhichsupportsclockfrequenciesupto100MHzandhasreadaccess
timesasfastas6.5ns. Twoindependent256/512/1,024x36dual-portSRAM
PIN CONFIGURATION
INDEX
1
2
3
4
5
6
7
8
CLKB
PRS2
W/RA
102
101
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
C17
C16
C15
C14
GND
MBC
C13
C12
C11
C10
C9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C8
VCC
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
C0
GND
B17
B16
SIZEC
VCC
B15
B14
B13
B12
GND
B11
B10
4665 drw 02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or fullornot. TheIRandORfunctionsareselectedintheFirstWordFallThrough
coincident. The enables for each port are arranged to provide a simple mode. IRindicateswhetherornottheFIFOhasavailablememorylocations.
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- ORshowswhethertheFIFOhasdataavailableforreadingornot. Itmarksthe
nouscontrol.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
presenceofvaliddataontheoutputs.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and
registers.Themailboxregisters'widthmatchestheselectedbuswidthofports aprogrammableAlmost-Fullflag(AFAandAFC). AEAandAEB indicatewhen
BandC. Eachmailboxregisterhas aflag(MBF1and MBF2)tosignalwhen aselectednumberofwordsremainintheFIFOmemory. AFAandAFCindicate
newmailhas beenstored.
whenthe FIFOcontains more thana selectednumberofwords.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the
Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation PortClockthatwritesdataintoitsarray. EFA/ORA,EFB/ORB,AEA,andAEB
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- are two-stage synchronized to the Port Clock that reads data from its array.
ming,or oneofthreepossibledefaultflagoffsetsettings,8,16or64. EachFIFO Programmableoffsets forAEA, AEB,AFA,AFCareloaded inparallelusing
has its own, independent Master Reset pin, MRS1 and MRS2.
PortAorinserialviatheSDinput. TheSerialProgrammingModepin(SPM)
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe makesthisselection. Threedefaultoffsetsettingsarealsoprovided. TheAEA
memory. UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., andAEBthresholdcanbesetat8,16or64locationsfromtheemptyboundary
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset andtheAFAandAFCthresholdcanbesetat8,16or64locationsfromthefull
is useful since it permits flushing of the FIFO memory without changing any boundary. Allthese choices are made usingthe FS0andFS1inputs during
configurationsettings. EachFIFOhasitsown,independentPartialResetpin, MasterReset.
PRS1 and PRS2.
Twoormore FIFOs maybe usedinparalleltocreate widerdata paths.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, Suchawidthexpansionrequiresnoadditional,externalcomponents. Further-
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A more, two IDT72V3626/72V3636/72V3646 FIFOs can be combined with
read operation is required to access that word (along with all other words unidirectional FIFOs capable of First Word Fall Through timing (i.e. the
residing in memory). In the First Word Fall Through mode (FWFT), the first SuperSyncFIFOfamily)toforma depthexpansion.
wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- automatically power down. During the power down state, supply current
sitateaformalreadrequest). ThestateoftheBE/FWFTpinduringMasterReset consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
determinesthemodeinuse.
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V3626/72V3636/72V3646arecharacterizedforoperationfrom
EachFIFOhas a combinedEmpty/OutputReadyFlag(EFA/ORAand
EFB/ORB)andacombinedFull/InputReadyFlag(FFA/IRAand FFC/IRC). 0°Cto70°C. Industrial temperature range (-40°C to +85°C)is available by
TheEFandFFfunctionsareselectedintheIDTStandardmode. EFindicates specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS
whetherornottheFIFOmemoryisempty. FFshowswhetherthememoryis technology.
3
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
A0-A35
AEA
Name
PortAData
I/O
Description
I/O 36-bitbidirectionaldataportforsideA.
PortAAlmost-
EmptyFlag
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA. ItisLOWwhenthenumberofwordsinFIFO2
islessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
AEB
PortBAlmost-
EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenthenumberofwordsinFIFO1
islessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
AFA
PortAAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocations
inFIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
AFC
PortCAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKC.ItisLOWwhenthenumberofemptylocations
inFIFO2is less thanorequaltothe value inthe Almost-FullCOffsetregister, Y2.
B0-B17
PortBData
O
I
18-bitoutputdataportforsideB.
BE/FWFT Big-Endian/
FirstWordFall
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
In this case, depending on the bus size, themost significant byte or word on Port A is read from
PortBfirst(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow). ALOWonBEwillselect
Little-Endianoperation.Inthis case,theleastsignificantbyteorwordonPortAis readfromPortBfirst
(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow).
ThroughSelect
AfterMasterReset,thispinselectsthetimingmode.AHIGHonFWFTselectsIDTStandardmode,a
LOWselectsFirstWordFallThroughmode.Oncethetimingmodehasbeenselected,thelevelon
FWFTmustbestaticthroughoutdeviceoperation.
C0-C17
CLKA
PortC Data
PortAClock
I
I
18-bitinputdataportforsideC.
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to
theLOW-to-HIGHtransitionofCLKA.
CLKB
CLKC
CSA
PortBClock
PortCClock
I
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbeasynchronous
orcoincidenttoCLKA. EFB/ORBandAEBaresynchronizedtotheLOW-to-HIGHtransitionofCLKB.
CLKCis acontinuous clockthatsynchronizes alldatatransfers throughPortCandcanbeasynchronous
or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGHtransitionof CLKC.
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35
outputsareinthehigh-impedancestatewhenCSAisHIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB. The B0-B17
outputsareinthehigh-impedancestatewhenCSBisHIGH.
EFA/ORA PortAEmpty/
OutputReady
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFA functionis selected. EFA indicates
whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORA
indicates the presence ofvaliddata onthe A0-A35outputs, available forreading. EFA/ORAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
Flag
EFB/ORB PortBEmpty/
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFB functionis selected. EFB indicates
whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB
indicatesthepresenceofvaliddataontheB0-B17outputs,availableforreading. EFB/ORBissynchronized
totheLOW-to-HIGHtransitionofCLKB.
OutputReadyFlag
ENA
PortAEnable
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
FFA/IRA
PortAFull/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whetherornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRA
indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FFC/IRC
Port C Full/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFCfunctionis selected. FFC indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC
indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRCis
synchronizedtotheLOW-to-HIGHtransitionofCLKC.
4
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (Continued)
Symbol
Name
I/O
Description
FS1/SEN FlagOffsetSelect1/
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.DuringMasterReset,
FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod. ThreeOffsetregister
programmingmethods are available:automaticallyloadone ofthree presetvalues (8, 16, or64), parallel
loadfromPortA, andserialload.
SerialEnable,
FS0/SD FlagOffsetSelect0/
SerialData
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SEN isusedasanenablesynchronousto
the LOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW, a risingedge onCLKAloadthe bitpresenton
FS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe Offsetregisters is 32forthe
72V3626, 36 for the 72V3636, and 40 for the 72V3646. The first bit write stores the Y-register (Y1) MSB and the
lastbitwritestorestheX-register(X2)LSB.
MBA
MBB
Port A Mailbox
Select
I
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputsareactive,aHIGHlevelonMBAselectsdatafromthemail2registerforoutputandaLOWlevelselects
FIFO2output-registerdataforoutput.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active,aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselectsFIFO1output
registerdataforoutput.
MBC
Port C Mailbox
Select
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
MasterReset.
MBF1
Mail1Register
Flag
O MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.Writestothemail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
MRS1
Mail2Register
Flag
O MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKCthatwritesdatatothemail2register.Writestothemail2
registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-HIGHtransitionofCLKAwhena
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MasterReset
I
ALOWonthis pin initializes theFIFO1readandwritepointers tothefirstlocationofmemoryandsets thePortB
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialor
parallel)andone ofthree programmable flagdefaultoffsets forFIFO1andFIFO2. Italsoconfigures ports Band
Cforbus size andendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-HIGH
transitionsofCLKBmustoccurwhileMRS1isLOW.
MRS2
MasterReset
I ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywithMRS1,selects
theprogrammingmethod(serialorparallel)andoneof thethreeflagdefaultoffsetsforFIFO2.FourLOW-to-HIGH
transitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKCmustoccurwhileMRS2isLOW.
PRS1
PRS2
PartialReset
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,
programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
PartialReset
I ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,
programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
RENB
SIZEB
Port B Read Enable
I
RENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB.
PortB
BusSizeSelect
I
I
I
SIZEBdetermines the bus widthofPortB. AHIGHonthis pinselects byte (9-bit)bus size. ALOWonthis pin
selects word(18-bit)bus size. SIZEBworks withSIZECandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZEBmustbe staticthroughoutdevice operation.
SIZEC
Port C
BusSizeSelect
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word(18-bit)bus size. SIZECworks withSIZEBandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZECmustbe staticthroughoutdevice operation.
SPM
SerialProgramming
Mode
ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallel
programmingordefaultoffsets (8,16,or64).
WENC
PortCWriteEnable
I
I
WENCmustbeHIGHtoenableaLOW-to-HIGHtransitionofCLKCtowritedataonPortC.
W/RA
PortAWrite/
ReadSelect
AHIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGHtransitionof
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
5
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
SupplyVoltage
Min.
3.0
2
Typ.
3.3
—
Max.
3.6
Unit
V
(1)
VCC
VIH
VIL
IOH
IOL
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
VCC+0.5
0.8
V
—
—
—
0
—
V
—
–4
mA
mA
°C
—
8
TA
—
70
NOTE:
1. For 10ns (100 MHz operation), VCC = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3626
IDT72V3636
IDT72V3646
Commercial
tCLK = 10(1), 15ns
Symbol
VOH
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
2.4
—
Typ.(2)
—
—
—
—
—
—
4
Max.
—
Unit
V
VCC = 3.0V,
IOH = –4 mA
IOL = 8 mA
VOL
OutputLogic"0"Voltage
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
0.5
±10
±10
5
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
VI = VCC - 0.2V or 0
VI = VCC - 0.2V or 0
f = 1 MHz
—
µ A
µ A
mA
mA
pF
ILO
—
ICC2(3)
ICC3(3)
Standby Current (with CLKA, CLKB and CLKC running) VCC = 3.6V,
—
StandbyCurrent(noclocksrunning)
InputCapacitance
VCC = 3.6V,
VI = 0,
—
1
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
—
8
—
pF
NOTES:
1. For 10ns speed grade only: VCC = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
5. Industrial temperature range is available by special order.
6
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3626/72V3636/72V3646withCLKA,
CLKBandCLKCsettofS. Alldata inputs anddata outputs change state duringeachclockcycle toconsume the highestsupplycurrent. Data outputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice'sinputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N
CL
fo
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
outputcapacitanceload
switchingfrequencyofanoutput
200
175
150
fdata = 1/2 fS
TA = 25οC
CL = 0 pF
VCC = 3.6V
VCC = 3.3V
125
100
VCC = 3.0V
75
50
25
0
80
100
0
10
20
30
40
50
60
70
90
4665 drw 03
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3626L10(1) IDT72V3626L15
IDT72V3636L10(1) IDT72V3636L15
IDT72V3646L10(1) IDT72V3646L15
Symbol
fS
Parameter
Min.
—
10
4.5
4.5
3
Max.
100
—
Min.
—
15
6
Max.
66.7
—
Unit
MHz
ns
Clock Frequency, CLKA, CLKB, or CLKC
Clock Cycle Time, CLKA, CLKB, or CLKC
Pulse Duration, CLKA, CLKB, or CLKC HIGH
Pulse Duration, CLKA, CLKB, ORCLKCLOW
Setup Time, A0-A35 before CLKA↑ andC0-C17before CLKC↑
SetupTime,CSAbeforeCLKA↑
tCLK
tCLKH
tCLKL
tDS
—
—
ns
—
6
—
ns
—
4
—
ns
tENS1
tENS2
4
—
4.5
4.5
—
ns
SetupTime,W/RA,ENA,andMBAbeforeCLKA↑;RENBandMBBbeforeCLKB ;
WENC and MBC before CLKC↑
3
—
—
ns
(2)
tRSTS
tFSS
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑or CLKB↑
5
7.5
7.5
7.5
3
—
—
—
—
—
—
—
—
—
5
8.5
7.5
7.5
4
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH
SetupTime, BE/FWFT beforeMRS1 andMRS2 HIGH
Setup Time, SPM before MRS1 and MRS2 HIGH
SetupTime,FS0/SDbeforeCLKA↑
tBES
tSPMS
tSDS
tSENS
tFWS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
SetupTime,BE/FWFTbeforeCLKA↑
0
0
HoldTime, A0-A35afterCLKA↑ andC0-C17afterCLKC↑
0.5
0.5
1
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB after
CLKB↑;WENCandMBCafterCLKC↑
1
(2)
tRSTH
tFSH
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑
4
2
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH
HoldTime, FS0/SDafterCLKA↑
tBEH
2
2
tSPMH
tSDH
2
2
0.5
0.5
2
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
2
(3)
tSKEW1
SkewTime, betweenCLKA↑andCLKB↑for EFB/ORBand FFA/IRA;betweenCLKA↑
and CLKC↑ for EFA/ORA and FFC/IRC
5
7.5
(3,4)
tSKEW2
SkewTime,betweenCLKA↑andCLKB↑forAEBandAFA; between CLKA↑and CLKC↑
for AEA and AFC
12
—
12
—
ns
NOTES:
1. For 10ns speed grade only: VCC = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
8
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3626L10(1) IDT72V3626L15
IDT72V3636L10(1) IDT72V3636L15
IDT72V3646L10(1) IDT72V3646L15
Symbol
tA
Parameter
Min.
2
Max.
6.5
6.5
6.5
6.5
6.5
6.5
Min.
2
Max.
10
8
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B17
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to FFC/IRC
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑toEFB/ORB
PropagationDelayTime,CLKA↑toAEAandCLKB↑toAEB
Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC
tWFF
tREF
tPAE
tPAF
2
2
ns
1
1
8
ns
1
1
8
ns
1
1
8
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH, CLKB↑ to MBF1
HIGH, and CLKC↑ to MBF2 LOW
0
0
8
ns
tPMR
tMDV
tRSF
Propagation Delay Time, CLKA↑to B0-B17(2) and CLKC↑toA0-A35(3)
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B17 valid
6.5
10
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and MBF1
HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH
tEN
tDIS
Enable Time, CSA orW/RALOWtoA0-A35Active andCSB LOWtoB0-B17Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH to
B0-B17atHIGHimpedance
NOTES:
1. For 10ns speed grade only: VCC = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
9
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
aFIFOfollowingaMasterResetwouldbeinconvenient. SeeFigure6and7
forPartialResettimingdiagrams.
SIGNALDESCRIPTION
MASTER RESET (MRS1, MRS2)
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memoryoftheIDT72V3626/72V3636/72V3646undergoesacompletereset
bytakingitsassociatedMasterReset(MRS1)inputLOWforatleastfourPort
AClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions. The
FIFO2memoryundergoes acompleteresetbytakingits associatedMaster
Reset(MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions. TheMasterResetinputscanswitch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag(FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB)LOW,theAlmost-Emptyflag(AEA,AEB)LOWandtheAlmost-Fullflag
(AFA,AFC)HIGH. AMasterResetalsoforces the associatedMailboxFlag
(MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraMasterReset,the
FIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles. Thenthe
FIFO is ready to be written to.
ALOW-to-HIGHtransitionontheFIFO1MasterReset(MRS1)inputlatches
thevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytes
aretransferredthroughPortsBandC. ItalsolatchesthevaluesoftheFlagSelect
(FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing the
Almost-FullandAlmost-Emptyoffsetprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearsthe
flagoffsetregistersofFIFO2(X2,Y2). ALOW-to-HIGHtransitionontheFIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
thevaluesoftheFlagSelect(FS0,FS1)andSerialProgrammingMode(SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method(fordetails see Table 1, FlagProgramming, andAlmost-Emptyand
Almost-Fullflagoffsetprogrammingsection). TherelevantMasterResettiming
diagrams can be found in Figure 4 and 5.
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
isactive,permittingachoiceofBig-orLittle-Endianbytearrangementfordata
writtentoPortCorreadfromPortB.Thisselectiondeterminestheorderbywhich
bytes(orwords)ofdataaretransferredthroughthoseports.Forthefollowing
illustrations,notethatbothports B andCareconfiguredtohaveabyte(ora
word) bus size.
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata
ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAastheleast
significantbyte(word)ofthelongword.
ALOWontheBE/FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
gofromLOWtoHIGHwillselecta Little-Endianarrangement. Whendata is
movinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)of
thelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAasthemost
significantbyte(word)ofthelongword.RefertoFigure2and3forillustrations
oftheBEfunction.SeeFigure4(FIFO1MasterReset)and5(FIFO2Master
Reset)forEndianSelecttimingdiagrams.
— TIMING MODE SELECTION
NotethatMBCmustbeHIGHduringMasterReset(untilFFA/IRAandFFC/
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through(FWFT)mode.OncetheMasterReset(MRS1, MRS2)inputisHIGH,
aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(forFIFO1)andCLKC(forFIFO2)willselectIDTStandardmode.Thismode
usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare
any words present in the FIFO memory. It uses the Full Flag function (FFA,
FFC)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requestedusinga formalreadoperation.
OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKC(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata
outputs(A0-A35orB0-B17).ItalsousestheInputReadyfunction(IRA,IRC)
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata
outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master Reset.
PARTIAL RESET (PRS1, PRS2)
TheFIFO1memoryofthesedevicesundergoesalimitedresetbytaking
its associated Partial Reset (PRS1) input LOW for at least four Port A Clock
(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.TheFIFO2
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(PRS2)
inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock(CLKC)
LOW-to-HIGHtransitions.ThePartialResetinputscanswitchasynchronously
totheclocks.APartialResetinitializestheinternalreadandwritepointersand
forcestheFull/InputReadyflag(FFA/IRA,FFC/IRC)LOW,theEmpty/Output
Readyflag(EFA/ORA,EFB/ORB)LOW,theAlmost-Emptyflag(AEA,AEB)
LOW,andtheAlmost-Fullflag(AFA,AFC)HIGH.APartialResetalsoforces
theMailboxFlag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.Aftera
PartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClock
cycles.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
10
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose significantbitofthebinarynumberineachcase.Validprogrammingvaluesfor
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation. Refer the registers range from 1 to 252 for the IDT72V3626; 1 to 508 for the
toFigure4(FIFO1MasterReset)andFigure5(FIFO2MasterReset)forFirst IDT72V3636;and1to1,020fortheIDT72V3646.AfteralltheOffsetregisters
WordFallThroughselecttimingdiagrams.
are programmed from Port A, the Port C Full/Input Ready flag (FFC/IRC) is
setHIGH,andbothFIFOsbeginnormaloperation.RefertoFigure8foratiming
diagramillustrationforparallelprogrammingoftheflagoffsetvalues.
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
FourregistersintheseFIFOsareusedtoholdtheoffsetvaluesfortheAlmost-
EmptyandAlmost-Fullflags.ThePortBAlmost-Emptyflag(AEB)Offsetregister — SERIAL LOAD
islabeledX1andthePortAAlmost-Emptyflag(AEA)Offsetregisterislabeled
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
X2.ThePortAAlmost-Fullflag(AFA)OffsetregisterislabeledY1andthePort withSPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
CAlmost-Fullflag(AFC)OffsetregisterislabeledY2.Theindexofeachregister transitionofMRS1andMRS2.Afterthisresetiscomplete,theXandYregister
namecorrespondstoitsFIFOnumber.TheOffsetregisterscanbeloadedwith valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH
preset values during the reset of a FIFO, programmed in parallel using the transitionofCLKAthattheFS1/SENinputisLOW.Thereare32-,36-,or40-
FIFO’sPortAdatainputs,orprogrammedinserialusingtheSerialData(SD) bitwritesneededtocompletetheprogrammingfortheIDT72V3626,IDT72V3636,
input (see Table 1).
or IDT72V3646, respectively. The four registers are written in the order Y1,
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard X1,Y2andfinally,X2.Thefirst-bitwritestoresthemostsignificantbitoftheY1
andFWFTmodes.
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
register value can be programmed from 1 to 252 (IDT72V3626), 1 to 508
(IDT72V3636), or 1 to 1,020 (IDT72V3646).
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
WhentheoptiontoprogramtheOffsetregistersseriallyischosen,thePort
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM) AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
andatleastoneoftheflagselectinputsmustbeHIGHduringtheLOW-to-HIGH FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
transitionofitsMasterReset(MRS1andMRS2)input.Forexample,toloadthe isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFC/
presetvalueof64intoX1andY1,SPM,FS0andFS1mustbeHIGHwhenFlFO1 IRC)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until
reset (MRS1) returns HIGH. Flag Offset registers associated with FIFO2 are allregisterbitsarewritten.FFC/IRCissetHIGHbytheLOW-to-HIGHtransition
loadedwithoneofthepresetvaluesinthesamewaywithFIFO2MasterReset ofCLKCafterthelastbitis loadedtoallownormalFIFO2operation.
(MRS2)toggledsimultaneouslywithFIFO1MasterReset(MRS1).Forrelevant
Preset value loading timing diagrams, see Figure 4 and 5.
SeeFigure9timingdiagram,SerialProgrammingoftheAlmost-FullFlag
andAlmost-EmptyFlagOffsetValuesafterReset(IDTStandardandFWFT
Modes).
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster FIFO WRITE/READ OPERATION
ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW
ThestateofthePortAdata(A0-A35)outputsiscontrolledbyPortAChip
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is Select(CSA)andPortAWrite/ReadSelect(W/RA).TheA0-A35outputsare
complete,thefirstfourwritestoFIFO1donotstoredatainRAMbutloadtheOffset inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35
registersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedbytheOffset outputs are active whenbothCSA andW/RAare LOW.
registersare(A7-A0),(A8-A0),or(A9-A0)fortheIDT72V3626,IDT72V3636,
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
orIDT72V3646,respectively.Thehighestnumberedinputisusedasthemost transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis
TABLE 1 — FLAG PROGRAMMING
SPM
FS1/SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
↑
X
↑
X
↑
↑
↑
↑
↑
↑
64
X
H
64
64
H
16
X
H
16
16
H
8
X
H
8
ParallelprogrammingviaPortA
SerialprogrammingviaSD
Reserved
8
ParallelprogrammingviaPortA
SerialprogrammingviaSD
Reserved
H
L
L
L
Reserved
Reserved
L
Reserved
Reserved
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
11
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
Data A(A0-A35) I/O
PORT FUNCTION
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
High-Impedance
Input
None
None
H
H
L
Input
FIFO1 write
Mail1write
H
L
↑
Input
X
↑
Output
Output
Output
Output
None
L
H
L
L
FIFO2read
None
L
H
H
X
↑
L
H
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
RENB
MBB
CLKB
Data B (B0-B17) Outputs
PORT FUNCTION
H
L
L
L
L
X
L
X
L
X
X
↑
High-Impedance
Output
None
None
H
L
L
Output
FIFO1read
H
H
X
↑
Output
None
H
Output
Mail1 read (set MBF1 HIGH)
TABLE 4 — PORT C ENABLE FUNCTION TABLE
WENC
MBC
CLKC
Data C (C0-C17) Inputs
PORT FUNCTION
H
H
L
L
L
H
L
↑
↑
X
X
Input
Input
Input
Input
FIFO2 write
Mail2write
None
H
None
IfENAis LOWduringa clockcycle, eitherCSA orW/RAmaychange states
duringthe setupandholdtime windowofthe cycle. This is alsotrue forCSB
whenRENBis LOW.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
registersonlywhenareadisselectedusingCSA,W/RA,ENAandMBAatPort
A or using CSB, RENB and MBB at Port B.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
ReadClock.Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Instead, data residing in the FIFO’s memory array is clocked to the output
registeronlywhenareadisselectedusingCSA,W/RA,ENAandMBAatPort
A or using CSB, RENB and MBB at Port B. Relevant write and read timing
diagramsforPortAcanbefoundinFigure10and15. Relevantreadandwrite
timingdiagramsforPortBandPortC,togetherwithBus-MatchingandEndian
select operation, can be found in Figure 11 to 14.
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand
writesonPortAareindependentofanyconcurrentPortBandPortCoperation.
ThestateofthePortBdata(B0-B17)outputsiscontrolledbythePortBChip
Select(CSB).TheB0-B17outputsareinthehigh-impedancestatewhenCSB
is HIGH. The B0-B17 outputs are active when CSB is LOW.
DataisreadfromFIFO1totheB0-B17outputsbyaLOW-to-HIGHtransition
of CLKB when CSB is LOW, RENB is HIGH, MBB is LOW and EFB/ORB is
HIGH(seeTable3).FIFOreadsonPortBareindependentofanyconcurrent
Port A and Port C operations.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transitionofCLKCwhenWENBisHIGH,MBCisLOW,andFFC/IRCisHIGH
(seeTable4).FIFOwritesonPortCareindependentofanyconcurrentPort
A and Port B operation.
ThesetupandholdtimeconstraintsforCSAandW/RAwithregardtoCLKA
as well as CSB with regard to CLKB are only for enabling write and read
operationsandarenotrelatedtohigh-impedancecontrolofthedataoutputs.
12
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
pointer and read pointer comparator that indicates when the FIFO memory
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop status is empty, empty+1, or empty+2.
stages.Thisisdonetoimproveflagsignalreliabilitybyreducingtheprobability
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
of metastable events when CLKA operates asynchronously with respect to totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
eitherCLKBorCLKC.EFA/ORA,AEA,FFA/IRA,andAFAaresynchronized flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin
toCLKA.EFB/ORBandAEBaresynchronizedtoCLKB.FFC/IRCandAFC memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
aresynchronizedtoCLKC.Tables5and6showtherelationshipofeachport oftheportclockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
flag to FIFO1 and FIFO2.
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthe
thirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simultaneously
forcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFOoutput
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready register.
(ORA,ORB)functionisselected.WhentheOutputReadyflagisHIGH,new
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
data is present in the FIFO output register. When the Output Ready flag is Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
LOW, the previous data word is present in the FIFO output register and cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
attemptedFIFOreadsareignored.
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected. twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
Whenthe EmptyFlagis HIGH, data is available inthe FIFO’s RAMmemory thetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOWuntil
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare the Empty Flag HIGH; only then can data be read.
ignored.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
The Empty/Output Ready flag of a FIFO is synchronized to the port clock clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,the attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
FIFOreadpointeris incrementedeachtimeanewwordis clockedtoits output can be the first synchronization cycle (see Figure 16, 17, 18 and 19).
register.ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3626
IDT72V3636
IDT72V3646
EFB/ORB
AEB
L
AFA
H
FFA/IRA
0
1toX1
0
1toX1
0
1toX1
L
H
H
H
H
H
H
H
H
L
L
H
(X1+1)to[256-(Y1+1)]
(256-Y1)to255
256
(X1+1)to[512-(Y1+1)]
(512-Y1)to511
512
(X1+1)to[1,024-(Y1+1)]
(1,024-Y1)to1,023
1,024
H
H
H
L
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKA
Synchronized
to CLKC
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3626
IDT72V3636
IDT72V3646
EFA/ORA
AEA
AFC
FFC/IRC
0
0
1toX2
0
1toX2
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
1toX2
(X2+1)to[256-(Y2+1)]
(256-Y2)to255
256
(X2+1)to[512-(Y2+1)]
(512-Y2)to511
512
(X2+1)to[1,024-(Y2+1)]
(1,024-Y2)to1,023
1,024
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.
13
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the
These are dualpurpose flags. InFWFTmode, the InputReady(IRAand IDT72V3626,IDT72V3636,orIDT72V3646respectively.AnAlmost-Fullflag
IRC)functionisselected.InIDTStandardmode,theFullFlag(FFAandFFC) is HIGH when the number of words in its FIFO is less than or equal to [256-
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis (Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3626, IDT72V3636, or
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory IDT72V3646respectively. Note thata data wordpresentinthe FIFOoutput
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites registerhas beenreadfrommemory.
to the FIFO are ignored.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
The Full/InputReadyflagofa FlFOis synchronizedtothe portclockthat requiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewleveloffill.
writes data toits array. ForbothFWFTandIDTStandardmodes, eachtime Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]or
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine lesswordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer sincethereadthatreducedthenumberofwordsinmemoryto[256/512/1,024-
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. (Y+1)].AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGHtransition
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready ofitssynchronizingclockaftertheFIFOreadthatreducesthenumberofwords
to be written to in a minimum of two cycles of the Full/Input Ready flag inmemoryto[256/512/1,024-(Y+1)].ALOW-to-HIGHtransitionofanAlmost-
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthantwo Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccursat
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe time tSKEW2 or greater after the read that reduces the number of words in
nextmemorywritelocationhasbeenread.ThesecondLOW-to-HIGHtransition memoryto[256/512/1,024-(Y+1)].Otherwise,thesubsequentsynchronizing
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input clock cycle may be the first synchronization cycle (see Figure 26 and 27).
Ready flag HIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock MAILBOX REGISTERS
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 20, 21, 22, and 23).
EachFIFOhasan18-bitbypassregisterallowingthepassageofcommand
andcontrolinformationfromPortAtoPortBorfromPortCtoPortAwithoutputting
itinqueue.TheMailboxSelect(MBA,MBB andMBC)inputschoosebetween
amailregisterandaFIFOforaportdatatransferoperation.Theusablewidth
ofboththeMail1andMail2registersmatchestheselectedbussizeforportsB
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads and C.
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
WhensendingdatafromPortAtoPortBviatheMail1Register,thefollowing
a write pointer and read pointer comparator that indicates when the FIFO isthecase: ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Register
memory status is almost-empty, almost-empty+1, or almost-empty+2. The when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister theselectedPortBbussizeis18bits,thentheusablewidthoftheMail1Register
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset, employsdatalinesA0-A17.(Inthiscase,A18-A35aredon’tcareinputs.) Ifthe
programmedfromPortA,orprogrammedserially(seetheAlmost-Emptyflag selectedPortBbus sizeis 9bits,thentheusablewidthoftheMail1Register
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW employs data lines A0-A8. (Inthis case, A9-A35are don’tcare inputs.)
whenits FIFOcontains Xorless words andis HIGHwhenits FIFOcontains
(X+1)ormorewords.AdatawordpresentintheFIFOoutputregisterhasbeen isthecase: ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
readfrommemory. whenaPortCwriteisselectedbyWENCwithMBCHIGH.IftheselectedPort
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock Cbussizeis18bits,thentheusablewidthoftheMail2Registeremploysdata
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel linesC0-C17.IftheselectedPortCbussizeis9bits,thentheusablewidthof
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords theMail2RegisteremploysdatalinesC0-C8.(Inthiscase,C9-C17aredon’t
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe careinputs.)
writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost- Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. mailregisterwhentheportmailboxselectinputisHIGH.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 24 and 25).
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadisselectedbyCSB,andRENBwithMBBHIGH.
Foran18-bitbus size,18bits ofmailboxdataareplacedonB0-B17.Forthe
9-bitbussize,9bitsofmailboxdataareplacedonB0-B8.(Inthiscase,B9-B17
ALMOST-FULL FLAGS (AFA, AFC)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites areindeterminate.)
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory onCLKAwhena PortAreadis selectedbyCSA, W/RA, andENAwithMBA
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined HIGH.Thedatainamailregisterremainsintactafteritisreadandchangesonly
bythecontentsofregisterY1forAFAandregisterY2forAFC.Theseregisters whennewdataiswrittentotheregister.Foran18-bitbussize,18bitsofmailbox
areloadedwithpresetvaluesduringaFlFOreset,programmedfromPortA, dataappearon A18-A35. (Inthiscase,A0-A17areindeterminate.) Fora9-
or programmed serially (see Almost-Empty flag and Almost-Full flag offset bitbus size,9bits ofmailboxdataappearonA18-A26.(Inthis case,A0-A17
programmingsection).AnAlmost-FullflagisLOWwhenthenumberofwords andA27-A35areindeterminate.)
14
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
Thedatainamailregisterremainsintactafteritisreadandchangesonly mailboxregisters.Furthermore,boththeword-andbyte-sizebusselections
whennewdataiswrittentotheregister.TheEndianSelectfeaturehasnoeffect limitthewidthofthedatabusthatcanbeusedformailregisteroperations.In
onmailboxdata.
thiscase,onlythosebytelanesbelongingtotheselectedword-orbyte-size
NotethatMBCmustbeHIGHduringMasterReset(until FFA/IRAand FFC/ buscancarrymailboxdata.Theremainingdataoutputswillbeindeterminate.
IRCgoHIGH. MBAandMBBaredon'tcareinputsduringMasterReset.For Theremainingdatainputswillbedon’tcareinputs.Forexample,whenaword-
mailregisterandmailregisterflagtimingdiagrams,seeFigure28and29.
sizebusisselectedonPortB,thenmailboxdatacanbetransmittedonlyfrom
A0-A17toB0-B17.Whenabyte-sizebusisselectedonPortB,thenmailbox
datacanbetransmittedonlyfromA0-A8toB0-B8.Similarly,whenaword-size
busisselectedonPortC,thenmailboxdatacanbetransmittedonlyfromC0-
C17toA18-A35.Whenabyte-sizebusisselectedonPortC,thenmailboxdata
canbetransmittedonlyfromC0-C8toA18-A26.
BUS SIZING
PortBmaybeconfiguredineitheran18-bitwordora9-bitbyteformatfor
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independentlyforPorts BandC. The levelappliedtothe PortBSize Select
(SIZEB)inputdeterminesthePortBbussizeandthelevelappliedtothePort
CSizeSelect(SIZEC)inputdeterminesthePortCbussize.Theselevelsshould
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.SincePort
bestaticthroughoutFIFOoperation.Bothbussizeselectionsareimplemented Bcanhave a byte orwordsize, onlythe firstone ortwobytes appearonthe
atthecompletionofMasterReset,bythetimetheFull/InputReadyflagisset selectedportionoftheFIFO1outputregister,withtherestofthelongwordstored
HIGH, as shown in Figure 2 and 3.
TwodifferentmethodsforsequencingdatatransferareavailableforPorts the long word to the FIFO1 output register in the order shown by Figure 2.
BandCregardlessofwhetherthebussizeselectionisbyte-orword-size.They WhenreadingdatafromFIFO1inbyteformat,theunusedB9-B17outputs
inauxiliaryregisters.Inthiscase,subsequentFIFO1readsoutputtherestof
arereferredtoasBig-Endian(mostsignificantbytefirst)andLittle-Endian(least areindeterminate.
significantbytefirst).ThelevelappliedtotheBig-EndianSelect(BE)inputduring
theLOW-to-HIGHtransitionofMRS1andMRS2selectstheendianmethodthat BUS-MATCHING FIFO2 WRITES
willbeactiveduringFIFOoperation.ThisselectionappliestobothportsBand
C.TheendianmethodisimplementedatthecompletionofMasterReset,bythe
time the Full/Input Ready flag is set HIGH, as shown in Figure 2 and 3 (see
EndianSelectionsection).
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
onthesedevices.Bus-Matchingoperationsaredoneafterdataisreadfrom
theFIFO1RAM(PortB)andbeforedataiswrittentotheFIFO2RAM(PortC).
The Endian select operations are not available when transferring data via
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers.TheCLKCrisingedgethatwritesthefourthbyteorthesecondword
oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.
The bytes are arranged in the manner shown in Figure 3.
WhenwritingdatatoFIFO2inbyteformat,theunusedC9-C17inputsare
don'tcareinputs.
15
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26 A18
–
A35–
A27
A17–
A9
A8–A0
BYTE ORDER ON PORT A:
D
A
B
C
Write to FIFO1
B17–
B9
B8
–
B0
BYTE ORDER ON PORT B:
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
L
A
B
B17–
B9
B8
–
B0
C
D
(b) WORD SIZE
–
–
BIG ENDIAN
B17–
B9
B8–
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
L
SIZEB
L
C
D
B17–
B9
B8
–
B0
A
B
(c) WORD SIZE
LITTLE ENDIAN
B17
B17
B17
–
–
–
–
B9
B9
B9
B8
B8
–
B0
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
H
A
–
B
B8
–
B0
3rd: Read from FIFO1
4th: Read from FIFO1
C
B17
B9
B8
–
B0
D
(d) BYTE SIZE
–
BIG ENDIAN
B17–
B9
B8–
B0
BE SIZEB
1st: Read from FIFO1
2nd: Read from FIFO1
D
L
H
B17
B17
B17
–
B9
B8–
B0
C
–
B9
B9
B8
–
B0
B
3rd: Read from FIFO1
–
B8–
B0
A
4th: Read from FIFO1
4665 drw 03a
(e) BYTE SIZE
–
LITTLE ENDIAN
Figure 2. Port B Bus Sizing
16
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26
A18
A8
A0
A35
A27
A17
A9
BYTE ORDER ON PORT A:
D
A
B
C
Read from FIFO2
C17
C9
C9
C8
C0
C0
BYTE ORDER ON PORT C:
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
L
A
B
C17
C8
C
D
(b) WORD SIZE BIG ENDIAN
C17
C9
C8
C0
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
L
SIZEC
L
C
D
C17
C9
C8
A
B
(c) WORD SIZE LITTLE ENDIAN
C17
C9
C9
C9
C9
C8
C8
C8
C8
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
H
A
C17
C17
C17
C0
B
C0
C0
3rd: Write to FIFO2
4th: Write to FIFO2
C
D
(d) BYTE SIZE BIG ENDIAN
C17
C17
C17
C17
C9
C9
C9
C9
C8
C0
BE SIZEC
1st: Write to FIFO2
2nd: Write to FIFO2
D
L
H
C8
C8
C0
C0
C
B
3rd: Write to FIFO2
C8
C0
A
4th: Write to FIFO2
4665 drw 04
(e) BYTE SIZE LITTLE ENDIAN
Figure 3. Port C Bus Sizing
17
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
1
2
tRSTH
t
RSTS
MRS1
tBEH
t
BES
tFWS
BE/FWFT
BE
FWFT
t
SPMH
t
SPMS
SPM
FS1,FS0
FFA/IRA
t
FSS
t
FSH
0,1
t
WFF
t
WFF
(2)
t
REF
EFB/ORB
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
4665 drw 05
NOTES:
1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)
1
2
CLKC
CLKA
tRSTH
t
RSTS
MRS2(3)
t
BES
tBEH
tFWS
BE/FWFT
BE
FWFT
t
SPMH
t
SPMS
SPM
FS1,FS0
FFC/IRC
t
FSS
tFSH
0,1
t
WFF
tWFF
(2)
REF
t
EFA/ORA
AEA
t
t
RSF
RSF
AFC
t
RSF
MBF2
4665 drw 06
NOTES:
1. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
3. MRS2 must toggle simultaneously with MRS1.
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)
18
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
tRSTH
t
RSTS
PRS1
t
WFF
t
WFF
FFA/IRA
(2)
REF
t
EFB/ORB
AEB
t
RSF
t
RSF
AFA
t
RSF
MBF1
4665 drw 07
NOTES:
1. MRS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 6. FIFO1 Partial Reset (IDT Standard and FWFT Modes)
CLKC
CLKA
t
RSTS
tRSTH
PRS2
t
WFF
t
WFF
FFC/IRC
(2)
REF
t
EFA/ORA
t
RSF
AEA
t
RSF
AFC
t
RSF
MBF1
4665 drw 08
NOTES:
1. MRS2 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
Figure 7. FIFO2 Partial Reset (IDT Standard and FWFT Modes)
19
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
4
MRS1,
MRS2
t
FSS
t
FSH
SPM
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FFA/IRA
(1)
tSKEW1
tENS2
tENH
ENA
tDH
tDS
A0-A35
First Word to FIFO1
AEA Offset
AFA Offset
AEB Offset
AFC Offset
(Y2)
(X2)
(Y1)
(X1)
CLKC
1
2
t
WFF
FFC/IRC
4665 drw 09
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA
and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
t
FSH
t
FSS
SPM
t
WFF
(1)
SKEW
t
FFA/IRA
FS1/SEN
FS0/SD(3)
t
SENS
t
SENH
t
FSS
t
SENS
tSENH
tSPH
tSDS
t
SDH
tSDS
tSDH
AFA Offset
(Y1) MSB
AEA Offset
(X2) LSB
CLKC
4
t
WFF
4665 drw 10
FFC/IRC
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA
and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
20
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA HIGH
t
ENS1
ENS2
t
ENH
ENH
CSA
t
t
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
tENS2
tENS2
tENH
tENH
t
tDH
t
DS
W1(1)
W2(1)
A0-A35
No Operation
4665 drw11
NOTE:
1. Written to FIFO1.
Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKC
FFC/IRC
HIGH
t
ENS2
t
ENS2
ENS2
t
ENH
t
ENH
MBC
t
ENS2
t
t
ENH
tENH
WENC
tDH
tDS
C0-C17
4665 drw12
DATA SIZE TABLE FOR WORD WRITES TO FIFO2
(1)
SIZE MODE
WRITE
NO.
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
SIZEC
BE
C17-C9
C8-C0
A35-A27
A26-A18
A17-A9
A8-A0
L
L
H
1
2
A
C
B
D
A
B
C
D
L
1
2
C
A
D
B
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 11. Port C Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
21
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
FFC/IRC HIGH
t
ENS2
t
ENH
ENH
t
ENH
MBC
tENS2
t
t
ENS2
t
ENH
WENC
tDS
tDH
C0-C8
4665 drw 13
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2
SIZE MODE(1)
WRITE
NO.
DATA WRITTEN
DATA READ FROM FIFO2
TO FIFO2
SIZEC
BE
C8-C0
A
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
1
2
3
4
B
H
H
A
B
C
D
C
D
D
C
H
L
A
B
C
D
B
A
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 12. Port C Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
CLKB
EFB/ORB HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
Read 2
t
DIS
DIS
t
A
t
MDV
t
A
t
EN
B0-B17
Read 1
Read 2
Previous Data
(Standard Mode)
OR
t
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
4665 drw 14
DATA SIZE TABLE FOR WORD READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
B
H
H
H
A
B
C
D
1
2
1
2
A
C
C
A
D
L
A
B
C
D
D
B
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 13. Port B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
22
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
EFB/ORB
HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
t
DIS
DIS
t
MDV
t
A
t
A
t
A
tA
t
EN
B0-B8
Previous Data
Read 2
Read 3
Read 4
Read 5
Read 1
(Standard Mode)
t
t
MDV
OR
tA
tA
t
A
t
A
t
EN
B0-B8
Read 1
Read 2
Read 3
Read 4
(FWFT Mode)
4665 drw 15
NOTE:
1. Unused bytes B9-B17 are indeterminate for byte-size reads.
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
B8-B0
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB must be static throughout device operation.
Figure 14. Port B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA
HIGH
CSA
W/RA
MBA
t
ENS2
t
ENS2
tENH
tENH
tENH
t
ENS2
ENA
No Operation
W2(1)
t
MDV
tDIS
t
A
tA
t
EN
A0-A35
W1(1)
W2(1)
Previous Data
(
Standard Mode)
tDIS
t
MDV
OR
tA
t
A
t
EN
A0-A35
(FWFT Mode)
W3(1)
W1(1)
4665 drw16
NOTE:
1. Read From FIFO2.
Figure 15. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
23
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
WRA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDS
tDH
W1
A0-A35
t
CLK
(1)
SKEW1
tCLKH
tCLKL
t
CLKB
3
1
2
t
REF
t
REF
FIFO1 Empty
LOW
ORB
CSB
MBB LOW
tENS2
tENH
RENB
tA
tA
Read 1
Read 2
B0-B17
4665 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 16. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
24
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
tCLKL
CLKA
LOW
HIGH
CSA
WRA
tENH
tENS2
MBA
tENS2
tENH
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
CLKHtCLK
tCLKL
(1)
SKEW1
t
t
CLKB
1
2
t
REF
t
REF
EFB
CSB
FIFO1 Empty
LOW
MBB LOW
tENS2
tENH
RENB
B0-B17
NOTES:
tA
tA
Read 1
Read 2
4665 drw18
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 17. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
25
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
CLKH
tCLKL
t
CLKC
t
ENS2
ENS2
t
ENH
MBC
t
t
ENH
WENC
IRC
HIGH
tDH
tDS
tDH
tDS
Write 1
Write 2
C0-C17
t
CLK
(1)
SKEW1
t
CLKH
tCLKL
t
CLKA
1
2
3
t
REF
t
REF
ORA FIFO2 Empty
CSA LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
A0-A35
W1
4665 drw19
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
26
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
CLKH
tCLKL
t
CLKC
tENS2
tENH
MBC
tENS2
tENH
WENC
FFC
HIGH
tDS
tDH
t
DS
tDH
Write 1
Write 2
C0-C17
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
t
REF
t
REF
EFA
CSA
FIFO2 Empty
LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
A0-A35
NOTES:
tA
W1
4665 drw20
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge
and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
27
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB LOW
LOW
MBB
tENS2
tENH
RENB
ORB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
CLK tCLKL
tCLKH
CLKA
IRA
1
2
t
WFF
t
WFF
FIFO1 Full
CSA LOW
W/RA HIGH
tENH
tENS2
MBA
tENH
tENS2
ENA
tDS
tDH
Write
A0-A35
4665 drw21
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
28
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
MBB
tENS2
tENH
RENB
EFB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
t
CLKH CLK tCLKL
CLKA
1
2
t
WFF
t
WFF
FFA
FIFO1 Full
CSA LOW
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
Write
A0-A35
4665 drw22
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively (the word-size case is shown).
Figure 21. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
29
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
W/RA
LOW
MBA
tENS2
tENH
ENA
ORA
HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0-A35
(1)
tCLK
t
tCLKH
tCLKL
CLKC
1
2
t
WFF
t
WFF
IRC FIFO2 Full
tENS2
tENH
MBC
WENC
C0-C17
t
ENS2
t
ENH
tDS
tDS
tDH
tDH
Write
4665 drw23
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
30
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
W/RA
LOW
MBA
ENA
tENS2
tENH
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKC
1
2
t
WFF
tWFF
FIFO2 Full
FFC
t
ENS2
ENS2
t
ENH
MBC
ENC
t
tENH
tDH
tDS
tDS
tDH
Write
C0-C17
To FIFO2
4665 drw24
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge
and rising CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 23. FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENH
tENS2
ENA
(1)
tSKEW2
CLKB
1
2
t
PAE
t
PAE
AEB
X1 Word in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
RENB
4665 drw25
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 24. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
31
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
tENH
tENS2
WENC
CLKA
(1)
tSKEW2
1
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
4665 drw 26
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
tPAF
(D-Y1) Words in FIFO1
ENH
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
t
tENS2
RENB
4665 drw 27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3626, 512 for the IDT72V3636, 1,024 for the IDT72V3646.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKC
tENH
tENS2
WENC
AFC
t
PAF
t
PAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
4665 drw 28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge
and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3626, 512 for the IDT72V3636, 1,024 for the IDT72V3646.
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
32
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
t
ENS1
ENS2
t
ENH
CSA
W/RA
MBA
ENA
t
tENH
t
ENS2
t
ENH
ENH
t
ENS2
t
tDH
t
DS
W1
A0-A35
CLKB
MBF1
t
PMF
t
PMF
CSB
MBB
tENH
tENS2
RENB
t
PMR
tDIS
tEN
t
MDV
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
B0-B17
4665 drw29
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port
B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will
be indeterminate).
Figure 28. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
33
IDT72V3626/72V3636/72V3646 CMOS 3.3VTRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
tENS2
tENH
MBC
ENC
tENS2
tENH
tDH
tDS
C0-C17
CLKA
W1
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
PMR
tEN
t
MDV
tDIS
A0-A35
W1 (Remains valid in Mail2 Register after read)
FIFO2 Output Register
4665 drw30
NOTE:
1. IfPortCis configuredforwordsize, data canbe writtentothe Mail2registerusingC0-C17. Inthis firstcase, A18-A35willhave validdata (A0-A17willbe indeterminate). IfPortCis configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
Figure 29. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
34
TM
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFO
WITHBUS-MATCHING256x36x2,512x36x2,1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330Ω
From Output
Under Test
30 pF (1)
510Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
Input
1.5V
1.5V
GND
GND
3V
t
S
th
tW
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
Input
1.5V
1.5V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
t
PZL
GND
tPLZ
3V
≈ 3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4665 drw31
NOTE:
1. Includes probe and jig capacitance.
Figure 30. Load Circuit and Voltage Waveforms
35
ORDERING INFORMATION
IDT
XXXXXX
X
XX
XX
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
PF
Thin Quad Flat Pack (TQFP, PK128-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
256 x 36 x 2 3.3V Triple Bus SyncFIFO
with Bus-Matching
72V3626
72V3636 512 x 36 x 2 3.3V Triple Bus SyncFIFO
with Bus-Matching
72V3646
1,024 x 36 x 2 3.3V Triple Bus SyncFIFO
with Bus-Matching
4665 drw 32
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
12/12/2000
03/21/2001
08/01/2001
pgs. 12 and 21.
pgs. 6 and 7.
pgs. 6, 8, 9 and 36.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
36
相关型号:
IDT72V3626L15PF
3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
IDT
©2020 ICPDF网 联系我们和版权申明