IDT72V3643L12PF8 [IDT]
FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128;
| 型号： | IDT72V3643L12PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片 |
| 文件： | 总27页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM
WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
PRELIMINARY
IDT72V3623
IDT72V3633
IDT72V3643
• Big- or Little-Endian format for word and byte bus sizes
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
FEATURES:
• Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3633–512 x 36
IDT72V3643–1,024 x 36
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Clock frequencies up to 83 MHz (8 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723623/723633/723643
• Industrial temperature range (–40oC to +85oC) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
ENA
Logic
MBA
36
RAM ARRAY
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
256 x 36
512 x 36
RS1
RS2
PRS
1,024 x 36
36
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
9
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
4662 drw 01
MBF2
June 1999
1
1999 Integrated Device Technology, Inc.
DSC-4662/-
IDT72V3623/33/43
IDT
fastas8ns. The256/512/1,024x36dual-portSRAMFIFObuffersdatafrom
PortAtoPortB. FIFOdataonPortBcanoutputin36-bit,18-bit,or9-bitformats
withachoiceofBig-orLittle-Endianconfigurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
DESCRIPTION:
TheIDT72V3623/72V3633/72V3643arepinandfunctionallycompatible
versionsoftheIDT723623/723633/723643,designedtorunoffa3.3Vsupply
forexceptionallylowpowerconsumption. Thesedevicesaremonolithic,high-
speed,low-power,CMOSunidirectionalSynchronous(clocked)FIFOmemory
whichsupportsclockfrequenciesupto83MHzandhasreadaccesstimesas
PIN CONFIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A28
A27
A26
A25
A24
A23
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
B15
B14
B13
B12
GND
B11
B10
A14
A13
Vcc
A12
GND
A11
A10
4662 drw 02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT
IDT72V3623/33/43
each port are independent of one another and can be asynchronous or areselectedintheFirstWordFallThroughmode. IRindicateswhetherornot
coincident. The enables for each port are arranged to provide a simple theFIFOhas availablememorylocations. ORshows whethertheFIFOhas
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- data available for reading or not. It marks the presence of valid data on the
nouscontrol.
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox
outputs.
TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram-
registers.Themailboxregisters'widthmatchestheselectedPortBbuswidth. mableAlmost-Fullflag(AF).AE indicateswhenaselectednumberofwords
Eachmailboxregisterhas a flag(MBF1andMBF2)tosignalwhennewmail remainintheFIFOmemory. AFindicateswhentheFIFOcontainsmorethan
has beenstored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
aselectednumberofwords.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray intoitsarray. EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
andselectsserialflagprogramming,parallelflagprogramming,oroneofthree readsdatafromitsarray. ProgrammableoffsetsforAEandAFareloaded in
possibledefaultflagoffsetsettings,8,16or64.
parallelusingPortAorinserialviatheSDinput.TheSerialProgrammingMode
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe pin(SPM)makesthisselection.Threedefaultoffsetsettingsarealsoprovided.
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e., TheAEthresholdcanbesetat8,16or64locationsfromtheemptyboundary
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset andtheAFthresholdcanbesetat8,16or64locationsfromthefullboundary.
is useful since it permits flushing of the FIFO memory without changing any Allthese choices are made usingthe FS0andFS1inputs duringReset.
configurationsettings.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A seriestocreategreaterworddepths. Theadditionofexternalcomponentsis
read operation is required to access that word (along with all other words unnecessary.
residing in memory). In the First Word Fall Through mode (FWFT), the first
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread automatically power down. During the power down state, supply current
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
sitate a formal read request). The state of the BE/FWFT pin during Reset inputs)willimmediatelytakethedeviceoutofthePowerDownstate.
determinesthemodeinuse.
TheIDT72V3623/72V3633/72V3643arecharacterizedforoperationfrom
o
o
o
o
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a 0 C to 70 C. Industrial temperature range (-40 C to +85 C) is available by
combinedFull/InputReadyFlag(FF/IR). TheEFandFFfunctionsareselected specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS
inthe IDTStandardmode. EF indicates whetherornotthe FIFOmemoryis technology.
empty. FFshowswhetherthememoryisfullornot. TheIRandORfunctions
3
IDT72V3623/33/43
IDT
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/O
O
36-bitbidirectionaldataportforsideA.
AE
Almost-EmptyFlag
(Port B)
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsin
theFIFOis less thanorequaltothevalueintheAlmost-EmptyBoffsetregister,X.
AF
Almost-FullFlag
(Port A)
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
locations intheFIFOis less thanorequaltothevalueintheAlmost-FullAoffsetregister,Y.
B0-B35
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
Inthis case, dependingonthe bus size, the mostsignificantbyte orwordwrittentoPortAis read
fromPortBfirst. ALOWonBEwillselectLittle-Endianoperation. Inthiscase,theleastsignificant
byteorwordwrittentoPortAisreadfromPortBfirst. AfterMasterReset,thispinselectsthetiming
mode. A HIGH onFWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Oncethetimingmodehasbeenselected,thelevelonFWFTmustbestaticthroughout
deviceoperation.
Fall Through
BM
Bus-MatchSelect
(Port B)
I
I
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endianarrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.
CLKA
CLKB
PortAClock
PortBClock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbe
asynchronous orcoincidenttoCLKA. EF/ORand AE are synchronizedtothe LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The
A0-A35outputs areinthehigh-impedancestatewhenCSA is HIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
The B0-B35outputs are inthe high-impedance state whenCSB is HIGH.
EF/OR
Empty/Output
Ready Flag
(Port B)
O
This is adualfunctionpin.IntheIDTStandardmode,theEFfunctionis selected. EFindicates
whetherornottheFIFOmemoryisempty. IntheFWFTmode,the ORfunctionisselected. ORindicates
thepresenceofvaliddataontheB0-B35outputs,availableforreading. EF/ORissynchronizedtothe
LOW-to-HIGHtransitionofCLKB.
ENA
ENB
FF/IR
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
Full/Input
Ready Flag
(Port A)
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FF functionis selected. FF indicates
whetherornotthe FIFOmemoryis full. Inthe FWFTmode, the IRfunctionis selected. IR
indicates whether or not there is space available for writing to the FIFO memory. FF/IRis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FS1/SEN
FlagOffset
Select1/
SerialEnable,
I
I
FS1/SEN andFS0/SDare dual-purpose inputs usedforflagoffsetregisterprogramming. During
Reset,FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.
Threeoffsetregisterprogrammingmethodsareavailable:automaticallyloadoneofthreepreset
values (8, 16, or 64), parallel load from Port A, and serial load.
FS0/SD
FlagOffset
Select0/
SerialData
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenable
synchronous totheLOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW,arisingedgeon
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
toprogram the offsetregisters is 16 for the 72V3623, 18 for the 72V3633, and 20forthe 72V3643.
ThefirstbitwritestorestheY-registerMSBandthelastbitwritestorestheX-registerLSB.
4
IDT
IDT72V3623/33/43
PIN DESCRIPTIONS (Continued)
Symbol
Name
I/O
Description
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputand
aLOWlevelselectsFIFOdataforoutput.
MBF1
Mail1RegisterFlag
Mail2RegisterFlag
Resets
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
followingeithera Reset(RS1)or Partial Reset (PRS).
MBF2
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.
Writes tothe mail2 registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
followingeithera Reset(RS2)or Partial Reset (PRS).
RS1, RS2
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransitiononRS1selectstheprogramming
method(serialorparallel)andoneofthreeprogrammableflag defaultoffsets. ItalsoconfiguresPort
Bforbus size andendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-
HIGHtransitionsofCLKBmustoccurwhileRS1isLOW.
PRS
PartialReset
I
I
ALOWonthispininitializestheFIFOreadandwritepointerstothefirstlocationofmemoryandsets
the PortBoutputregistertoallzeroes. DuringPartialReset, thecurrentlyselectedbussize,endian
arrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
SIZE
BusSizeSelect
(Port B)
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
whenBMis HIGHselects word(18-bit)bus size. SIZEworks withBMandBEtoselectthebus size
andendianarrangementforPortB. The levelofSIZEmustbe staticthroughoutdevice operation.
SPM
SerialProgramming
Mode
I
I
I
ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallel
programmingordefaultoffsets (8,16,or64).
W/RA
W/RB
PortAWrite/
ReadSelect
AHIGHselectsawriteoperationandaLOWselectsareadoperationonPortAforaLOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGH impedancestatewhenW/RAisHIGH.
ALOWselectsawriteoperationandaHIGHselectsareadoperationonPortBforaLOW-to-HIGH
transitionofCLKB. The B0-B35outputs are inthe HIGHimpedance state whenW/RBis LOW.
PortBWrite/
ReadSelect
5
IDT72V3623/33/43
IDT
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
ο C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ.
Max.
3.6
Unit
V
(1)
VCC
SupplyVoltage
3.0
2
3.3
—
—
—
—
—
VIH
VIL
IOH
IOL
TA
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
VCC+0.5
0.8
V
—
—
—
0
V
–4
mA
mA
ο C
8
70
NOTE:
1. For 12ns (83 MHz operation), Vcc=3.3V +/-0.15V, JEDEC JESD8-A compliant.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3623
IDT72V3633
IDT72V3643
Commercial
tCLK = 12, 15, 20 ns
Symbol
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
Typ.(1)
Max.
Unit
VOH
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
IOH = –4 mA
2.4
—
—
V
VOL
ILI
OutputLogic"0"Voltage
Input Leakage Current (Any Input)
OutputLeakageCurrent
StandbyCurrent
IOL = 8 mA
—
—
—
—
—
—
—
—
—
—
4
0.5
±10
±10
1
V
VI = VCC or 0
VO = VCC or 0
µA
µA
mA
pF
ILO
ICC(2)
CIN
COUT
VI = VCC - 0.2V or 0
InputCapacitance
f = 1 MHz
f = 1 MHZ
—
OutputCapacitance
VO = 0,
8
—
pF
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25οC.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
6
IDT
IDT72V3623/33/43
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3623/72V3633/72V3643with
CLKAandCLKBsettofS. Alldatainputs anddataoutputs changestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3623/
72V3633/72V3643 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
CL
fo
switching frequency of an output
When no read or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is cal-
culated by:
PT = VCC x fS x 0.025 mA/MHz
200
175
150
f
data = 1/2 fS
T
A
= 25oC
= 0 pF
VCC = 3.6V
C
L
VCC = 3.3V
125
100
75
VCC = 3.0V
50
25
0
80
90
0
10
20
30
40
50
60
70
4662 drw 03
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3623/33/43
IDT
TIMINGREQUIREMENTSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
ο
ο
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0 C to +70 C; JEDEC JESD8-A compliant
72V3623L12
72V3633L12
72V3643L12
72V3623L15
72V3633L15
72V3643L15
72V3623L20
72V3633L20
72V3643L20
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Min.
—
12
5
Max.
Min.
—
15
6
Max.
66.7
—
Min.
—
20
8
Max.
Unit
MHz
ns
83
—
—
—
—
—
50
—
—
—
—
—
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
—
ns
Pulse Duration, CLKAandCLKBLOW
5
6
—
8
ns
SetupTime, A0-A35before CLKA↑ andB0-B35before CLKB↑
SetupTime,CSA,beforeCLKA↑;CSB,beforeCLKB↑
3.5
4.5
4
—
5
ns
tENS1
4.5
—
5
ns
tENS2
Setup Time, ENA, W/RA and MBA before CLKA↑; ENB, W/RB
andMBBbefore CLKB↑
3.5
—
4.5
—
5
—
ns
tRSTS
tFSS
SetupTime, RS1 orPRS LOWbefore CLKA↑ orCLKB↑(1)
Setup Time, FS0 and FS1 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
Setup Time, SPM before RS1 HIGH
5
7.5
7.5
7.5
3
—
—
—
—
—
—
—
—
—
5
8.5
7.5
7.5
4
—
—
—
—
—
—
—
—
—
6
9.5
8.5
8.5
5
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBES
tSPMS
tSDS
SetupTime,FS0/SDbeforeCLKA↑
tSENS
tFWS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
5
SetupTime,FWFTbeforeCLKA↑
0
0
0
HoldTime,A0-A35afterCLKA↑ andB0-B35afterCLKB↑
0.5
0.5
1
1
tENH
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;CSB,
W/RB, ENB, andMBBafterCLKB↑
1
1
tRSTH
tFSH
Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑(1)
Hold Time, FS0 and FS1 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
4
2
—
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
—
4
3
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBEH
2
2
3
tSPMH
tSDH
Hold Time, SPM afterRS1 HIGH
2
2
3
HoldTime, FS0/SDafterCLKA↑
0.5
0.5
2
1
1
tSENH
tSPH
HoldTime,FS1/SEN HIGHafterCLKA↑
Hold Time, FS1/SEN HIGH after RS1 HIGH
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
1
1
2
3
(2)
tSKEW1
7.5
12
7.5
12
9
tSKEW2(2,3) Skew Time between CLKA↑ and CLKB↑ for AE and AF
16
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
8
IDT
IDT72V3623/33/43
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
ο
ο
Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0 C to +70 C; JEDEC JESD8-A compliant
72V3623L12
72V3633L12
72V3643L12
72V3623L15
72V3633L15
72V3643L15
72V3623L20
72V3633L20
72V3643L20
Symbol
tA
Parameter
Min.
2
Max.
Min.
2
Max.
Min.
2
Max.
12
Unit
ns
Access Time,CLKA↑ toA0-A35andCLKB↑ toB0-B35
PropagationDelayTime, CLKA↑ toFF/IR
PropagationDelayTime,CLKB↑ toEF/OR
PropagationDelayTime,CLKB↑ toAE
PropagationDelayTime,CLKA↑ toAF
8
8
8
8
8
8
10
8
tWFF
tREF
tPAE
tPAF
tPMF
2
2
2
10
ns
1
1
8
2
10
ns
1
1
8
1
10
ns
1
1
8
1
10
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2
and CLKB↑ to MBF2 LOW or MBF1 HIGH
0
0
8
0
10
ns
tPMR
tMDV
tRSF
tEN
PropagationDelayTime, CLKA↑ toB0-B35(1) andCLKB↑ to
2
2
1
2
1
8
8
2
2
1
2
1
10
10
15
10
8
2
2
1
2
1
12
12
20
12
10
ns
ns
ns
ns
ns
A0-A35(2)
Propagation Delay Time, MBA to A0-A35 valid and MBB to
B0-B35Valid
Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF
HIGH, MBF1 HIGH and MBF2 HIGH
10
6
Enable Time, CSA andW/RA LOWtoA0-A35Active andCSB
LOWand W/RBHIGHtoB0-B35Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high
impedance and CSB HIGH or W/RB LOW to B0-B35 at high
impedance
6
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT72V3623/33/43
IDT
significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort
Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe
readfromPortBlast.
ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBfirst;the
mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom
PortBlast. RefertoFigure2foranillustrationoftheBEfunction.SeeFigure
3(Reset)foranEndianselecttimingdiagram.
SIGNALDESCRIPTION
RESET(RS1, RS2)
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
pulsetoRS1andRS2simultaneously. Afterwards,theFIFOmemoryofthe
IDT72V3623/72V3633/72V3643 undergoes a complete reset by taking its
Reset(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour
PortBclock(CLKB)LOW-to-HIGHtransitions.TheResetinputs canswitch
asynchronously tothe clocks. AResetinitializes the internalreadandwrite
pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output
Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Fullflag(AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe
parallelmailboxregisterHIGH,andatthesametimetheRS2andMBF2operate
likewise. AfteraReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwo
writeclockcyclestobeginnormaloperation.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferredthroughPortB.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe
values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method(fordetails seeTable1,FlagProgramming,andAlmost-Emptyand
Almost-Fullflagoffsetprogrammingsection). TherelevantResettimingdiagram
can be found in Figure 3.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKA andCLKB willselect
IDTStandardmode. ThismodeusestheEmptyFlagfunction(EF)toindicate
whetherornotthereareanywords presentintheFIFOmemory. Ituses the
FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
includingthefirst,mustberequestedusingaformalreadoperation.
OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring
thenextLOW-to-HIGHtransitionofCLKA andCLKBwillselectFWFTmode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReadyfunction
(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
PARTIALRESET(PRS)
TheFIFOmemoryoftheIDT72V3623/72V3633/72V3643undergoesa
limitedresetbytakingitsPartialReset(PRS)inputLOWforatleastfourPortA
clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The
PartialResetinputcanswitchasynchronouslytotheclocks. APartialReset
initializestheinternalreadandwritepointersandforcestheFull/InputReady
flag(FF/IR)LOW, the Empty/OutputReadyflag(EF/OR)LOW, the Almost-
Emptyflag(AE)LOW,andtheAlmost-Fullflag(AF)HIGH. APartialResetalso
forcestheMailboxflag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.
AfteraPartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWrite
Clock cycles to begin normal operation. See Figure 4, Partial Reset (IDT
StandardandFWFTModes)forthe relevanttimingdiagram.
Following Reset,thelevelappliedtotheBE/FWFTinputtochoosethe
desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto
Figure 3(Reset)fora FirstWordFallThroughselecttimingdiagram.
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
TworegistersintheIDT72V3623/72V3633/72V3643areusedtoholdthe
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag
(AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled
Y.Theoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofthe
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).SPM,FS0/
SD, and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogramminga FIFOfollowinga Resetwouldbe inconvenient.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,theSerialProgramMode
(SPM)andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-
to-HIGHtransitionoftheResetinput(RS1). Forexample,toloadthepreset
valueof64intoXandY,SPM,FS0andFS1mustbeHIGHwhenRS1returns
HIGH. For the relevant preset value loading timing diagram, see Figure 3.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionis
active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread
fromPortB. Thisselectiondeterminestheorderbywhichbytes(orwords)of
dataaretransferredthroughthisport. Forthefollowingillustrations,assumethat
a byte (orword)bus size has beenselectedforPortB. (Note thatwhenPort
Bisconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication
— PARALLEL LOAD FROM PORT A
Toprogramthe XandYregisters fromPortA, performa Resetonwith
SPMHIGHandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1.
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredatain
RAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On
1
and the BE input is a “don’t care” .)
AHIGHonthe BE/FWFT inputwhenthe Reset(RS1)inputgoes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT
IDT72V3623/33/43
TABLE 1: FLAG PROGRAMMING
SPM
H
H
H
H
L
FS1/SEN
FS0/SD
RS1
↑
X AND Y REGlSTERS(1)
H
H
L
L
H
H
L
L
H
L
H
L
L
H
H
L
64
↑
16
↑
8
ParallelprogrammingviaPortA
SerialProgrammingviaSD
reserved
↑
↑
L
↑
L
↑
reserved
L
↑
reserved
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure linesareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBisLOW.
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag The B0-B35 lines are active outputs whenCSB is LOW and W/RB is HIGH.
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
timingdiagram.ThePortAdatainputsusedbytheoffsetregistersare(A7-A0), transitionofCLKBwhenCSB is LOW,W/RBis HIGH, ENBis HIGH, MBBis
(A8-A0), or (A9-A0) for the IDT72V3623, IDT72V3633 or IDT72V3643, LOW,andEF/ORisHIGH(seeTable3). FIFOreadsonPortBareindependent
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof of any concurrent writes on Port A.
thebinarynumberineachcase. Validprogrammingvaluesfortheregisters
The setup and hold time constraints to the port clocks for the port Chip
range from 1 to 252 for the IDT72V3623; 1 to 508 for the IDT72V3633; and SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
1to1,020fortheIDT72V3643. Afteralltheoffsetregistersareprogrammed andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable
fromPortA,theFIFObegins normaloperation.
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay
changestatesduringthesetupandholdtimewindowofthecycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwithSPMLOW, LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterby
FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1. theLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
After this reset is complete, the X and Y register values are loaded bit-wise HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
throughtheFS0/SDinputoneachLOW-to-HIGHtransitionofCLKAthatthe arrayis clockedtothe outputregisteronlywhena readis selectedusingthe
FS1/SENinputisLOW.Thereare16-,18-or20-bitwritesneededtocomplete port’sChipSelect,Write/Readselect,Enable,andMailboxselect.
the programming for the IDT72V3623, IDT72V3633 or the IDT72V3643,
WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether
respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis
canbeprogrammedfrom1to252(IDT72V3623),1to508(IDT72V3633)or clockedtotheoutputregisteronlywhenareadisselectedusingtheport’sChip
1 to 1,020 (IDT72V3643).
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/ diagram can be found in Figure 7. Relevant Port B Read timing diagrams
InputReady(FF/IR)flagremainsLOWuntilallregisterbitsarewritten. FF/IR togetherwithBus-MatchingandEndianselectcanbefoundinFigure8,9and
issetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded 10.
toallownormalFIFOoperation.
SeeFigure6,SerialProgrammingoftheAlmost-FullFlagandAlmost- SYNCHRONIZED FIFO FLAGS
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop
stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone
FIFO WRITE/READ OPERATION
The state ofthe PortAdata (A0-A35)lines is controlledbyPortAChip another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
Select (CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesarein synchronizedtoCLKB. Table4 shows therelationshipofeachportflagtothe
the High-impedance state when eitherCSA or W/RA is HIGH. The A0-A35 numberofwords storedinmemory.
lines are active outputs whenbothCSA andW/RA are LOW.
DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH EMPTY/OUTPUTREADYFLAGS(EF/OR)
transitionofCLKAwhenCSAis LOW,W/RAis HIGH,ENAis HIGH,MBAis
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
of any concurrent reads on Port B. intheFIFOoutputregister. WhentheOutputReadyflagisLOW,theprevious
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read ignored.
select(W/RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When
PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB). TheB0-B35 theEmptyFlagisHIGH,dataisavailableintheFIFO’smemoryforreadingto
11
IDT72V3623/33/43
IDT
TABLE 2: PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
None
X
X
X
X
X
↑
Input
Input
H
L
X
None
L
H
H
L
Input
FIFOWrite
Mail1Write
None
L
H
H
H
↑
Input
L
L
L
L
X
↑
Output
Output
Output
Output
L
L
H
L
None
L
L
L
H
X
↑
None
L
L
H
H
Mail2 Read (Set MBF2 HIGH)
TABLE 3: PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Functions
X
X
X
X
X
↑
Input
Input
None
L
L
X
None
L
L
H
L
Input
None
Mail2Write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
Output
Output
Output
None
L
H
H
L
FIFO read
L
H
L
H
X
↑
None
L
H
H
H
Mail1 Read (Set MBF1 HIGH)
TABLE 4: FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT72V3623(3)
IDT72V3633(3)
IDT72V3643(3)
EF/OR
AE
AF
H
H
H
L
FF/IR
H
0
1 to X
0
1 to X
0
1 to X
L
H
H
H
H
L
L
H
(X+1)to[256-(Y+1)]
(256-Y)to255
256
(X+1)to[512-(Y+1)]
(512-Y)to511
512
(X+1)to[1,024-(Y+1)]
(1,024-Y)to1,023
1,024
H
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
theoutputregister. WhentheEmptyFlagisLOW,thepreviousdatawordis oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
presentinthe FIFOoutputregisterandattemptedFIFOreads are ignored. thewordwaswritten. TheOutputReadyflagoftheFIFOremainsLOWuntil
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-
thatreadsdatafromitsarray(CLKB). ForboththeFWFTandIDTStandard neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
modes,theFIFOreadpointerisincrementedeachtimeanewwordisclocked outputregister.
toits outputregister. The state machine thatcontrols anOutputReadyflag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
FIFOmemorystatusisempty,empty+1,orempty+2. cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady twocycles oftheportClockthatreads datafromtheFIFOhavenotelapsed
flagsynchronizingclock. Therefore,anOutputReadyflagis LOWifaword sincethetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOW
inmemoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
12
IDT
IDT72V3623/33/43
duringaFlFOresetor,programmedfromPortA,orprogrammedserially(see
Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost-
FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthanorequal
to (256-Y), (512-Y), or (1,024-Y) for the IDT72V3623, IDT72V3633, or
IDT72V3643respectively. AnAlmost-FullflagisHIGHwhenthenumberof
wordsinitsFIFOislessthanorequalto[256-(Y+1)],[512-(Y+1)],or[1,024-
(Y+1)]fortheIDT72V3623,IDT72V3633,orIDT72V3643respectively. Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are requiredaftera FIFOreadforits Almost-Fullflagtoreflectthe newlevel
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
notelapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionof
anAlmost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycle
ifitoccursattimetSKEW2orgreaterafterthereadthatreducesthenumberof
words in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent
synchronizingclockcyclemaybethefirstsynchronizationcycle(seeFigure
16).
forcing the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (FF/IR)
Thisisadualpurposeflag. InFWFTmode,theInputReady(IR)function
isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For
bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation
is free in the FIFO to receive new data. No memory locations are free when
theFull/InputReadyflagisLOWandattemptedwritestotheFIFOareignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat
writesdatatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,each
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFO memorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
MAILBOX REGISTERS
Two36-bitbypassregistersareontheIDT72V3623/72V3633/72V3643
topasscommandandcontrolinformationbetweenPortAandPortBwithout
puttingitinqueue. TheMailboxselect(MBA,MBB)inputs choosebetween
amailregisterandaFIFOforaportdatatransferoperation. Theusablewidth
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeis 36bits,theusablewidthoftheMail1Registeremploys
datalinesA0-A35. IftheselectedPortBbussizeis18bits,thentheusablewidth
oftheMail1RegisteremploysdatalinesA0-A17. (Inthiscase,A18-A35are
don’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidth
oftheMail1RegisteremploysdatalinesA0-A8. (Inthiscase,A9-A35aredon’t
careinputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
RegisterwhenaPortBwriteis selectedbyCSB,W/RB,andENBwithMBB
HIGH. IftheselectedPortBbussizeis36bits,theusablewidthoftheMail2
employsdatalinesB0-B35. IftheselectedPortBbussizeis18bits,thenthe
usablewidthoftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,
B18-B35aredon’tcareinputs.) IftheselectedPortBbus sizeis 9bits,then
theusablewidthoftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,
B9-B35are don’tcare inputs.)
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfrom
theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom
themailregisterwhentheportMailboxselectinputisHIGH.
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadis selectedbyCSB,W/RB,andENBwithMBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17. (Inthis
case,B18-B35areindeterminate.) Fora9-bitbussize,9bitsofmailboxdata
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
onCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENAwithMBA
HIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime
tSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcyclecanbe
the firstsynchronizationcycle (see Figures 13and14).
ALMOST-EMPTYFLAG(AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray(CLKB). ThestatemachinethatcontrolsanAlmost-Empty
flagmonitorsawritepointerandreadpointercomparatorthatindicateswhen
theFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.
TheAlmost-EmptystateisdefinedbythecontentsofregisterX. Theseregisters
areloadedwithpresetvalues duringaFIFOreset,programmedfromPortA,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programmingsection). AnAlmost-EmptyflagisLOWwhenitsFIFOcontainsX
orlesswordsandisHIGHwhenitsFIFOcontains(X+1)ormorewords. Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 15).
ALMOST-FULL FLAG (AF)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstateisdefined
by the contents of register Y. These registers are loaded with preset values
13
IDT72V3623/33/43
IDT
Fora36-bitbussize,36bitsofmailboxdataareplacedonA0-A35. For
Only 36-bit long word data is written to or read from the FIFO memory on
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17. (Inthiscase, the IDT72V3623/72V3633/72V3643. Bus-matching operations are done after
A18-A35are indeterminate.) Fora 9-bitbus size, 9bits ofmailboxdata are data is read from the FIFO RAM. These bus-matching operations are not
placedon A0-A8. (In this case, A9-A35are indeterminate.)
available when transferring data via mailbox registers. Furthermore, both the
The data in a mail register remains intact after it is read and changes word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused
onlywhennewdatais writtentotheregister. TheEndianselectfeaturehas formailregisteroperations. Inthis case, onlythose byte lanes belongingtothe
no effect on mailbox data. For mail register and mail register flag timing selected word- or byte-size bus can carry mailbox data. The remaining data
diagrams, see Figure 17 and 18.
outputswillbeindeterminate. Theremainingdatainputswillbedon’tcareinputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, selected, then mailbox data can be transmitted only between A0-A8 and B0-
or 9-bit byte format for data read from the FIFO. The levels applied to the B8. (See Figures 17 and 18).
PortBBusSizeselect(SIZE)andtheBus-Matchselect(BM)determinethe
Port B bus size. These levels should be static throughout FIFO operation. BUS-MATCHING FIFO READS
BothbussizeselectionsareimplementedatthecompletionofReset,bythetime
the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Data is read from the FIFO RAM in 36-bit long word increments. If a long
wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
TwodifferentmethodsforsequencingdatatransferareavailableforPort output register. If byte or word size is implemented on Port B, only the first one
Bwhenthebus sizeselectionis eitherbyte-orword-size. Theyarereferred or two bytes appear on the selected portion of the FIFO output register, with the
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
bytefirst). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW- reads output the rest of the long word to the FIFO output register in the order
to-HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduring shown by Figure 2.
FIFOoperation. BEis adon’tcareinputwhenthebus sizeselectedforPort
WhenreadingdatafromFIFOinbyteorwordformat,theunusedB0-B35
Bislongword. TheendianmethodisimplementedatthecompletionofReset, outputsareindeterminate.
by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
14
IDT
IDT72V3623/33/43
BYTE ORDER ON PORT A:
A35
B35
A27
B27
A26
B26
A18
B18
A17
A9
B9
A8
B8
A0
B0
Write to FIFO
A
A
B
B
C
D
D
B17
BYTE ORDER ON PORT B:
BE BM SIZE
C
Read from FIFO
X
L
X
(a) LONG WORD SIZE
B35
B35
B27
B27
B26
B26
B18
B18
B17
B9
B9
B8
B8
B0
B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
A
B
D
H
H
L
B17
C
(b) WORD SIZE
BIG-ENDIAN
B35
B35
B27
B27
B26
B18
B17
B9
B8
B0
B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
C
D
L
H
L
B26
B18
B17
B9
B8
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35
B35
B35
B35
B27
B27
B27
B27
B26
B26
B26
B26
B18
B17
B17
B17
B17
B9
B9
B9
B9
B8
B8
B8
B8
B0
B0
B0
B0
BE BM SIZE
A
B
C
D
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B18
B18
B18
3rd: Read from FIFO
4th: Read from FIFO
(d) BYTE SIZE
BIG-ENDIAN
B35
B35
B35
B35
B27 B26
B27 B26
B27 B26
B27 B26
B18
B18
B18
B18
B17
B17
B17
B17
B9
B8
B8
B8
B8
B0
B0
B0
B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B9
B9
B9
C
B
2nd: Read from FIFO
3rd: Read from FIFO
A
4th: Read from FIFO
4662 drw 04
(e) BYTE SIZE
LITTLE-ENDIAN
Figure 2. Bus sizing
15
IDT72V3623/33/43
IDT
1
2
CLKA
CLKB
t
RSTS
tRSTH
RS1, RS2
BE/FWFT
t
BEH
t
BES
tFWS
BE
0,1
FWFT
t
t
SPMS
FSS
tSPMH
SPM
t
FSH
FS1,FS0
t
WFF
t
WFF
FF/IR
EF/OR
AE
(2)
tREF
t
t
RSF
RSF
AF
t
RSF
MBF1,
MBF2
4662 drw 05
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS
t
WFF
t
WFF
FF/IR
(2)
REF
t
EF/OR
AE
t
RSF
t
RSF
AF
t
RSF
MBF1,
4662 drw 06
MBF2
NOTES:
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
IDT
IDT72V3623/33/43
CLKA
4
2
1
RS1
t
FSS
t
FSH
SPM
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FF/IR
tENS2
tENH
ENA
A0-A35
NOTE:
tDH
t
DS
4662 drw 07
AE Offset
First Word to FIFO1
AF Offset
(X)
(Y)
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
RS1
4
t
t
FSS
FSS
t
FSH
SPM
t
WFF
FF/IR
t
SENS
t
SENH
SDH
t
SENS
t
SENH
SDH
tSPH
FS1/SEN
tSDS
t
t
tSDS
FS0/SD(2)
4662 drw 08
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
17
IDT72V3623/33/43
IDT
tCLK
tCLKL
tCLKH
CLKA
FF/IRA HIGH
tENS1
tENH
CSA
tENS2
t
ENH
ENH
ENH
W/RA
t
ENS2
ENS2
t
MBA
ENA
t
tENS2
tENS2
tENH
t
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0-A35
4662 drw 09
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR HIGH
CSB
W/RB
MBB
ENB
t
ENS2
tENS2
tENH
t
ENH
tENH
t
ENS2
No Operation
W2(1)
tDIS
t
MDV
tA
t
A
tEN
W1 (1)
B0-B35
Previous Data
(Standard Mode)
t
MDV
t
DIS
OR
tA
tA
W1(1)
tEN
B0-B35
W2 (1)
W3 (1)
(FWFT Mode)
4662 drw 10
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
IDT
IDT72V3623/33/43
CLKB
FF/OR HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
Read 2
t
DIS
t
MDV
t
A
t
A
B0-B17
t
EN
(Standard Mode)
Previous Data
Read 1
Read 2
t
DIS
OR
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
4662 drw 11
NOTE:
1. Unused word B18-B35 are indeterminate.
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
DATA WRITTEN TO FIFO 1
READ
NO.
DATA READ FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
IDT72V3623/33/43
IDT
CLKB
EF/OR HIGH
CSB
W/RB
MBB
t
ENS2
t
ENH
A
ENB
No Operation
Read 4
t
MDV
tDIS
t
A
tA
t
t
A
t
EN
B0-B8
(Standard Mode)
OR
Read 1
Previous Data
Read 2
Read 3
tDIS
tA
t
MDV
tA
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
Read 5
4662 drw 12
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
READ
DATA READ FROM FIFO
B8-B0
NO.
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
H
H
L
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
IDT
IDT72V3623/33/43
tCLK
tCLKL
tCLKH
CLKA
LOW
HIGH
CSA
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
t
IR HIGH
A0-A35
tDS
tDH
W1
t
tSKEW1
CLKtCLKL
(1)
tCLKH
CLKB
1
2
3
t
REF
tREF
FIFO Empty
LOW
OR
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
B0-B35
NOTES:
tA
Old Data in FIFO Output Register
W1
4662 drw 13
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
IDT72V3623/33/43
IDT
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
W/RA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
FF HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
t
REF
t
REF
EF
FIFO Empty
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0-B35
NOTES:
W1
4662 drw 14
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
IDT
IDT72V3623/33/43
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENS2
tENH
ENB
OR HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
CLKA
tCLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
t
WFF
t
WFF
IR
FIFO Full
LOW
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
To FIFO
4662 drw 15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
IDT72V3623/33/43
IDT
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
SKEW1
Next Word From FIFO
B0-B35
(1)
t
tCLK
tCLKH
tCLKL
CLKA
1
2
WFF
ENH
WFF
t
t
FIFO Full
LOW
FF
CSA
HIGH
W/RA
tENS2
t
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
4662 drw 16
To FIFO
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Words in FIFO
(X+1) Words in FIFO
ENS2
t
tENH
ENB
4662 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
IDT
IDT72V3623/33/43
CLKA
1
2
(1)
tENS2
tENH
tSKEW2
ENA
AF
t
PAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
CLKB
tENS2
tENH
ENB
4662 drw 18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3623, 512 for the IDT72V3633, 1,024 for the IDT72V3643.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENS1
tENH
CSA
tENH
tENH
tENS2
tENS2
W/RA
MBA
tENS2
tENH
tDH
ENA
tDS
W1
A0-A35
CLKB
tPMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
tMDV
tEN
tDIS
tPMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
4662 drw 19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
IDT72V3623/33/43
IDT
CLKB
tENH
tENS1
CSB
tENS2
tENH
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
tDH
tDS
W1
B0-B35
CLKA
MBF2
t
PMF
t
PMF
CSA
W/RA
MBA
ENA
tENH
tENS2
t
EN
tPMR
t
DIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
4662 drw 20
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid
data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
READ CLOCK (CLKB)
CLKB
CLKA
CHIP SELECT (CSA)
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
CHIP SELECT (CSB)
EMPTY FLAG/
OUTPUT READY (EF/OR)
EF/OR
ENA
V
CC
FF/IR
ENB
READ ENABLE (ENB)
V
CC
CSB
CSA
READ SELECT (W/RB)
IDT
IDT
72V3623
72V3633
72V3643
72V3623
72V3633
72V3643
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A
0
-A35
n
B
0
-B35
B0-B35
n
FULL FLAG/
INPUT READY (FF/IR)
DATA OUT (Qn)
Qn
Dn
V
CC
V
CC
W/RA
MBA
W/RB
MBB
4662 drw 21
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO
is the sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 19. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
26
PARAMETER MEASUREMENT INFORMATION
3.3 V
330
Ω
From Output
Under Test
30 pF (1)
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
GND
3 V
3 V
Timing
Input
1.5 V
High-Level
Input
GND
1.5 V
1.5 V
1.5 V
1.5 V
GND
3 V
tS
th
tW
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
GND
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈ 3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
OL
t
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4662 drw 22
NOTE:
1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms.
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
PF
Commercial (0οC to +70οC)
Thin Quad Flat Pack (TQFP, PK128-1)
12
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Speed in Nanoseconds
L
Low Power
72V3623
72V3633
72V3643
256 x 36 3.3V SyncFIFO with Bus-Matching
512 x 36 3.3V SyncFIFO with Bus-Matching
1,024 x 36
3.3V SyncFIFO with Bus-Matching
NOTE:
4662 drw 23
1. Industrial temperature range is available by special order.
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
408-330-1753
FIFOhelp@idt.com
www.idt.com
PFPkg:www.idt.com/docs/PSC4045.pdf
The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
27
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