IDT72V3651L15PQF9 [IDT]
FIFO, 2KX36, 10ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132;
| 型号： | IDT72V3651L15PQF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 2KX36, 10ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132 先进先出芯片 |
| 文件： | 总21页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM
512 x 36
1,024 x 36
IDT72V3631
IDT72V3641
IDT72V3651
2,048 x 36
• Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723631/723641/723651
FEATURES
• Storage capacity:
IDT72V3631 - 512 x 36
IDT72V3641 - 1,024 x 36
IDT72V3651 - 2,048 x 36
• Easily expandable in width and depth
•
Industrial temperature range (–40°C to +85°C) is available
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
DESCRIPTION
TheIDT72V3631/72V3641/72V3651arepinandfunctionallycompatible
versonsoftheIDT723631/723641/723651,designedtorunoffa3.3Vsupply
forexceptionallylow-powerconsumption. Thesedevicesaremonolithichigh-
speed,low-power,CMOSclockedFIFOmemory. Itsupportsclockfrequencies
upto67MHzandhasreadaccesstimesasfastas10ns. The512/1,024/2,048
x36dual-portSRAMFIFObuffersdatafromportAtoPortB. TheFIFOmemory
has retransmitcapability, whichallows previouslyreaddata tobe accessed
again. The FIFOoperates inFirstWordFallThroughmode andhas flags to
indicateemptyandfullconditionsandconditionsandtwoprogrammableflags
(Almost-FullandAlmost-Empty)toindicatewhenaselectednumberofwords
isstoredinmemory. Communicationbetweeneachportmaytakeplacewith
• Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
Reset
Logic
RST
RTM
36
Read
Pointer
Write
Pointer
RFM
A
0
- A35
B0 - B35
Status Flag
OR
AE
IR
AF
Logic
Flag Offset
Registers
FS
0
/SD
FS /SEN
1
10
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
Mail 2
Register
4658 drw 01
MBF2
IDTandtheIDTlogoaretrademarkofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4658/2
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
TheInputReady(IR)flagandAlmost-Full(AF)flagoftheFIFOaretwo-stage
synchronizedtoCLKA. TheOutputReady(OR)flagandAlmost-Empty(AE)
flag of the FIFO are two-stage synchronized to CLKB. Offset values for the
Almost-FullandAlmost-EmptyflagsoftheFIFOcanbeprogrammedfromport
A or through a serial input.
TheIDT72V3631/72V3641/72V3651arecharacterizedforoperationfrom
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
specialorder. ThesedevicesarefabricatedusingIDT'shighspeed,submicron
CMOStechnology.
DESCRIPTION(CONTINUED)
two36-bitmailboxregisters. Eachmailboxregisterhasaflagtosignalwhen
newmailhasbeenstored. Twoormoredevicesmaybeusedinparalleltocreate
wider data paths. Expansion is also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronousinterface. AlldatatransfersthroughaportaregatedtotheLOW-
to-HIGHtransitionofacontinuous(free-running)portclockbyenablesignals.
Thecontinuousclocksforeachportareindependentofoneanotherandcan
be asynchronous or coincident. The enables for each port are arranged to
provide a simple interface between microprocessors and/or buses with
synchronouscontrol.
PIN CONFIGURATION
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
B
B
B
B
35
34
33
32
A
A
A
A
V
A
A
35
34
33
32
CC
31
30
*
GND
B
B
B
B
B
B
31
30
29
28
27
26
GND
A
A
A
A
A
A
A
29
28
27
26
25
24
23
V
CC
B
25
B24
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
A
V
A
A
A
A
22
CC
21
20
19
18
98
97
96
95
GND
94
B
17
16
93
B
GND
92
V
CC
A
A
A
A
A
V
A
17
16
15
14
13
CC
12
91
B
15
14
13
12
90
B
B
B
89
88
87
GND
NC
86
85
NC
NC
84
4658 drw 02
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
PQFP (PQ132-1, order code: PQF)
TOP VIEW
2
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION(CONTINUED)
A
A
A
A
35
34
33
32
1
B
B
B
B
35
34
33
32
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
3
4
V
CC
5
GND
A
31
6
B
B
B
B
B
B
V
B
B
31
30
29
28
27
26
CC
25
24
A30
7
GND
8
A
A
A
A
A
A
A
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
B
B
B
B
B
23
22
21
20
19
18
A
22
CC
V
A
21
20
19
18
A
A
A
GND
GND
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
A
A
A
A
A
17
16
15
14
13
V
CC
A12
GND
4658 drw 03
NOTE:
1. NC – No internal connection.
TQFP (PN120-1, order code: PF)
TOP VIEW
3
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
A0-A35 Port-AData
I/O 36-bitbidirectionaldataportforsideA.
AE
AF
Almost-Empty
Flag
Almost-Full
Flag
O
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to
thevalueintheAlmost-Emptyregister(X).
ProgrammableflagsynchronizedtoCLKA. Itis LOWwhenthenumberofemptylocations intheFIFOis less thanor
equaltothevalueintheAlmost-FullOffsetregister(Y).
O
B0-B35 Port-BData
I/O 36-bitbidirectionaldataportforsideB.
CLKA
CLKB
CSA
Port-A Clock
I
I
I
I
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughport-Aandmaybeasynchronous or
coincident to CLKB. IR and AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKBis a continuous clockthatsynchronizes alldata transfers throughport-B andmaybe asynchronous or
coincident to CLKA. OR and AE are synchronous to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35
outputs are in the high-impedance state when CSB is HIGH.
Port-BClock
Port-AChip
Select
Port-BChip
Select
CSB
ENA
ENB
FS1/
Port-AEnable
Port-BEnable
Flag-Offset
Select1/
I
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset,
FS1/SENandFS0/SDselectstheflagoffsetprogrammingmethod.ThreeOffsetregisterprogrammingmethodsare
available:automaticallyloadone oftwopresetvalues, parallelloadfromport A, andserialload.
SEN,
SerialEnable
FS0/SD FlagOffset0/
SerialData
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SENisusedasanenablesynchronousto
the LOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW, a risingedge onCLKAloadthe bitpresentonFS0/
SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe Offsetregisters is 18/20/22forthe
IDT72V3631/72V3641/72V3651respectively. ThefirstbitwritestorestheY-registerMSBandthelastbitwritestores
theX-registerLSB.
IR
Input Ready
Flag
O
IRis synchronizedtotheLOW-to-HIGHtransitionofCLKA. WhenIRis LOW,theFIFOis fullandwrites toits
arrayare disabled. Whenthe FIFOis inretransmitmode, IR indicates whenthe memoryhas beenfilledtothe point
oftheretransmitdataandpreventsfurtherwrites.IRissetLOWduringresetandissetHIGHafterreset.
A HIGH level chooses a mailbox register for a port-A read or write operation.
MBA
MBB
Port-AMailbox
Select
Port-BMailbox
Select
I
I
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active,
a HIGHlevelonMBBselects datafromthemail1registerforoutputandaLOWlevelselects FIFOdataforoutput.
MBF1
MBF2
OR
Mail1Register
Flag
O
O
O
MBF1issetLOWbytheLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register. MBF1issetHIGH
by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH by a
reset.
Mail2Register
Flag
MBF2issetLOWbytheLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register. MBF2issetHIGH
by a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a
reset.
ORis synchronizedtothe LOW-to-HIGHtransitionofCLKB. WhenORis LOW, the FIFOis emptyandreads are
disabled. Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the
resetandgoes HIGHonthethirdLOW-to-HIGHtransitionofCLKBafterawordis loadedtoemptymemory.
Whenthe FIFOis inretransmitmode, a HIGHonRFMenables a LOW-to-HIGHtransitionof CLKBtoresetthe read
pointertothebeginningretransmitlocationandoutputthefirstselectedretransmitdata.
OutputReady
Flag
RFM
Read From
Mark
I
I
RST
Reset
Toresetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset
selection.
RTM
Retransmit
Mode
I
WhenRTMis HIGHandvaliddata is presentinthe FIFOoutputregister(ORis HIGH), a LOW-to-HIGHtransition
ofCLKBselects thedataforthebeginningofaretransmitandputs theFIFOinretransmitmode. Theselectedword
remainstheinitialretransmitpointuntilaLOW-to-HIGHtransitionofCLKBoccurswhileRTMisLOW,takingtheFIFO
outofretransmitmode.
W/RA
W/RB
Port-AWrite/
ReadSelect
I
I
A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGHtransitionof
CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
Port-BWrite/
ReadSelect
A LOWselects a write operationanda HIGHselects a readoperationonportBfora LOW-to-HIGHtransitionof
CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
4
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(2)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5(3)
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
VO(2)
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO = < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Control Inputs: maximum VI = 5.0V.
RECOMMENDED OPERATING
CONDITIONS
Symbol
VCC
VIH
Parameter
SupplyVoltage
Min.
3.0
2
Typ.
3.3
—
Max.
3.6
Unit
V
HIGH Level Input Voltage
LOW-LevelInputVoltage
HIGH-LevelOutputCurrent
LOW-LevelOutputCurrent
VCC+0.5
0.8
V
VIL
—
—
—
0
—
V
IOH
—
–4
mA
mA
°C
IOL
—
8
TA
OperatingFree-air
Temperature
—
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3631
IDT72V3641
IDT72V3651
Commercial
tCLK = 15, 20 ns
Symbol
VOH
VOL
Parameter
Output Logic "1" Voltage
Output Logic "0" Voltage
Input Leakage Current (Any Input)
Output Leakage Current
Standby Current
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min.
2.4
—
Typ.(1)
—
—
—
—
—
4
Max.
—
Unit
V
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
0.5
±5
V
ILI
VI = VCC or 0
VO = VCC or 0
VI = VCC –0.2V or 0
f = 1 MHz
—
µA
µA
µA
pF
ILO
ICC2(2)
—
±5
—
400
—
CIN
Input Capacitance
—
COUT
Output Capacitance
VO = 0,
f = 1 MHZ
—
8
—
pF
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
5
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3641 with CLKA and CLKB set
tofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnectedtonormalize
thegraphtoazero-capacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3631/72V3641/72V3651inputsdriven
by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC2 x fO)
N
where:
N = numberofoutputs=36
CL = outputcapacitanceload
fO = switchingfrequencyofanoutput
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.025 mA/MHz
175
f
T
data = 1/2 fS
150
125
100
75
A
= 25°C
VCC = 3.6V
C
L
= 0 pF
VCC = 3.3V
VCC = 3.0V
50
25
0
0
10
20
30
40
50
60
70
4658 drw 04
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
6
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICSOVERRECOMMENDEDRANGESOF
SUPPLYVOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
IDT72V3631L15
IDT72V3641L15
IDT72V3651L15
IDT72V3631L20
IDT72V3641L20
IDT72V3651L20
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKAorCLKBLOW
Min.
–
Max.
Min.
–
Max.
Unit
MHz
ns
66.7
–
50
–
tCLK
tCLKH
tCLKL
tDS
15
6
20
8
–
–
ns
6
–
8
–
ns
SetupTime, A0-A35before CLKA↑andB0-B35
beforeCLKB↑
5
–
6
–
ns
tENS1
tENS2
SetupTime,ENAtoCLKA↑;ENBtoCLKB↑
5
7
–
–
6
–
–
ns
ns
Setup Time, CSA, W/RA, and MBA to CLKA↑;
CSB, W/RB, and MBB to CLKB↑
7.5
tRMS
Setup Time, RTM and RFM to CLKB↑
Setup Time, RST LOW before CLKA↑
6
5
–
–
6.5
6
–
–
ns
ns
tRSTS
(1)
orCLKB↑
tFSS
Setup Time, FS0 and FS1 before RST HIGH
SetupTime,FS0/SDbeforeCLKA↑
9
5
–
–
–
–
10
6
–
–
–
–
ns
ns
ns
ns
tSDS(2)
tSENS(2)
tDH
Setup Time, FS1/SEN before CLKA↑
5
6
HoldTime, A0-A35afterCLKA↑ andB0-B35
afterCLKB↑
0.5
0.5
tENH1
tENH2
HoldTime,ENAafterCLKA↑;ENBafterCLKB↑
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
Hold Time, CSA, W/RA, and MBA after CLKA↑;
CSB, W/RB, and MBB after CLKB↑
tRMH
tRSTH
tFSH
Hold Time, RTM and RFM after CLKB↑
0.5
5
–
–
–
–
–
–
–
0.5
6
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
(1)
Hold Time, RST LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after RST HIGH
Hold Time, FS1/SEN HIGH after RST HIGH
HoldTime,FS0/SDafterCLKA↑
0
0
(2)
tSPH
0
0
(2)
tSDH
0
0
(2)
tSENH
Hold Time, FS1/SEN after CLKA↑
0
0
tSKEW1(3)
SkewTime,betweenCLKA↑andCLKB↑
for OR and IR
9
11
tSKEW2(3,4)
SkewTime,betweenCLKA↑andCLKB↑
for AE and AF
12
–
16
–
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag Offset registers.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
7
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS
IDT72V3631L15
IDT72V3641L15
IDT72V3651L15
IDT72V3631L20
IDT72V3641L20
IDT72V3651L20
Symbol
fS
Parameter
Min.
–
Max.
Min.
–
Max.
50
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
AccessTime,CLKB↑toB0-B35
66.7
10
8
tA
2
2
12
tPIR
PropagationDelayTime,CLKA↑toIR
PropagationDelayTime,CLKB↑toOR
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
1
1
10
ns
tPOR
tPAE
tPAF
tPMF
1
8
1
10
ns
1
8
1
10
ns
1
8
1
10
ns
Propagation Delay Time, CLKA↑ to MBF1
LOW or MBF2 HIGH and CLKB↑ to MBF2
LOW or MBF1 HIGH
0
8
0
10
ns
tPMR
PropagationDelayTime,CLKA↑toB0-B35(1)
2
10
2
12
ns
andCLKB↑ toA0-A35(2)
tMDV
tRSF
PropagationDelayTime, MBBtoB0-B35Valid
2
1
10
15
2
1
12
20
ns
ns
Propagation Delay Time, RST LOW to AE LOW
and AF HIGH
tEN
tDIS
Enable Time, CSA and W/RA LOW to A0-A35
Active and CSB LOW and W/RB HIGH to
B0-B35Active
2
1
10
8
2
1
12
10
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOWtoB0-B35athighimpedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
8
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
is complete,theXandYregistervalues areloadedbitwisethroughtheFS0/
SDinputoneachLOW-to-HIGHtransitionofCLKAthattheFS1/SENinputis
LOW. Thereare18-,20-,or22-bitwritesneededtocompletetheprogramming
fortheIDT72V3631,IDT72V3641,orIDT72V3651,respectively. Thefirst-bit
writestoresthemostsignificantbitoftheYregister,andthelast-bitwritestores
theleastsignificantbitoftheXregister. Eachregistervaluecanbeprogrammed
from 1 to 508 (IDT72V3631), 1 to 1,020 (IDT72V3641), or 1 to 2,044
(IDT72V3651).
WhentheoptiontoprogramtheOffsetregistersseriallyischosen,theInput
Ready(IR)flagremainsLOWuntilallregisterbitsarewritten. TheIRflagisset
HIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloadedtoallow
normalFIFOoperation. Thetimingdiagramforserialloadofoffset registers
can be found in Figure 4.
SIGNALDESCRIPTION
RESET
The IDT72V3631/72V3641/72V3651 is reset by taking the Reset (RST)
inputLOWforatleastfourport-AClock(CLKA)andfourport-B(CLKB)LOW-
to-HIGHtransitions. TheResetinputmayswitchasynchronouslytotheclocks.
AresetinitializesthememoryreadandwritepointersandforcestheInputReady
(IR)flagLOW,theOutputReady(OR)flagLOW,theAlmost-Empty(AE)flag
LOW,andtheAlmost-Full(AF)flagHIGH. Resettingthedevicealsoforcesthe
MailboxFlags(MBF1,MBF2)HIGH. AfteraFIFOisreset,itsInputReadyflag
issetHIGHafteratleasttwoclockcyclestobeginnormaloperation. AFIFO
mustberesetafterpowerupbeforedataiswrittentoitsmemory.Therelevant
FIFO Reset timing diagram can be found in Figure 2.
FIFO WRITE/READ OPERATION
FIRST WORD FALL THROUGH MODE (FWFT)
Thestateoftheport-Adata(A0-A35)outputsiscontrolledbytheport-AChip
Select(CSA)andtheport-AWrite/Readselect(W/RA). TheA0-A35outputs
areinthehigh-impedancestatewheneitherCSA orW/RAisHIGH. TheA0-
A35outputs are active whenbothCSA andW/RAare LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSAandtheport-AMailboxselect(MBA)areLOW,
W/RA,theport-AEnable(ENA),andtheInputReady(IR)flagareHIGH(see
Table 2). Writes to the FIFO are independent of any concurrent FIFO read.
For the Write Cycle Timing diagram, see Figure 5.
Theport-Bcontrolsignalsareidenticaltothoseofport-Awiththeexception
thattheport-BWrite/Readselect(W/RB)istheinverseoftheport-AWrite/Read
select(W/RA). Thestateoftheport-Bdata(B0-B35)outputsiscontrolledby
theport-BChipSelect(CSB)andtheport-BWrite/Readselect(W/RB). The
B0-B35outputsareinthehigh-impedancestatewheneitherCSBisHIGHor
W/RBisLOW. TheB0-B35outputsareactivewhenCSBisLOWandW/RB
isHIGH.
DataisreadfromtheFIFOtoitsoutputregisteronaLOW-to-HIGHtransition
ofCLKBwhenCSBandtheport-BMailboxselect(MBB)areLOW,W/RB,the
port-B Enable (ENB), and the Output Ready (OR) flag are HIGH (see Table
3). ReadsfromtheFIFOareindependentofanyconcurrentFIFOwrites. For
the Read Cycle Timing diagram, see Figure 6.
ThesedevicesoperateintheFirstWordFallThroughmode(FWFT).This
modeusestheOutputReadyfunction(OR)toindicatewhetherornotthereis
validdataatthedataoutputs(B0-B35).ItalsousestheInputReady(IR)function
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting. In
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-
MING
TworegistersinthesedevicesareusedtoholdtheoffsetvaluesfortheAlmost-
EmptyandAlmost-Fullflags. The Almost-Empty(AE)flagOffsetregisteris
labeledX,andtheAlmost-Full(AF)flagOffsetregisterislabeledY. TheOffset
registercanbeloadedwithavalueinthreeways:oneoftwopresetvaluesare
loadedintotheOffsetregisters,parallelloadfromportA,orserialload. TheOffset
registerprogrammingmodeischosenbytheflagselect(FS1,FS0)inputsduring
a LOW-to-HIGH transition on the RST input (See Table 1).
— PRESET VALUES
Ifthepresetvalueof8or64ischosenbytheFS1andFS0inputsatthetime
of a RST LOW-to-HIGH transition according to Table 1, the preset value is
automaticallyloadedintotheXandYregisters. Nootherdeviceinitializationis
necessarytobeginnormaloperation,andtheIRflagissetHIGHaftertwoLOW-
to-HIGHtransitionsonCLKA.ForthePresetvalueloadingtimingdiagram,see
Figure 2.
Thesetup-andhold-timeconstraintstotheportclocksfortheportChipSelects
andWrite/Readselectsareonlyforenablingwriteandreadoperationsandare
notrelatedtohigh-impedancecontrolofthedataoutputs. IfaportEnableisLOW
duringaclockcycle,theportChipSelectandWrite/Readselectmaychange
statesduringthesetup-andholdtimewindowofthecycle.
WhentheORflagisLOW,thenextdatawordissenttotheFIFOoutputregister
automaticallybytheCLKBLOW-to-HIGHtransitionthatsetstheORflagHIGH.
WhenORisHIGH,anavailabledatawordisclockedtotheFIFOoutputregister
onlywhenaFIFOreadisselectedbytheport-BChipSelect(CSB),Write/Read
select (W/RB), Enable (ENB), and Mailbox select (MBB).
— PARALLELLOADFROMPORTA
ToprogramtheXandYregisters fromportA,thedeviceis resetwithFS0
andFS1LOWduringtheLOW-to-HIGHtransitionofRST. Afterthis resetis
complete,theIRflagissetHIGHaftertwoLOW-to-HIGHtransitionsonCLKA.
ThefirsttwowritestotheFIFOdonotstoredatainitsmemorybutloadtheOffset
registersintheorderY,X. EachOffsetregisteroftheIDT72V3631,IDT72V3641,
and IDT72V3651 uses port-A inputs (A8-A0), (A9-A0), and (A10-A0),
respectively. Thehighestnumberinputisusedasthemostsignificantbitofthe
binarynumberineachcase. Eachregistervaluecanbeprogrammedfrom1
to508(IDT72V3631),1to1,020(IDT72V3641),and1to2,044(IDT72V3651).
AfterbothOffsetregistersareprogrammedfromportA,subsequentFIFOwrites
storedataintheRAM. Thetimingdiagramforparallelloadofoffsetregisters
can be found in Figure 3.
TABLE 1 — FLAG PROGRAMMING
FS1
H
FS0
H
RST
↑
X and Y Registers (1)
Serial Load
H
L
↑
64
L
H
↑
8
— SERIAL LOAD
ToprogramtheXandYregisters serially,thedeviceis resetwithFS0/SD
andFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRST. Afterthisreset
L
L
↑
Parallel Load From Port A
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
9
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
SYNCHRONIZED FIFO FLAGS
EachIDT72V3631/72V3641/72V3651FIFOflagissynchronizedtoitsport
INPUT READY FLAG (IR)
TheInputReadyflagofaFIFOissynchronizedtotheportClockthatwrites
Clockthroughatleasttwoflip-flopstages. This is done toimprove the flags’ datatoitsarray(CLKA). WhentheIRflagisHIGH,amemorylocationisfree
reliabilitybyreducingtheprobabilityofmetastableeventsontheiroutputswhen intheFIFOtowritenewdata. NomemorylocationsarefreewhentheIRflag
CLKA and CLKB operate asynchronously to one another. OR and AE are isLOWandattemptedwritestotheFIFOareignored.
synchronizedtoCLKB. IRandAFaresynchronizedtoCLKA. Table4shows
EachtimeawordiswrittentoaFIFO,itswritepointerisincremented. The
statemachinethatcontrolsanIRflagmonitorsawrite-pointerandreadpointer
comparatorthatindicateswhentheFIFO memorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
therelationshipofeachflagtothenumberofwordsstoredinmemory.
OUTPUTREADYFLAG(OR)
TheOutputReadyflagofaFIFOissynchronizedtotheportClockthatreads tobewritteninaminimumofthreecyclesofCLKA. Therefore,anIRflagisLOW
data from its array (CLKB). When the OR flag is HIGH, new data is present iflessthantwocyclesofCLKAhaveelapsedsincethenextmemorywritelocation
intheFIFOoutputregister. WhentheORflagisLOW,thepreviousdataword hasbeenread. ThesecondLOW-to-HIGHtransitiononCLKAaftertheread
ispresentintheFIFOoutputregisterandattemptedFIFOreadsareignored. setstheInputReadyflagHIGH,anddatacanbewritteninthefollowingcycle.
AFIFOreadpointeris incrementedeachtimeanewwordis clockedtoits
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycleof
outputregister. ThestatemachinethatcontrolsanORflagmonitorsawrite- a read if the clock transition occurs at time tSKEW1 or greater after the read.
pointer and read-pointer comparator that indicates when the FIFO memory Otherwise,thesubsequentCLKAcyclemaybethefirstsynchronizationcycle
statusisempty,empty+1,orempty+2. FromthetimeawordiswrittentoaFIFO, (see Figure 8).
itcanbeshiftedtotheFIFOoutputregisterinaminimumofthreecyclesofCLKB.
Therefore, anORflagis LOWifa wordinmemoryis the nextdata tobe sent ALMOST-EMPTY FLAG (AE)
totheFIFOoutputregisterandthreeCLKBcycleshavenotelapsedsincethe
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportClockthatreads
timethewordwaswritten. TheORflagoftheFIFOremainsLOWuntilthethird datafromitsarray(CLKB). ThestatemachinethatcontrolsanAEflagmonitors
LOW-to-HIGHtransitionofCLKBoccurs,simultaneouslyforcingtheORflag a write-pointer and read-pointer comparator that indicates when the FIFO
HIGHandshiftingthewordtotheFIFOoutputregister.
memorystatus is almost-empty, almost-empty+1, oralmost-empty+2. The
ALOW-to-HIGHtransitiononCLKBbeginsthefirstsynchronizationcycleof almost-emptystateisdefinedbythecontentsofregisterX. Thisregisterisloaded
a write if the clock transition occurs at time tSKEW1 or greater after the write. with a preset value during a FIFO reset, programmed from port A, or
Otherwise,thesubsequentCLKBcyclemaybethefirstsynchronizationcycle programmedserially(seeAlmost-EmptyflagandAlmost-Fullflagoffsetpro-
(see Figure 7).
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
X
Data A (A0-A35) I/O
Input
Port Functions
None
H
L
X
X
Input
None
L
H
H
L
↑
Input
FIFO Write
L
H
H
H
↑
Input
Mail1 Write
L
L
L
L
X
Output
None
L
L
H
L
↑
Output
None
None
L
L
L
H
X
Output
L
L
H
H
↑
Output
Mail2 Read (Set MBF2 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
X
Data B (B0-A35) I/O
Input
Port Functions
None
L
L
X
X
Input
None
L
L
H
L
↑
Input
None
Mail2 Write
L
L
H
H
↑
Input
L
H
L
L
X
Output
None
L
H
H
L
↑
Output
FIFO read
L
H
L
H
X
Output
None
L
H
H
H
↑
Output
Mail1 Read (Set MBF1 HIGH)
10
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
grammingsection). TheAEflagisLOWwhentheFIFOcontainsXorlesswords SYNCHRONOUS RETRANSMIT
andisHIGHwhentheFIFOcontains(X+1)ormorewords. Adatawordpresent
inthe FIFOoutputregisterhas beenreadfrommemory.
ThesynchronousretransmitfeatureofthesedevicesallowFIFOdatatobe
readrepeatedlystartingatauser-selectedposition. TheFIFOisfirstputinto
TwoLOW-to-HIGHtransitionsofCLKBarerequiredafteraFIFOwritefor retransmitmodetoselectabeginningwordandpreventongoingFIFOwrite
theAEflagtoreflectthenewleveloffill;therefore,theAEflagofaFIFOcontaining operationsfromdestroyingretransmitdata. Datavectorswithaminimumlength
(X+1)ormorewordsremainsLOWiftwocyclesofCLKBhavenotelapsedsince ofthreewordscanretransmitrepeatedlystartingattheselectedword. TheFIFO
thewritethatfilledthememorytothe(X+1)level. AnAEflagissetHIGHbythe can be taken out of retransmit mode at any time and allow normal device
secondLOW-to-HIGHtransitionofCLKBaftertheFIFOwritethatfillsmemory operation.
to the (X+1) level. A LOW-to-HIGH transition of CLKB begins the first
TheFIFOisputinretransmitmodebyaLOW-to-HIGHtransitiononCLKB
synchronizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfills whenthe retransmitmode (RTM)inputis HIGHandORis HIGH. The rising
theFIFOto(X+1)words.Otherwise,thesubsequentCLKBcyclemaybethe CLKB edge marks the data present in the FIFO output register as the first
firstsynchronizationcycle(seeFigure9).
retransmitdata. TheFIFOremainsinretransmitmodeuntilaLOW-to-HIGH
transitionoccurswhileRTMisLOW.
ALMOST-FULL FLAG (AF)
Whentwoormorereadshavebeendonepasttheinitialmarkedretransmit
TheAlmost-FullflagofaFIFOissynchronizedtotheportClockthatwrites word,aretransmitisinitiatedbyaLOW-to-HIGHtransitiononCLKBwhenthe
datatoitsarray(CLKA). ThestatemachinethatcontrolsanAFflagmonitors read-from-mark (RFM) input is HIGH. This rising CLKB edge shifts the first
a write-pointer and read-pointer comparator that indicates when the FIFO retransmitwordtotheFIFOoutputregisterandsubsequentreadscanbegin
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate immediately. Retransmit loops can be done endlessly while the FIFO is in
isdefinedbythecontentsofregisterY. Thisregisterisloadedwithapresetvalue retransmitmode. RFMmustbeLOWduringtheCLKBrisingedgethattakes
during a FIFO reset, programmed from port A, or programmed serially (see the FIFOoutofretransmitmode (see Figure 11).
Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). TheAFflag
WhentheFIFOisputintoretransmitmode,itoperateswithtworeadpointers.
isLOWwhenthenumberofwordsintheFIFOisgreaterthanorequalto(512-Y), Thecurrentreadpointeroperates normally,incrementingeachtimewhena
(1,024-Y),OR(2,048-Y)fortheIDT72V3631,IDT72V3641,orIDT72V3651, newwordisshiftedtotheFIFOoutputregister. Thisreadpointerpositionis used
respectively. The AF flag is HIGH when the number of words in the FIFO is bytheORandAEflags. Theshadowreadpointerstoresthememorylocation
less than or equal to [512-(Y+1)], [1,024-(Y+1)], or [2,048-(Y+1)] for the atthetimethedeviceisputintoretransmitmodeanddoesnotchangeuntilthe
IDT72V3631, IDT72V3641, or IDT72V3651, respectively. A data word deviceistakenoutofretransmitmode. Theshadowreadpointerpositionisused
presentinthe FIFOoutputregisterhas beenreadfrommemory.
bytheIRandAFflags. DatawritescanproceedwhiletheFIFOisinretransmit
TwoLOW-to-HIGHtransitions ofCLKAarerequiredafteraFIFOreadfor mode, but AF is set LOW by the write that stores (512-Y), (1,024 - Y), or
itsAFflagtoreflectthenewleveloffill. Therefore,theAFflagofaFIFOcontaining (2,048-Y)wordsafterthefirstretransmitwordfortheIDT72V3631,IDT72V3641,
[512/1,024/2,048-(Y+1)]orlesswordsremainsLOWiftwocyclesofCLKAhave orIDT72V3651, respectively. The IRflagis setLOWbythe 512th, 1,024th,
notelapsedsincethereadthatreducedthenumberofwordsinmemoryto[512/ or2,048thwriteafterthefirstretransmitwordfortheIDT72V3631,IDT72V3641,
1,024/2,048-(Y+1)]. An AF flag is set HIGH by the second LOW-to-HIGH or IDT72V3651, respectively.
transition of CLKA after the FIFO read that reduces the number of words in
WhentheFIFOisinretransmitmodeandRFMisHIGH,arisingCLKBedge
memory to [512/1,024/2,048-(Y+1)]. A LOW-to-HIGH transition of CLKA loadsthecurrentreadpointerwiththeshadowread-pointervalueandtheOR
beginsthefirstsynchronizationcycleifitoccursattimetSKEW2orgreaterafter flagreflectsthenewleveloffillimmediately. IftheretransmitchangestheFIFO
thereadthatreducesthenumberofwordsinmemoryto[512/1,024/2,048-(Y+1)]. status out of the almost-empty range, up to two CLKB rising edges after the
Otherwise,thesubsequentCLKAcyclemaybethefirstsynchronizationcycle retransmitcycleareneededtoswitchAEhigh(seeFigure12).TherisingCLKB
(see Figure 10).
TABLE 4 — FIFO FLAG OPERATION
(1,2)
Number of Words in the FIFO
Synchronized
to CLKB
Synchronized
to CLKA
IDT72V3631(3)
IDT72V3641(3)
0
IDT72V3651(3)
0
OR
AE
AF
H
H
H
L
IR
H
H
H
H
L
0
1 to X
L
H
H
H
H
L
L
1 to X
1 to X
(X+1) to [512-(Y+1)]
(512-Y) to 511
512
(X+1) to [1,024-(Y+1)]
(1,024-Y) to 1,023
1,024
(X+1) to [2,048-(Y+1)]
(2,048-Y) to 2,047
2,048
H
H
H
L
NOTES:
1. When a word is present in the FIFO output register, its previous memory location is free.
2. Data in the output register does not count as a "word i n FIFO memory". Since in FWFT mode, the first words written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the memory count.
3. X is the Almost-Empty Offset for AE. Y is the Almost-Full Offset for AF.
11
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
edgethattakestheFIFOoutofretransmitmodeshiftsthereadpointerusedby withMBAHIGH. ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatothe
theIRandAFflagsfromtheshadowtothecurrentreadpointer. Ifthechange mail2registerwhena port-BWrite is selectedbyCSB, W/RB, andENBwith
ofreadpointerusedbyIRand AFshouldcause one orbothflags totransmit MBBHIGH. Writingdatatoamailregistersetsitscorrespondingflag(MBF1
HIGH, at least two CLKA synchronizing cycles are needed before the flags orMBF2)LOW. Attemptedwritestoamailregisterareignoredwhileitsmail
reflectthe change. ArisingCLKAedge afterthe FIFOis takenoutofretransmit flagisLOW.
mode is the first synchronizing cycle of IR if it occurs at time tSKEW1 or greater
Whentheport-Bdata(B0-B35)outputsareactive,thedataonthebuscomes
after the rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO fromtheFIFOoutputregisterwhentheport-BMailboxselect(MBB)inputisLOW
istakenoutofretransmitmodeisthefirstsynchronizingcycleofAFifitoccurs andfromtheMail1registerwhenMBBisHIGH. Mail2dataisalwayspresent
at time tSKEW2 or greater after the rising CLKB edge (see Figure 14).
ontheport-Adata(A0-A35)outputswhentheyareactive. TheMail1register
Flag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaport-
BReadisselectedbyCSB,W/RB,andENBwithMBBHIGH. TheMail2register
MAILBOX REGISTERS
Two36-bitbypassregistersareontheIDT72V3631/72V3641/72V3651to Flag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhenaport-
passcommandandcontrolinformationbetweenportAandportB. TheMailbox A Read is selected by CSA, W/RA, and ENA with MBA HIGH. The data in a
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport mailregisterremainsintactafteritisreadandchangesonlywhennewdatais
datatransferoperation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35data writtentotheregister. MailRegisterandMailRegisterFlagtimingcanbefound
tothemail1registerwhenaport-AWriteisselectedbyCSA,W/RA,andENA in Figure 15 and 16.
12
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
FSS
t
RSTS
t
FSH
RST
FS1,FS0
IR
0,1
tPIR
tPIR
tPOR
OR
AE
AF
t
RSF
t
RSF
t
RSF
MBF1,
MBF2
4658 drw 05
Figure 2. FIFO Reset and Loading X and Y with a Preset Value of Eight
CLKA
4
RST
t
FSH
t
FSS
FS1,FS0
IR
tPIR
tENS1
tENH1
ENA
tDS
tDH
A0 - A35
AF Offset
AE Offset
First Word
Stored in FIFO
(Y)
(X)
4658 drw 06
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A
13
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
CLKA
4
RST
tPIR
IR
tSENS
tSENH
t
FSS
tSENS
tSPH
tSENH
FS1/SEN
t
FSH
tSDS
tSDH
t
FSS
tSDH
tSDS
FS0/SD
4658 drw 07
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTE:
1. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
Figure 4. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
tCLK
tCLKH
tCLKL
CLKA
IR
HIGH
tENS2
tENH2
CSA
tENS2
tENH2
W/RA
tENS2
tENH2
MBA
ENA
tENS1
tENS1
tENH1
tENH1
tENS1
tENH1
tDH
tDS
No Operation
A0 - A35
W1
W2
4658 drw 08
Figure 5. FIFO Write Cycle Timing
tCLK
tCLKH
tCLKL
CLKB
OR HIGH
CSB
W/RB
MBB
ENB
t
ENH1
t
ENH1
A
t
ENH1
tENS1
t
ENS1
tENS1
No Operation
W3
tDIS
t
t
MDV
t
A
tEN
B0 - B35
W2
W1
4658 drw 09
Figure 6. FIFO Read Cycle Timing
14
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
t
t
CLKH CLK tCLKL
CLKA
CSA LOW
W/RA
HIGH
t
ENS2
t
ENH2
ENH1
MBA
t
ENS1
t
ENA
IR HIGH
A0 - A35
t
DH
tDS
W1
t
CLKH CLKtCLKL
(1)
t
SKEW1
t
1
2
3
CLKB
OR FIFO Empty
tPOR
t
POR
CSB
LOW
HIGH
LOW
W/RB
MBB
tENS1
tENH1
ENB
tA
Old Data in FIFO Output Register
W1
B0 -B35
4658 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and the first word load to the output register may occur one CLKB cycle
later than shown.
Figure 7. OR Flag Timing and First Data Word Fall Through when the FIFO is Empty
15
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
LOW
MBB
tENS1
tENH1
ENB
OR HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0 - B35
(1)
SKEW1
tCLK
t
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
FIFO Full
LOW
IR
CSA
W/RA HIGH
tENH2
tENS2
MBA
ENA
tENS1
tENH1
tDS
tDH
Write
A0 - A35
4658 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 8. IR Flag Timing and First Available Write when the FIFO is Full
CLKA
tENS1
tENH1
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Word in FIFO
(X+1) Words in FIFO
ENS1
t
ENH1
t
ENB
4658 drw 12
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
Figure 9. Timing for AE when FIFO is Almost-Empty
16
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKA
tENH1
tENS1
ENA
t
PAF
tPAF
(Depth(2) -Y) Words in FIFO
[Depth(2)-(Y+1)] Words in FIFO
AF
CLKB
ENB
tENS1
tENH1
4658 drw 13
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT72V3631, 1,024 for the IDT72V3641, and 2,048 for the IDT72V3651.
3. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
Figure 10. Timing for AF when FIFO is Almost-Full
CLKB
t
ENH1
RMH
t
ENS1
ENB
RTM
RFM
t
RMS
t
RMS
tRMH
t
t
RMS
tRMH
HIGH
OR
tA
tA
tA
tA
W0
W1
W2
Retransmit from
Selected Position
W0
W1
4658 drw 14
B0-B35
End Retransmit
Mode
Initiate Retransmit Mode
with W0 as First Word
NOTE:
1. CSB = LOW, W/RB = HIGH, MBB = LOW. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown only to relate
retransmit operations to the FIFO output register.
Figure 11. Retransmit Timing Showing Minimum Retransmit Length
1
CLKB
RTM
RFM
2
HIGH
t
RMS
tRMH
t
PAE
AE
X or fewer words from Empty
(X+1) or more
words from Empty
4658 drw 15
NOTE:
1. X is the value loaded in the Almost-Empty flag Offset register.
Figure 12. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X.
17
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
One or More Write Locations Available
4658 drw 16
(1)
t
SKEW1
CLKA
IR
1
2
tPIR
FIFO Filled to First Restransmit Word
CLKB
RTM
t
RMS
tRMH
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
(1)
tSKEW2
CLKA
1
2
t
PAE
(Depth(2)-Y) or More Words Past First Restransmit Word
AF
(Y+1) or More Write Locations Available
CLKB
tRMH
t
RMS
RTM
4658 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT72V3631, 1,024 for the IDT72V3641, and 2,048 for the IDT72V3651.
3. Y is the value loaded in the Almost-Full flag Offset register.
Figure 14. AF Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
CLKA
tENS2
tENH2
CSA
tENH2
tENS2
W/RA
tENS2
tENH2
MBA
tENS2
tENH2
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH1
tENS1
t
PMR
tEN
t
DIS
t
MDV
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4658 drw 18
Figure 15. Timing for Mail1 Register and MBF1 Flag
18
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
CLKB
t
ENS2
tENH2
tENH2
tENH2
CSB
tENS2
W/RB
tENS2
MBB
ENB
tENH2
tENS2
tDH
tDS
B0 - B35
W1
CLKA
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH1
tENS1
tEN
t
PMR
tDIS
A0 - A35
W1 (Remains valid in Mail2 Register after read)
4658 drw 19
Figure 16. Timing for Mail2 Register and MBF2 Flag
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
CLKB
OR
CLKA
READ CLOCK (CLKB)
CHIP SELECT (CSA)
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
CHIP SELECT (CSB)
ENA
IR
V
CC
OUTPUT READY (OR)
READ ENABLE (ENB)
ENB
IDT
IDT
V
CC
CSB
CSA
72V3631
72V3641
72V3651
72V3631
72V3641
72V3651
READ SELECT (W/RB)
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A0-A35
Dn
n
B0-B35
Qn
B0-B35
n
DATA OUT (Qn)
INPUT READY (IR)
MBA
V
CC
V
CC
MBB
W/RA
W/RB
4658 drw 20
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. Retransmit feature is not supported in depth expansion applications.
4. The amount of time it takes for OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum
of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
5. The amount of time is takes for IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N -
1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 17. Block Diagram of 512 x 36, 1,024 x 36, 2,048 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
19
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330
Ω
From Output
Under Test
30 pF (1)
510
Ω
3 V
3 V
Timing
Input
1.5 V
High-Level
Input
1.5 V
1.5 V
GND
GND
3 V
t
S
th
tW
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
1.5 V
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
¯
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
¯
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4658 drw 21
NOTE:
1. Includes probe and jig capacitance
Figure 18. Load Circuit and Voltage Waveforms
20
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
PF
PQF
15
20
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
512 x 36 3.3V SyncFIFO
1,024 x 36 3.3V SyncFIFO
2,048 x 36 3.3V SyncFIFO
72V3631
72V3641
72V3651
4658 drw 22
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
07/31/2000
11/04/2003
pgs. 1, 14, 21.
pg. 1.
CORPORATE HEADQUARTERS
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800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
21
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