IDT72V3676L15PF8 [IDT]
Bi-Directional FIFO, 8KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128;型号: | IDT72V3676L15PF8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Bi-Directional FIFO, 8KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128 时钟 先进先出芯片 内存集成电路 |
文件: | 总39页 (文件大小:385K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3656
IDT72V3666
IDT72V3676
• Serial or parallel programming of partial flags
FEATURES
• Big- or Little-Endian format for word and byte bus sizes
• Loopback mode on Port A
• Retransmit Capability
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V parts,
IDT723656/723666/723676
• Pin compatible to the lower density parts, IDT72V3626/3636/3646
• Industrial temperature range (–40°C to +85°C) is available
• Memory storage capacity:
IDT72V3656
IDT72V3666
IDT72V3676
–
–
–
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
CLKA
CSA
Register
Port-A
Control
Logic
18
W/RA
B0-B17
ENA
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
MBA
36
36
LOOP
CLKB
RENB
CSB
Port-B
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
PRS1
MBB
Read
Pointer
Write
Pointer
SIZEB
36
Status Flag
Logic
FFA/IRA
EFB/ORB
AFA
AEB
FIFO1
FIFO2
Common
Port
FS2
FS0/SD
Control
Logic
Programmable Flag
Offset Registers
Timing
Mode
BE
FS1/SEN
(B and C)
A0-A35
13
FWFT
FFC/IRC
AFC
Status Flag
Logic
EFA/ORA
AEA
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
36
RT1
RTM
RT2
FIFO1 and
FIFO2
Retransmit
Logic
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
18
36
36
C0-C17
CLKC
WENC
MBC
Port-C
Control
Logic
Mail 2
Register
SIZEC
4665 drw01
MBF2
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4665/4
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SRAMFIFOsonboardeachchipbufferdatabetweenabidirectional36-bitbus
(Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C
receivesdata.) FIFOdatacanbereadoutofPortBandwrittenintoPortCusing
either18-bitor9-bitformatswithachoiceofBig-orLittle-Endianconfigurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface. Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
DESCRIPTION
TheIDT72V3656/72V3666/72V3676arepinandfunctionallycompatible
versionsoftheIDT723626/723636/723646,designedtorunoffa3.3Vsupply
for exceptionally low-power consumption. These devices are a monolithic,
high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO
memorywhichsupportsclockfrequenciesupto100MHzandhasreadaccess
times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port
PIN CONFIGURATION
INDEX
1
2
3
4
5
6
7
8
CLKB
PRS2/RT2
LOOP
C17
C16
C15
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C14
RTM
MBC
C13
C12
C11
C10
C9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C8
VCC
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
C0
GND
B17
B16
SIZEC
VCC
B15
B14
B13
B12
GND
B11
B10
4665 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or aselectednumberofwordsremainintheFIFOmemory. AFAandAFCindicate
coincident. The enables for each port are arranged to provide a simple whenthe FIFOcontains more thana selectednumberofwords.
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the
Port Clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox AEBaretwo-stagesynchronizedtothePortClockthatreadsdatafromitsarray.
registers.Themailboxregisters'widthmatchestheselectedbuswidthofports Programmableoffsets forAEA, AEB,AFA,AFCareloaded inparallelusing
BandC. Eachmailboxregisterhas aflag(MBF1and MBF2)tosignalwhen PortAorinserialviatheSDinput.Fivedefaultoffsetsettingsarealsoprovided.
newmailhas beenstored.
TheAEAandAEBthresholdcanbesetat8,16, 64,256,and1,024locations
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial from the empty boundary and the AFA and AFC threshold can be set at 8,
Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation 16,64,256or1,024locationsfromthefullboundary. Allthesechoicesaremade
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram- using the FS0, FS1 and FS2 inputs during Master Reset.
ming,or oneoffivepossibledefaultflagoffsetsettings,8,16,64,256or1,024.
Interspersed Parity can also be selected during a Master Reset of the
Each FIFO has its own, independent Master Reset pin, MRS1 and MRS2. FIFO.IfInterspersedParityisselectedthenduringparallelprogrammingofthe
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe flagoffsetvalues,thedevicewillignoredatalineA8.IfNon-InterspersedParity
memory. UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., is selectedthendatalineA8willbecomeavalidbit.
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
A Loopback function is provided on Port A. When the Loop feature is
is useful since it permits flushing of the FIFO memory without changing any selectedviatheLOOP pin,thedataoutputfromFIFO2willbedirectedtothe
configurationsettings. EachFIFOhasitsown,independentPartialResetpin, datainputofFIFO1.IfLoopisselectedandPortAisset-upforwriteoperation
PRS1 andPRS2. Note thatthe RetransmitMode, RTMpinmustbe LOWat viaW/RApin,thendataoutputfromFIFO2willbewrittentoFIFO1,butwillnot
thepointapartialresetisperformed.
beplacedontheoutputPortA(A0-A35).IfPortAisset-upforreadoperation
BothFIFO'shaveRetramsmitcapability,whenaRetransmitisperformed viaW/RAthendataoutputfromFIFO2willbewrittenintoFIFO1andplacedonto
onarespectiveFIFOonlythereadpointerisresettothefirstmemorylocation. PortA(A0-A35).TheLoopwillcontinuetohappenprovidedthatFIFO1isnot
ARetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction fullandFIFO2isnotempty.IfduringaLoopsequenceFIFO1becomesfullthen
withtheRetransmitpinsRT1orRT2,foreachrespectiveFIFO.Notethatthe anydata thatcontinues tobe readoutfromFIFO2willonlybe placedonthe
two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins.
PortA(A0-A35)lines,providedthatPortAisset-upforreadoperation.Ifduring
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, aLoopsequencetheFIFO2becomesempty,thenthelastwordfromFIFO2
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntiltheLoop
read operation is required to access that word (along with all other words functionisstopped.TheLoopfeaturecanbeusefulwhenperformingsystem
residing in memory). In the First Word Fall Through mode (FWFT), the first debuggingandremoteloopbacks.
wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread
Twoormore FIFOs maybe usedinparalleltocreate widerdata paths.
operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- Suchawidthexpansionrequiresnoadditional,externalcomponents. Further-
sitate a formal read request). The state of the BE/FWFT pin during Master more, two IDT72V3656/72V3666/72V3676 FIFOs can be combined with
Resetdeterminesthemodeinuse.
unidirectional FIFOs capable of First Word Fall Through timing (i.e. the
EachFIFOhas a combinedEmpty/OutputReadyFlag(EFA/ORAand SuperSyncFIFOfamily)toforma depthexpansion.
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/
If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill
IRC). The EF and FF functions are selected in the IDT Standard mode. EF automatically power down. During the power down state, supply current
indicates whether or not the FIFO memory is empty. FF shows whetherthe consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
memoryisfullornot. TheIRandORfunctionsareselectedintheFirstWord inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
FallThroughmode. IRindicateswhetherornottheFIFOhasavailablememory
locations. ORshowswhethertheFIFOhasdataavailableforreadingornot. 0°Cto70°C. Industrial temperature range (-40°C to +85°C)is available by
Itmarksthepresenceofvaliddataontheoutputs. specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS
TheIDT72V3656/72V3666/72V3676arecharacterizedforoperationfrom
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and technology.
aprogrammableAlmost-Fullflag(AFAandAFC). AEAandAEB indicatewhen
3
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
PortAData
I/O
Description
A0-A35
I/O 36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
EmptyFlag
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA. ItisLOWwhenthenumberofwordsinFIFO2
islessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
AEB
AFA
AFC
PortBAlmost-
EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenthenumberofwordsinFIFO1
islessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
PortAAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocations
inFIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
PortCAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKC.ItisLOWwhenthenumberofemptylocations
inFIFO2is less thanorequaltothe value inthe Almost-FullCOffsetregister, Y2.
B0-B17
PortBData
O
I
18-bitoutputdataportforsideB.
BE/FWFT
Big-Endian/
FirstWordFall
ThroughSelect
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
In this case, depending on the bus size, themost significant byte or word on Port A is read from
PortBfirst(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow). ALOWonBEwillselect
Little-Endianoperation.Inthis case,theleastsignificantbyteorwordonPortAis readfromPortBfirst
(A-to-Bdata flow)oris writtentoPortCfirst(C-to-Adata flow).
AfterMasterReset, this pinselects the timingmode. AHIGHonFWFT selects IDTStandardmode, a
LOWselectsFirstWordFallThroughmode.Oncethetimingmodehasbeenselected,thelevelon
FWFT must be static throughout device operation.
C0-C17
CLKA
PortC Data
PortAClock
I
I
18-bitinputdataportforsideC.
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to
theLOW-to-HIGHtransitionofCLKA.
CLKB
CLKC
CSA
PortBClock
PortCClock
I
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbeasynchronous
or coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKCis acontinuous clockthatsynchronizes alldatatransfers throughPortCandcanbeasynchronous
or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB. The B0-B17
outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
PortAEmpty/
OutputReady
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFA functionis selected. EFA indicates
whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORA
indicates the presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
EFB/ORB
PortBEmpty/
OutputReadyFlag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFB functionis selected. EFB indicates
whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB
indicatesthepresenceofvaliddataontheB0-B17outputs,availableforreading. EFB/ORBissynchronized
totheLOW-to-HIGHtransitionofCLKB.
ENA
PortAEnable
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
FFA/IRA
PortAFull/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whetherornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FFC/IRC
Port C Full/
Input Ready Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFCfunctionis selected. FFC indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC
indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRC is
synchronizedtotheLOW-to-HIGHtransitionofCLKC.
4
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
FS0/SD
FlagOffsetSelect0/
SerialData
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.DuringMasterReset,
FS1/SENandFS0/SD,togetherwithFS2,selecttheflagoffsetprogrammingmethod. ThreeOffsetregister
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
parallelloadfromPortA, andserialload.
FS1/SEN FlagOffsetSelect1/
I
I
SerialEnable
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SEN isusedasanenablesynchronousto
the LOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW, a risingedge onCLKAloadthe bitpresenton
FS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe Offsetregisters is 44forthe
72V3656, 48 for the 72V3666, and 52 for the 72V3676. The first bit write stores the Y-register (Y1) MSB and the
lastbitwritestorestheX-register(X2)LSB.
FS2(1)
FlagOffsetSelect2
LOOP
LoopbackSelect
I
I
This pinselects theloopbackfeatureforPortA.DuringLoopbackdatafromFIFO2willbedirectedtotheinputof
FIFO1. toinitiate a Loopthe LOOP pinmustbe heldLOWandthe ENApinmustbe HIGH.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputsareactive,aHIGHlevelonMBAselectsdatafromthemail2registerforoutputandaLOWlevelselects
FIFO2output-registerdataforoutput.
MBA
Port A Mailbox
Select
MBB
Port B Mailbox
Select
I
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active,aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselectsFIFO1output
registerdataforoutput.
MBC
Port C Mailbox
Select
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
MasterReset.
MBF1
Mail1Register
Flag
O MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.Writestothemail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
MRS1
Mail2Register
Flag
O MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKCthatwritesdatatothemail2register.Writestothemail2
registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-HIGHtransitionofCLKAwhena
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MasterReset
I
ALOWonthis pin initializes theFIFO1readandwritepointers tothefirstlocationofmemoryandsets thePortB
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialor
parallel)andone offive programmable flagdefaultoffsets forFIFO1andFIFO2. Italsoconfigures ports Band
Cforbus size andendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-HIGH
transitionsofCLKBmustoccurwhileMRS1isLOW.
MRS2
MasterReset
I ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA
outputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywithMRS1,selects
theprogrammingmethod(serialorparallel)andoneof thefiveflagdefaultoffsetsforFIFO2.FourLOW-to-HIGH
transitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKCmustoccurwhileMRS2isLOW.
PRS1/
RT1
PartialReset/
RetransmitFIFO1
I
ThispinismuxedforbothPartialReset andRetransmitoperations,itisusedinconjunctionwiththeRTMpin. IfRTM
isinaLOWcondition,aLOWonthispinperformsaPartialResetonFIFO1andinitializestheFIFO1readandwrite
pointerstothefirstlocationofmemoryandsetsthePortBoutputregistertoallzeroes.DuringPartialReset,thecurrently
selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsare
allretained. IfRTMis HIGH, a LOWonthis pinperforms a Retransmitandinitializes the FIFO1readpointeronlyto
thefirstmemorylocation.
PRS2/
PartialReset/
I ThispinismuxedforbothPartialReset andRetransmitoperations,itisusedinconjunctionwiththeRTMpin. IfRTM
RT2
RetransmitFIFO2
isinaLOWcondition,aLOWonthispinperformsaPartialResetonFIFO2andinitializestheFIFO2readandwrite
selectedbussize,endianarrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsare
allretained. IfRTMis HIGH, a LOWonthis pinperforms a Retransmitandinitializes the FIFO2readpointeronlyto
thefirstmemorylocation.
RENB
RTM
Port B Read Enable
RetransmitMode
I
RENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreaddata onPortB.
Thispinisusedinconjunctionwiththe RT1andRT2pins.WhenRTMisHIGHaRetransmitisperformedonFIFO1
or FIFO2 respectively.
I
5
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
PortB
I/O
Description
(1)
SIZEB
I
SIZEBdetermines the bus widthofPortB. AHIGHonthis pinselects byte (9-bit)bus size. ALOWonthis pin
selects word(18-bit)bus size. SIZEBworks withSIZECandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZEBmustbe staticthroughoutdevice operation.
BusSizeSelect
(1)
SIZEC
Port C
BusSizeSelect
I
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word(18-bit)bus size. SIZECworks withSIZEBandBEtoselectthe bus size andendianarrangement
forports BandC. The levelofSIZECmustbe staticthroughoutdevice operation.
WENC
PortCWriteEnable
I
I
WENCmustbeHIGHtoenableaLOW-to-HIGHtransitionofCLKCtowritedataonPortC.
W/RA
PortAWrite/
ReadSelect
AHIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGHtransitionof
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
NOTE:
1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or VCC.
6
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
SupplyVoltagefor10ns
SupplyVoltagefor15ns
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
Min.
3.15
3.0
2
Typ.
3.3
3.3
—
Max.
3.45
3.6
Unit
V
(1)
VCC
VCC
VIH
VIL
IOH
IOL
TA
V
VCC+0.5
0.8
V
—
—
—
0
—
V
—
–4
mA
mA
°C
—
8
—
70
NOTE:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3656
IDT72V3666
IDT72V3676
Commercial
tCLK = 10, 15 ns(2)
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min.
2.4
—
—
—
—
—
—
—
Typ.(1)
—
—
—
—
—
—
4
Max.
—
0.5
±10
±10
5
Unit
V
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
OutputLogic"0"Voltage
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
µ A
µ A
mA
mA
pF
ILO
ICC2(3)
ICC3(3)
Standby Current (with CLKA, CLKB & CLKC running)
StandbyCurrent(noclocksrunning)
InputCapacitance
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
1
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
7
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3656/72V3666/72V3676withCLKA,
CLKBandCLKCsettofS. Alldata inputs anddata outputs change state duringeachclockcycle toconsume the highestsupplycurrent. Data outputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice'sinputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL = outputcapacitanceload
fo = switchingfrequencyofanoutput
100
90
VCC = 3.6V
80
70
60
VCC = 3.0V
VCC = 3.3V
fdata = 1/2 fS
TA
= 25°C
CL
= 0 pF
50
40
30
20
10
0
100
0
10
20
30
40
50
Clock Frequency MHz
60
70
90
80
4665 drw02a
fS
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
8
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C;JEDEC JESD8-A compliant)
IDT72V3656L10(1)
IDT72V3666L10(1)
IDT72V3676L10(1)
IDT72V3656L15
IDT72V3666L15
IDT72V3676L15
Symbol
fS
Parameter
Min.
—
10
4.5
4.5
3
Max.
Min.
—
15
6
Max.
Unit
MHz
ns
Clock Frequency, CLKA, CLKB, or CLKC
100
—
—
—
—
—
66.7
—
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA, CLKB, or CLKC
Pulse Duration, CLKA, CLKB, or CLKC HIGH
Pulse Duration, CLKA, CLKB, ORCLKCLOW
Setup Time, A0-A35 before CLKA↑ andC0-C17before CLKC↑
—
ns
6
—
ns
4
—
ns
tENS1
SetupTime, CSA andW/RAbefore CLKA↑; CSB
beforeCLKB↑
4
4.5
—
ns
tENS2
tRSTS
SetupTime, ENA, andMBAbefore CLKA↑;RENB
3
5
—
—
4.5
5
—
—
ns
ns
and MBB before CLKB↑; WENC and MBC before CLKC↑
Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
(2)
LOWbeforeCLKA↑orCLKB↑
tFSS
tBES
Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH
SetupTime, BE/FWFT beforeMRS1 andMRS2 HIGH
SetupTime,FS0/SDbeforeCLKA↑
7.5
7.5
3
—
—
—
—
—
—
—
—
8.5
7.5
4
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
tSDS
tSENS
tFWS
tRTMS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
SetupTime,BE/FWFTbeforeCLKA↑
0
0
Setup Time, RTM before RT1; RTM before RT2
HoldTime, A0-A35afterCLKA↑ andC0-C17afterCLKC↑
5
5
0.5
0.5
1
tENH
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;CSB,
RENB, andMBBafterCLKB↑;WENCandMBCafterCLKC↑
1
tRSTH
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
4
—
4
—
ns
(2)
LOWafterCLKA↑orCLKB↑
tFSH
Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
HoldTime, FS0/SDafterCLKA↑
2
2
—
—
—
—
—
—
—
2
2
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tBEH
tSDH
0.5
0.5
2
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
HoldTime, RTMafterRT1;RTMafterRT2
2
tRTMH
5
5
(3)
tSKEW1
SkewTime, betweenCLKA↑ andCLKB↑for EFB/ORBand
FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and
FFC/IRC
5
7.5
(3,4)
tSKEW2
SkewTime,betweenCLKA↑andCLKB↑for AEBandAFA;
between CLKA↑ and CLKC↑ for AEA and AFC
12
—
12
—
ns
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
4. Design simulated, not tested.
9
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C;JEDEC JESD8-A compliant)
IDT72V3656L10(1)
IDT72V3666L10(1)
IDT72V3676L10(1)
IDT72V3656L15
IDT72V3666L15
IDT72V3676L15
Symbol
tA
Parameter
Min.
2
Max.
6.5
Min.
2
Max.
10
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B17
tWFF
PropagationDelayTime, CLKA↑toFFA/IRAandCLKC↑ to
FFC/IRC
2
6.5
2
8
ns
tREF
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑to
EFB/ORB
1
6.5
1
8
ns
tPAE
tPAF
tPMF
PropagationDelayTime,CLKA↑toAEAandCLKB↑toAEB
Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC
1
1
0
6.5
6.5
6.5
1
1
0
8
8
8
ns
ns
ns
Propagation Delay Time, CLKA↑to MBF1 LOW orMBF2
HIGH, CLKB↑ to MBF1 HIGH, and CLKC↑ to MBF2 LOW
tPMR
tMDV
tRSF
PropagationDelayTime, CLKA↑ toB0-B17(2) andCLKC↑
3
2
1
6.5
8
2
2
1
10
10
15
ns
ns
ns
toA0-A35(3)
Propagation Delay Time, MBA to A0-A35 valid and MBB to
B0-B17 valid
Propagation Delay Time, MRS1 or PRS1 LOW to AEB
LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2
LOW to AEA LOW, AFC HIGH, andMBF2 HIGH
10
tEN
tDIS
Enable Time, CSA orW/RALOWtoA0-A35Active and
CSBLOWtoB0-B17Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35 at high
impedance and CSB HIGHtoB0-B17atHIGHimpedance
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
10
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
aFIFOfollowingaMasterResetwouldbeinconvenient. SeeFigure6and7
forPartialResettimingdiagrams.
SIGNALDESCRIPTION
MASTER RESET (MRS1, MRS2)
RETRANSMIT (RT1, RT2)
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memoryoftheIDT72V3656/72V3666/72V3676undergoesacompletereset
bytakingitsassociatedMasterReset(MRS1)inputLOWforatleastfourPort
AClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions. The
FIFO2memoryundergoes acompleteresetbytakingits associatedMaster
Reset(MRS2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions. TheMasterResetinputscanswitch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and the Almost-
Fullflag(AFA,AFC)HIGH. AMasterResetalsoforcestheassociatedMailbox
Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master
Reset,theFIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles.
Then the FIFO is ready to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input
latchesthevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhich
bytes aretransferredthroughPorts BandC. Italsolatches thevalues ofthe
FlagSelect (FS0,FS1andFS2)inputsforchoosingtheAlmost-FullandAlmost-
Emptyoffsetsandprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearsthe
flagoffsetregistersofFIFO2(X2,Y2). ALOW-to-HIGHtransitionontheFIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetsandprogrammingmethod(fordetailsseeTable
1,FlagProgramming,andAlmost-EmptyandAlmost-Fullflagoffsetprogram-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
TheFIFO1memoryofthesedevicesundergoesaRetransmitbytakingits
associatedRetransmit (RT1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializesthereadpointerofFIFO1tothefirstmemorylocation.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit(RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions.TheRetransmitinitializestheread
pointerofFIFO1tothefirstmemorylocation.
The RTM pin must be HIGH during the time of Retransmit. Note that the
RT1inputismuxedwiththePRS1input,thestateoftheRTMpindetermining
whetherthispinperformsaRetransmitorPartialReset.Also,theRT2inputis
muxedwiththePRS2input,thestateoftheRTMpindeterminingwhetherthis
pinperformsaRetransmitorPartialReset.SeeFigures30,31,32and33for
Retransmittimingdiagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
isactive,permittingachoiceofBig-orLittle-Endianbytearrangementfordata
writtentoPortCorreadfromPortB.Thisselectiondeterminestheorderbywhich
bytes(orwords)ofdataaretransferredthroughthoseports.Forthefollowing
illustrations,notethatbothports B andCareconfiguredtohaveabyte(ora
word) bus size.
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata
ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAastheleast
significantbyte(word)ofthelongword.
Note that MBC must be HIGH during Master Reset (until FFA/IRA and
FFC/IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master
Reset.
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortCtoPortA,thebyte(word)writtento
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortClastwillbereadfromPortAasthemost
significantbyte(word)ofthelongword.RefertoFigure2and3forillustrations
oftheBEfunction.SeeFigure4(FIFO1MasterReset)and5(FIFO2Master
Reset)forEndianSelecttimingdiagrams.
PARTIAL RESET (PRS1, PRS2)
TheFIFO1memoryofthesedevicesundergoesalimitedresetbytaking
its associated Partial Reset (PRS1) input LOW for at least four Port A Clock
(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.TheFIFO2
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(PRS2)
inputLOWforatleastfourPortAClock(CLKA)andfourPortCClock(CLKC)
LOW-to-HIGHtransitions.TheRTMpinmustbeLOWduringthetimeofpartial
reset.ThePartialResetinputscanswitchasynchronouslytotheclocks.APartial
ResetinitializestheinternalreadandwritepointersandforcestheFull/Input
Ready flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/
ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Full flag (AFA, AFC) HIGH. A Partial Reset also forces the Mailbox
Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial
Reset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is
HIGH,aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransition
ofCLKA(forFIFO1)andCLKC(forFIFO2)willselectIDTStandardmode.This
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
11
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
modeusestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthere orLOWduringamasterreset.Forexample,toloadthepresetvalueof64into
areanywordspresentintheFIFOmemory.ItusestheFullFlagfunction(FFA, X1andY1,FS0,FS1andFS2mustbeHIGHwhenFlFO1reset(MRS1)returns
FFC)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting. HIGH.FlagOffsetregisters associatedwithFIFO2areloadedwithoneofthe
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must preset values in the same way with FIFO2 Master Reset (MRS2) toggled
be requestedusinga formalreadoperation.
simultaneously with FIFO1 Master Reset (MRS1). For relevant Preset value
OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/ loading timing diagrams, see Figure 4 and 5.
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKC(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady — PARALLEL LOAD FROM PORT A
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster
outputs(A0-A35orB0-B17).ItalsousestheInputReadyfunction(IRA,IRC) ResetonbothFlFOs simultaneouslywithFS2HIGHorLOW, FS0andFS1
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata FS2atthispointofresetwilldeterminewhethertheparallelprogrammingmethod
outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby hasInterspersedParityorNon-InterspersedParity.RefertoTable1forFlag
performingaformalreadoperation.
Programming Flag Offset setup . It is important to note that once parallel
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose programminghasbeenselectedduringaMasterResetbyholdingbothFS0
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation. Refer & FS1 LOW, these inputs must remain LOW during all subsequent FIFO
toFigure4(FIFO1MasterReset)andFigure5(FIFO2MasterReset)forFirst operation. They can only be toggled HIGH when future Master Resets are
WordFallThroughselecttimingdiagrams.
performedandotherprogrammingmethodsaredesired.
Afterthisresetiscomplete,thefirstfourwritestoFIFO1donotstoredatain
RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
FourregistersintheseFIFOsareusedtoholdtheoffsetvaluesfortheAlmost- InterspersedParitymodethePortAdatainputsusedbytheOffsetregistersare
EmptyandAlmost-Fullflags.ThePortBAlmost-Emptyflag(AEB)Offsetregister (A10-A0), (A11-A0), or (A12-A0) for the IDT72V3656, IDT72V3666, or
islabeledX1andthePortAAlmost-Emptyflag(AEA)Offsetregisterislabeled IDT72V3676,respectively.ForInterspersedParitymodethePortAdatainputs
X2.ThePortAAlmost-Fullflag(AFA)OffsetregisterislabeledY1andthePort usedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9,A7-A0),or(A13-
CAlmost-Fullflag(AFC)OffsetregisterislabeledY2.Theindexofeachregister A9,A7-A0)fortheIDT72V3656,IDT72V3666,orIDT72V3676,respectively.
namecorrespondstoitsFIFOnumber.TheOffsetregisterscanbeloadedwith The highest numbered input is used as the most significant bit of the binary
preset values during the reset of a FIFO, programmed in parallel using the numberineachcase.Validprogrammingvaluesfortheregistersrangefrom
FIFO’sPortAdatainputs,orprogrammedinserialusingtheSerialData(SD) 1to2,044fortheIDT72V3656;1to4,092fortheIDT72V3666;and1to8,188
input (see Table 1).
fortheIDT72V3676.AfteralltheOffsetregistersareprogrammedfromPortA,
FS0/SD,FS1/SENandFS2functionthesamewayinbothIDTStandard thePortCFull/InputReadyflag(FFC/IRC)issetHIGH,andbothFIFOsbegin
andFWFTmodes.
normaloperation.RefertoFigure8foratimingdiagramillustrationforparallel
programmingoftheflagoffsetvalues.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH
TABLE 1 FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
L
L
H
H
L
L
H
L
L
H
H
L
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
↑
↑
64
X
X
64
16
X
L
X
16
H
H
H
H
H
H
L
8
X
X
8
256
X
X
256
1,024
X
1,024
X
SerialprogrammingviaSD
SerialprogrammingviaSD
(3,5)
(3,5)
L
ParallelprogrammingviaPortA
ParallelprogrammingviaPortA
IP Mode(4, 5)
L
IP Mode(4, 5)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
12
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 2 PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
LOOP
Data A(A0-A35) I/O
PORT FUNCTION
H
L
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
↑
X
↑
X
↑
↑
H
H
H
H
H
H
H
H
L
High-Impedance
Input
None
None
H
H
L
Input
FIFO1 write
Mail1write
H
L
Input
Output
Output
Output
Output
Output
None
L
H
L
L
FIFO2read
None
L
H
H
L
L
H
H
Mail2 read (set MBF2 HIGH)
H
LoopthedataoutputofFIFO2toinput
of FIFO1 only
L
L
H
L
↑
L
Output
LoopthedataoutputofFIFO2toinput
of FIFO1 and put data on Port A
TABLE 3 PORT B ENABLE FUNCTION TABLE
CSB
RENB
MBB
CLKB
Data B (B0-B17) Outputs
PORT FUNCTION
H
L
L
L
L
X
L
X
L
X
X
↑
X
↑
High-Impedance
Output
None
None
H
L
L
Output
FIFO1read
H
H
Output
None
H
Output
Mail1 read (set MBF1 HIGH)
TABLE 4 PORT C ENABLE FUNCTION TABLE
WENC
MBC
CLKC
Data C (C0-C17) Inputs
PORT FUNCTION
H
H
L
L
L
H
L
↑
↑
X
X
Input
Input
Input
Input
FIFO2 write
Mail2write
None
H
None
WhentheoptiontoprogramtheOffsetregistersseriallyischosen,thePort
AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFC/
IRC)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until
allregisterbitsarewritten.FFC/IRCissetHIGHbytheLOW-to-HIGHtransition
ofCLKCafterthelastbitis loadedtoallownormalFIFO2operation.
SeeFigure9timingdiagram,SerialProgrammingoftheAlmost-FullFlag
andAlmost-EmptyFlagOffsetValuesafterReset(IDTStandardandFWFT
Modes).
INTERSPERSED PARITY
InterspersedParityisselectedduringaMasterResetoftheFIFO.Referto
Table1fortheset-upconfigurationofInterspersedParity.TheInterspersed
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword
loaded into the parallel port (A0-An) during programming of the flag offset
values.IfInterspersedParityisselectedthenduringparallelprogrammingof
theflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
ParityisselectedthendatalineA8willbecomeavalidbit.IfInterspersedParity
isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
programmingcanbedone.
FIFO WRITE/READ OPERATION
— SERIAL LOAD
ThestateofthePortAdata(A0-A35)outputsiscontrolledbyPortAChip
Select(CSA)andPortAWrite/ReadSelect(W/RA).TheA0-A35outputsare
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35
outputs are active whenbothCSA andW/RAare LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand
writes on Port A are independent of any concurrent Port B or Port C
operation.
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
withFS2LOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
transitionofMRS1andMRS2.Afterthisresetiscomplete,theXandYregister
valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH
transitionofCLKAthattheFS1/SENinputisLOW.Thereare44-,48-,or52-
bitwritesneededtocompletetheprogrammingfortheIDT72V3656,IDT7V3666,
or IDT72V3676, respectively. The four registers are written in the order Y1,
X1,Y2andfinally,X2.Thefirst-bitwritestoresthemostsignificantbitoftheY1
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
registervaluecanbeprogrammedfrom1to2,044(IDT72V3656),1to4,092
(IDT72V3666), or 1 to 8,188 (IDT72V3676).
13
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
The state of the Port B data (B0-B17) outputs is controlled by the Port B ReadClock.Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Chip Select (CSB). The B0-B17 outputs are in the high-impedance state Instead, data residing in the FIFO’s memory array is clocked to the output
when CSB is HIGH. The B0-B17 outputs are active when CSB is LOW.
registeronlywhenareadisselectedusingCSA,W/RA,ENAandMBAatPort
Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH A or using CSB, RENB and MBB at Port B. Relevant write and read timing
transitionofCLKBwhenCSBisLOW,RENBisHIGH,MBBisLOWandEFB/ diagramsforPortAcanbefoundinFigure10and15. Relevantreadandwrite
ORB is HIGH (see Table 3). FIFO reads on Port B are independent of any timingdiagramsforPortBandPortC,togetherwithBus-MatchingandEndian
concurrentPortAandPortCoperations.
select operation, can be found in Figure 11 to 14.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transitionofCLKCwhenWENBisHIGH,MBCisLOW,andFFC/IRCisHIGH LOOPBACK (LOOP)
(seeTable4).FIFOwritesonPortCareindependentofanyconcurrentPort
A and Port B operation.
A Loopback function is provided on Port A and is selected by setting the
LOOPpinLOW.WhentheLoopfeatureisselected,thedataoutputfromFIFO2
ThesetupandholdtimeconstraintsforCSAandW/RAwithregardtoCLKA willbedirectedtothedatainputofFIFO1.IfLoopisselectedandPortAisset-
as well as CSB with regard to CLKB are only for enabling write and read upforwriteoperationviatheW/RApinbeingHIGH,thendataoutputfromFIFO2
operationsandarenotrelatedtohigh-impedancecontrolofthedataoutputs. willbewrittentoFIFO1,oneveryLOW-to-HIGHtransitionofCLKA,provided
IfENAis LOWduringa clockcycle, either CSA orW/RAmaychange states CSAisLOWandENAisHIGH.However,FIFO2dataoutputwillnotbeplaced
duringthe setupandholdtime windowofthe cycle. This is alsotrue forCSB ontheoutputPortA(A0-A35).IfPortAisset-upforreadoperationviatheW/
whenRENBis LOW.
RApinbeingLOW,thendataoutputfromFIFO2willbewrittenintoFIFO1on
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, every LOW-to-HIGH transition of CLKA, provided CSA is LOW and ENA is
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe HIGH. Also FIFO2 data will be output to Port A (A0-A35). When the LOOP
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. pin is HIGH then Port A operates in the normal manner. Refer to Table 2 for
WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput theinputset-upoftheLoopfeature.
registersonlywhenareadisselectedusingCSA,W/RA,ENAandMBAatPort
A or using CSB, RENB and MBB at Port B.
TheLoopoperationwillcontinuetohappenprovidedthatFIFO1isnotfull
andFIFO2isnotempty.IfduringaLoopsequenceFIFO1becomesfullthen
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause anydata thatcontinues tobe readoutfromFIFO2willonlybe placedonthe
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe Port A (A0-A35) lines, (provided that Port A is set-up for read operation). If
TABLE 5 FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3656
IDT72V3666
IDT72V3676
EFB/ORB
AEB
L
AFA
H
FFA/IRA
0
0
1toX1
0
1toX1
L
H
H
H
H
H
H
H
H
L
1toX1
L
H
(X1+1)to[2,048-(Y1+1)]
(2,048-Y1)to2,047
2,048
(X1+1)to[4,096-(Y1+1)]
(4,096-Y1)to4,095
4,096
(X1+1)to[8,192-(Y1+1)]
(8,192-Y1)to8,191
8,192
H
H
H
L
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 6 FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKA
Synchronized
to CLKC
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3656
IDT72V3666
IDT72V3676
EFA/ORA
AEA
AFC
FFC/IRC
0
1toX2
0
1toX2
0
1toX2
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X2+1)to[2,048-(Y2+1)]
(2,048-Y2)to2,047
2,048
(X2+1)to[4,096-(Y2+1)]
(4,096-Y2)to4,095
4,096
(X2+1)to[8,192-(Y2+1)]
(8,192-Y2)to8,191
8,192
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Dataintheoutputregisterdoes notcountas a"wordinFIFOmemory".SinceinFWFTmode,thefirstwordwrittentoanemptyFIFOgoes unrequestedtotheoutputregister(noreadoperation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.
14
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
duringaLoopsequencetheFIFO2becomes empty,thenthelastwordfrom
FIFO2willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntil
theLoopfunctionisstopped.TheLoopfeaturecanbeusefulwhenperforming
systemdebuggingandremoteloopbacks.SeeFigures34and35forLoopback
timingdiagrams.
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites
to the FIFO are ignored.
The Full/InputReadyflagofa FlFOis synchronizedtothe portclockthat
writes data toits array. ForbothFWFTandIDTStandardmodes, eachtime
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthantwo
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe
nextmemorywritelocationhasbeenread.ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag signal reliability by reducing the probability of
metastableeventswhenCLKAoperatesasynchronouslywithrespecttoeither
CLKB or CLKC. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized
to CLKA. EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and
AFCaresynchronizedtoCLKC.Tables5and6showtherelationshipofeach
port flag to FIFO1 and FIFO2.
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)
Thesearedualpurposeflags.IntheFWFTmode,theOutputReady(ORA,
ORB)functionisselected.WhentheOutputReadyflagisHIGH,newdatais
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 20, 21, 22, and 23).
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.
WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMmemoryfor
readingtotheoutputregister.WhentheEmptyFlagisLOW,thepreviousdata
word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array. For both the FWFT and IDT Standard modes,
theFIFOreadpointerisincrementedeachtimeanewwordisclockedtoitsoutput
register.ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportclockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthe
thirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simultaneously
forcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFOoutput
register.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
thetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOWuntil
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
the Empty Flag HIGH; only then can data be read.
ALMOST-EMPTYFLAGS(AEA,AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset,
programmedfromPortA,orprogrammedserially(seetheAlmost-Emptyflag
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW
whenits FIFOcontains Xorless words andis HIGHwhenits FIFOcontains
(X+1)ormorewords.AdatawordpresentintheFIFOoutputregisterhasbeen
readfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (AFA, AFC)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
bythecontentsofregisterY1forAFAandregisterY2forAFC.Theseregisters
areloadedwithpresetvaluesduringaFlFOreset,programmedfromPortA,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programmingsection).AnAlmost-FullflagisLOWwhenthenumberofwords
in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for
theIDT72V3656,IDT72V3666,orIDT72V3676respectively.AnAlmost-Full
flagisHIGHwhenthenumberofwordsinitsFIFOislessthanorequalto[2,048-
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figure 16, 17, 18 and 19).
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
These are dualpurpose flags. InFWFTmode, the InputReady(IRAand
IRC)functionisselected.InIDTStandardmode,theFullFlag(FFAandFFC)
15
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
(Y+1)],[4,096-(Y+1)],or[8,192-(Y+1)]fortheIDT72V3656,IDT72V3666,or
IDT72V3676respectively.NotethatadatawordpresentintheFIFOoutput IRCgoHIGH. MBAandMBBaredon'tcareinputsduringMasterReset.For
NotethatMBCmustbeHIGHduringMasterReset(until FFA/IRAand FFC/
registerhas beenreadfrommemory.
mailregisterandmailregisterflagtimingdiagrams,seeFigure28and29.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof BUS SIZING
fill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reducesthenumberofwordsinmemoryto[2,048/4,096/8,192-(Y+1)].ALOW-
to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthefirst
synchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)].
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle (see Figure 26 and 27).
PortBmaybeconfiguredineitheran18-bitwordora9-bitbyteformatfor
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independentlyforPorts BandC. The levelappliedtothe PortBSize Select
(SIZEB)inputdeterminesthePortBbussizeandthelevelappliedtothePort
CSizeSelect(SIZEC)inputdeterminesthePortCbussize.Theselevelsshould
bestaticthroughoutFIFOoperation.Bothbussizeselectionsareimplemented
atthecompletionofMasterReset,bythetimetheFull/InputReadyflagisset
HIGH, as shown in Figure 2 and 3.
TwodifferentmethodsforsequencingdatatransferareavailableforPorts
BandCregardlessofwhetherthebussizeselectionisbyte-orword-size.They
arereferredtoasBig-Endian(mostsignificantbytefirst)andLittle-Endian(least
significantbytefirst).ThelevelappliedtotheBig-EndianSelect(BE)inputduring
MAILBOX REGISTERS
EachFIFOhasan18-bitbypassregisterallowingthepassageofcommand theLOW-to-HIGHtransitionofMRS1andMRS2selectstheendianmethod
andcontrolinformationfromPortAtoPortBorfromPortCtoPortAwithoutputting
itinqueue.TheMailboxSelect(MBA,MBB andMBC)inputschoosebetween
amailregisterandaFIFOforaportdatatransferoperation.Theusablewidth
ofboththeMail1andMail2registersmatchestheselectedbussizeforportsB
and C.
thatwillbeactiveduringFIFOoperation.Thisselectionappliestobothports
BandC.TheendianmethodisimplementedatthecompletionofMasterReset,
bythetimetheFull/InputReadyflagissetHIGH,asshowninFigure2and3
(seeEndianSelectionsection).
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
onthesedevices.Bus-Matchingoperationsaredoneafterdataisreadfrom
theFIFO1RAM(PortB)andbeforedataiswrittentotheFIFO2RAM(PortC).
The Endian select operations are not available when transferring data via
mailboxregisters.Furthermore,boththeword-andbyte-sizebusselections
limitthewidthofthedatabusthatcanbeusedformailregisteroperations.In
thiscase,onlythosebytelanesbelongingtotheselectedword-orbyte-size
buscancarrymailboxdata.Theremainingdataoutputswillbeindeterminate.
Theremainingdatainputswillbedon’tcareinputs.Forexample,whenaword-
sizebusisselectedonPortB,thenmailboxdatacanbetransmittedonlyfrom
A0-A17toB0-B17.Whenabyte-sizebusisselectedonPortB,thenmailbox
datacanbetransmittedonlyfromA0-A8toB0-B8.Similarly,whenaword-size
busisselectedonPortC,thenmailboxdatacanbetransmittedonlyfromC0-
C17toA18-A35.Whenabyte-sizebusisselectedonPortC,thenmailboxdata
canbetransmittedonlyfromC0-C8toA18-A26.
WhensendingdatafromPortAtoPortBviatheMail1Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Register
whena PortAwrite is selectedby CSA, W/RA, andENAwithMBAHIGH. If
theselectedPortBbussizeis18bits,thentheusablewidthoftheMail1Register
employs data lines A0-A17. (Inthis case, A18-A35are don’tcare inputs.) If
theselectedPortBbussizeis9bits,thentheusablewidthoftheMail1Register
employs data lines A0-A8. (Inthis case, A9-A35are don’tcare inputs.)
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
whenaPortCwriteisselectedbyWENCwithMBCHIGH.IftheselectedPort
Cbussizeis18bits,thentheusablewidthoftheMail2Registeremploysdata
linesC0-C17.IftheselectedPortCbussizeis9bits,thentheusablewidthof
theMail2RegisteremploysdatalinesC0-C8.(Inthiscase,C9-C17aredon’t
careinputs.)
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe
mailregisterwhentheportmailboxselectinputisHIGH.
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadisselectedbyCSB,andRENBwithMBBHIGH.
Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.Forthe
9-bitbussize,9bitsofmailboxdataareplacedonB0-B8.(Inthiscase,B9-B17
areindeterminate.)
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.SincePort
Bcanhave a byte orwordsize, onlythe firstone ortwobytes appearonthe
selectedportionoftheFIFO1outputregister,withtherestofthelongwordstored
inauxiliaryregisters.Inthiscase,subsequentFIFO1readsoutputtherestof
the long word to the FIFO1 output register in the order shown by Figure 2.
WhenreadingdatafromFIFO1inbyteformat,theunusedB9-B17outputs
areindeterminate.
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
onCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENAwithMBA
HIGH.Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister.Foran18-bitbussize,18bitsofmailbox
dataappearon A18-A35. (Inthiscase,A0-A17areindeterminate.) Fora9-
bitbussize,9bitsofmailboxdataappearonA18-A26.(Inthiscase,A0-A17
andA27-A35areindeterminate.)
Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister.TheEndianSelectfeaturehasnoeffect
onmailboxdata.
BUS-MATCHING FIFO2 WRITES
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers.TheCLKCrisingedgethatwritesthefourthbyteorthesecondword
oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.
The bytes are arranged in the manner shown in Figure 3.
WhenwritingdatatoFIFO2inbyteformat,theunusedC9-C17inputsare
don'tcareinputs.
16
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26
A18
A8
A0
A35
A27
A17
A9
BYTE ORDER ON PORT A:
D
A
B
C
Write to FIFO1
B17
B9
B8
B0
BYTE ORDER ON PORT B:
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
L
A
B
B17
B9
B8
B0
C
D
(b) WORD SIZE BIG ENDIAN
B17
B9
B8
B8
B0
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
L
SIZEB
L
C
D
B17
B9
A
B
(c) WORD SIZE LITTLE ENDIAN
B17
B17
B17
B17
B9
B9
B9
B9
B8
B0
B0
B0
1st: Read from FIFO1
2nd: Read from FIFO1
BE
H
SIZEB
H
A
B8
B
B8
3rd: Read from FIFO1
4th: Read from FIFO1
C
B8
B0
D
(d) BYTE SIZE BIG ENDIAN
B17
B9
B8
B0
B0
B0
BE SIZEB
1st: Read from FIFO1
2nd: Read from FIFO1
D
L
H
B17
B9
B8
C
B17
B9
B9
B8
B
3rd: Read from FIFO1
B17
B8
B0
A
4th: Read from FIFO1
4665 drw 03
(e) BYTE SIZE LITTLE ENDIAN
Figure 2. Port B Bus Sizing
17
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
A26
A18
A8
A0
A35
A27
A17
A9
BYTE ORDER ON PORT A:
D
A
B
C
Read from FIFO2
C17
C9
C9
C8
C0
C0
BYTE ORDER ON PORT C:
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
L
A
B
C17
C8
C
D
(b) WORD SIZE BIG ENDIAN
C17
C9
C8
C0
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
L
SIZEC
L
C
D
C17
C9
C8
A
B
(c) WORD SIZE LITTLE ENDIAN
C17
C9
C9
C9
C9
C8
C8
C8
C8
C0
1st: Write to FIFO2
2nd: Write to FIFO2
BE
H
SIZEC
H
A
C17
C17
C17
C0
B
C0
C0
3rd: Write to FIFO2
4th: Write to FIFO2
C
D
(d) BYTE SIZE BIG ENDIAN
C17
C17
C17
C17
C9
C9
C9
C9
C8
C0
BE SIZEC
1st: Write to FIFO2
2nd: Write to FIFO2
D
L
H
C8
C8
C0
C0
C
B
3rd: Write to FIFO2
C8
C0
A
4th: Write to FIFO2
4665 drw 04
(e) BYTE SIZE LITTLE ENDIAN
Figure 3. Port C Bus Sizing
18
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
1
2
tRSTH
t
RSTS
MRS1
tBEH
t
BES
tFWS
BE/FWFT
BE
0,1
FWFT
t
FSS
tFSH
FS2,FS1
,FS0
t
WFF
t
WFF
FFA/IRA
(2)
REF
t
EFB/ORB
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
RTM
LOW
HIGH
4665 drw 05
LOOP
NOTES:
1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)
1
2
CLKC
CLKA
tRSTH
t
RSTS
MRS2(3)
t
BES
tBEH
tFWS
BE/FWFT
BE
0,1
FWFT
t
FSS
t
FSH
FS2,FS1
,FS0
t
WFF
t
WFF
FFC/IRC
EFA/ORA
AEA
(2)
REF
t
t
RSF
t
t
RSF
RSF
AFC
MBF2
RTM
LOW
HIGH
4665 drw06
LOOP
NOTES:
1. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
3. MRS2 must toggle simultaneously with MRS1.
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)
19
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
tRSTH
t
RSTS
PRS1
t
WFF
t
WFF
FFA/IRA
(2)
REF
t
EFB/ORB
AEB
t
RSF
t
RSF
AFA
t
RSF
MBF1
RTM
LOW
4665 drw 07
NOTES:
1. MRS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 6. FIFO1 Partial Reset (IDT Standard and FWFT Modes)
CLKC
CLKA
t
RSTS
tRSTH
PRS2
t
WFF
t
WFF
FFC/IRC
(2)
REF
t
EFA/ORA
t
RSF
AEA
t
RSF
AFC
t
RSF
MBF1
4665 drw 08
NOTES:
1. MRS2 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
Figure 7. FIFO2 Partial Reset (IDT Standard and FWFT Modes)
20
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
4
MRS1,
MRS2
t
FSS
t
t
FSH
FSH
FS2
t
FSS
0,0
FS1,FS0
t
WFF
FFA/IRA
(1)
tSKEW1
tENS2
tENH
ENA
tDH
tDS
A0-A35
First Word to FIFO1
AEA Offset
AFA Offset
AEB Offset
AFC Offset
(Y2)
(X2)
(Y1)
(X1)
CLKC
1
2
t
WFF
FFC/IRC
4665 drw09
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
t
FSH
t
FSS
FS2
t
WFF
(1)
SKEW
t
FFA/IRA
FS1/SEN
FS0/SD(3)
t
SENS
t
SENH
t
FSS
t
SENS
tSENH
tSPH
tSDS
t
SDH
tSDS
tSDH
AFA Offset
(Y1) MSB
AEA Offset
(X2) LSB
CLKC
4
t
WFF
4665 drw 10
FFC/IRC
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
21
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA HIGH
t
ENH
ENH
t
ENS1
CSA
t
t
ENS1
W/RA
tENH
tENS2
MBA
ENA
tENH
tENH
tENH
tENS2
tENS2
tENS2
tDH
t
DS
W1(1)
W2(1)
A0-A35
No Operation
4665 drw11
NOTE:
1. Written to FIFO1.
Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKC
FFC/IRC
HIGH
t
ENS2
ENS2
t
ENS2
ENS2
t
ENH
t
ENH
MBC
t
t
t
ENH
tENH
WENC
tDH
tDS
C0-C17
4665 drw12
DATA SIZE TABLE FOR WORD WRITES TO FIFO2
(1)
SIZE MODE
WRITE
NO.
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
SIZEC
BE
C17-C9
C8-C0
A35-A27
A26-A18
A17-A9
A8-A0
L
L
H
1
2
A
C
B
D
A
B
C
D
L
1
2
C
A
D
B
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 11. Port C Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
22
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
FFC/IRC HIGH
t
ENS2
ENS2
t
ENH
ENH
t
ENH
MBC
tENS2
t
t
t
ENH
WENC
tDS
tDH
C0-C8
4665 drw 13
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2
SIZE MODE(1)
WRITE
NO.
DATA WRITTEN
TO FIFO2
C8-C0
DATA READ FROM FIFO2
SIZEC
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
A
B
C
D
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 12. Port C Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
CLKB
EFB/ORB HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
Read 2
t
DIS
DIS
t
A
t
MDV
t
A
t
EN
B0-B17
Read 1
Read 2
Previous Data
(Standard Mode)
OR
t
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
4665 drw 14
DATA SIZE TABLE FOR WORD READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
B
H
H
H
A
B
C
D
1
2
1
2
A
C
C
A
D
L
A
B
C
D
D
B
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 13. Port B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
23
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
EFB/ORB
HIGH
CSB
MBB
tENS2
tENH
RENB
No Operation
t
DIS
DIS
t
MDV
t
A
t
A
t
A
tA
t
EN
B0-B8
Previous Data
Read 2
Read 3
Read 4
Read 5
Read 1
(Standard Mode)
t
t
MDV
OR
tA
tA
t
A
t
A
t
EN
B0-B8
Read 1
Read 2
Read 3
Read 4
(FWFT Mode)
4665 drw 15
NOTE:
1. Unused bytes B9-B17 are indeterminate for byte-size reads.
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO1
B8-B0
SIZEB
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB must be static throughout device operation.
Figure 14. Port B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA
HIGH
CSA
W/RA
MBA
tENS2
tENS2
tENH
tENH
tENH
tENS2
ENA
No Operation
W2(1)
t
MDV
tDIS
t
A
tA
t
EN
A0-A35
Previous Data
W1(1)
W2(1)
(
Standard Mode)
tDIS
t
MDV
OR
tA
t
A
t
EN
A0-A35
(FWFT Mode)
W3(1)
W1(1)
4665 drw16
NOTE:
1. Read From FIFO2.
Figure 15. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
24
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
WRA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDS
tDH
W1
A0-A35
CLKHt
CLKtCLKL
(1)
SKEW1
t
t
CLKB
3
1
2
t
REF
t
REF
FIFO1 Empty
LOW
ORB
CSB
MBB LOW
tENS2
tENH
RENB
tA
tA
Read 1
Read 2
B0-B17
4665 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 16. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
25
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
tCLKL
CLKA
LOW
HIGH
CSA
WRA
tENH
tENS2
MBA
tENS2
tENH
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
CLKHtCLK
tCLKL
(1)
SKEW1
t
t
CLKB
1
2
t
REF
t
REF
EFB
CSB
FIFO1 Empty
LOW
MBB LOW
tENS2
tENH
RENB
B0-B17
NOTES:
tA
tA
Read 1
Read 2
4665 drw18
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 17. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
26
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
CLKH
tCLKL
t
CLKC
MBC
tENS2
tENH
tENS2
tENH
WENC
IRC
HIGH
tDH
tDS
tDH
tDS
Write 1
Write 2
C0-C17
t
CLK
(1)
SKEW1
t
CLKH
tCLKL
t
CLKA
1
2
3
t
REF
t
REF
ORA FIFO2 Empty
CSA LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
A0-A35
W1
4665 drw19
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA
cycles. If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur
one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
27
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
CLKH
tCLKL
t
CLKC
tENS2
tENH
MBC
tENS2
tENH
WENC
FFC
HIGH
tDS
tDH
t
DS
tDH
Write 1
Write 2
C0-C17
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
t
REF
t
REF
EFA
CSA
FIFO2 Empty
LOW
LOW
LOW
W/RA
MBA
tENS2
tENH
ENA
tA
A0-A35
W1
4665 drw20
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
28
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB LOW
LOW
MBB
tENS2
tENH
RENB
ORB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
CLK tCLKL
tCLKH
CLKA
IRA
1
2
t
WFF
t
WFF
FIFO1 Full
CSA LOW
W/RA HIGH
tENS2
tENH
MBA
tENH
tENS2
ENA
tDS
tDH
Write
A0-A35
4665 drw21
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
29
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
MBB
tENS2
tENH
RENB
EFB
HIGH
tA
tA
Read 1
Read 2
B0-B17
Previous Word in
FIFO1 Output Register
(1)
tSKEW1
t
t
CLKH CLK tCLKL
CLKA
1
2
t
WFF
t
WFF
FFA
FIFO1 Full
CSA LOW
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
Write
A0-A35
4665 drw22
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively (the word-size case is shown).
Figure 21. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
30
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
W/RA
LOW
MBA
tENS2
tENH
ENA
ORA
HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0-A35
(1)
tCLK
t
tCLKH
tCLKL
CLKC
1
2
t
WFF
t
WFF
IRC FIFO2 Full
tENS2
tENH
MBC
WENC
C0-C17
t
ENS2
t
ENH
tDS
tDS
tDH
tDH
Write
4665 drw23
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
31
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
LOW
LOW
W/RA
MBA
ENA
tENS2
tENH
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
tSKEW1
Next Word From FIFO2
A0-A35
(1)
tCLK
tCLKH
tCLKL
CLKC
1
2
tWFF
tWFF
FIFO2 Full
FFC
tENS2
tENH
MBC
ENC
tENS2
tDS
tENH
tDH
tDS
tDH
Write
C0-C17
4665 drw24
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 23. FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENH
tENS2
ENA
(1)
tSKEW2
CLKB
1
2
t
PAE
t
PAE
AEB
X1 Word in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
RENB
4665 drw 25
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 24. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
32
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKC
tENH
tENS2
WENC
CLKA
(1)
tSKEW2
1
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
4665 drw 26
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
tPAF
(D-Y1) Words in FIFO1
ENH
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
t
tENS2
RENB
4665 drw 27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKC
tENH
tENS2
WENC
AFC
t
PAF
t
PAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
4665 drw 28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
33
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
tENS1
tENH
CSA
W/RA
MBA
ENA
t
ENS1
t
ENH
tENS2
t
ENH
ENH
t
ENS2
t
tDH
t
DS
W1
A0-A35
CLKB
MBF1
t
PMF
t
PMF
CSB
MBB
tENH
tENS2
RENB
t
PMR
tDIS
tEN
t
MDV
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
B0-B17
NOTE:
4665 drw29
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port
B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will
be indeterminate).
Figure 28. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
CLKC
tENS2
tENS2
tENH
tENH
tDH
MBC
ENC
tDS
C0-C17
CLKA
W1
tPMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
tPMR
tEN
tDIS
tMDV
A0-A35
W1 (Remains valid in Mail2 Register after read)
FIFO2 Output Register
4665 drw30
NOTE:
1. IfPortCis configuredforwordsize, data canbe writtentothe Mail2registerusingC0-C17. Inthis firstcase, A18-A35willhave validdata (A0-A17willbe indeterminate). IfPortCis configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
Figure 29. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
34
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
tENS2
tENH
RENB
RT1
t
RSTS
t
RSTH
t
RTMS
t
RTMH
RTM
EFB
(2)
REF
(2)
REF
t
t
tA
B0-Bn
Wx
W1
4665 drw31
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.
Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)
CLKC
CLKA
4
1
2
3
2
3
4
1
tENS2
tENH
ENA
RT2
t
RSTS
tRSTH
t
RTMH
t
RTMS
RTM
EFA
(2)
REF
(2)
REF
t
t
tA
A0-An
Wx
W1
4665 drw32
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.
Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)
35
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
RENB
RT1
LOW
t
RSTS
t
RSTH
t
RTMS
t
RTMH
RTM
ORB
(2)
REF
(2)
REF
t
t
tA
B0-Bn
Wx
W1
4665 drw33
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.
Figure 32. Retransmit Timing for FIFO1 (FWFT Mode)
CLKC
CLKA
4
1
2
3
2
3
4
1
ENA
RT2
LOW
RSTS
t
tRSTH
t
RTMS
t
RTMH
RTM
ORA
(2)
REF
(2)
REF
t
t
tA
A0-An
Wx
W1
4665 drw34
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRC will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.
Figure 33. Retransmit Timing for FIFO2 (FWFT Mode)
36
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
ENA
t
ENS2
tENS2
t
ENH
tENH
t
ENH
t
ENS2
No Operation
Wn+1
t
MDV
tDIS
t
A
tA
tEN
Wn(1)
Write to FIFO 1
Wn-1(1)
A0-A35
4665 drw35
Write to FIFO 1
NOTES:
1. Data is read from FIFO2 and written into FIFO1 & placed on Port A simultaneously. The first data word written into FIFO1 is the Previous Data Word (Wn-1)
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
Figure 34. Loopback Operation (FIFO2 data transfer to FIFO1 and Port A)
tCLK
tCLKH
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
ENA
t
ENS2
t
ENS2
t
ENH
tENH
t
ENH
t
ENS2
No Operation
Wn+1
t
MDV
tDIS
t
A
tA
tEN
(4) WRITE
to FIFO 1
Wn(1)
Write to FIFO 1
Wn-1(1)
Write to FIFO 1
A0-A35
HIGH-Z
4665 drw36
NOTES:
1. Data is read from FIFO2 and written into FIFO1 only. The data from FIFO2 is NOT placed on Port A. Port A is held in the high impedance state.
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
4. Write operations to FIFO1 cannot be accessed via Port A.
Figure 35. Loopback Operation (FIFO2 data transfer to FIFO1)
37
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330Ω
From Output
Under Test
30 pF (1)
510Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
1.5V
Input
GND
1.5V
GND
3V
t
S
th
tW
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
1.5V
1.5V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
tPZL
GND
tPLZ
3V
3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
V
t
PHZ
OL
OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4665 drw 37
NOTE:
1. Includes probe and jig capacitance.
Figure 36. Load Circuit and Voltage Waveforms
38
ORDERING INFORMATION
IDT
XXXXXX
X
XX
XX
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
PF
Commercial (0°C to +70°C)
Thin Quad Flat Pack (TQFP, PK128-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3656
72V3666
72V3676
2,048 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching
4,096 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching
8,192 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching
4665 drw38
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
06/14/2000
09/26/2000
12/22/2000
03/21/2001
11/03/2003
pgs. 1-3, 5, 6, 8-11, 13, 14, 16, 21, 22, 24-34, 37, and 39.
pgs. 7, 9, 10 and 39.
pgs. 5, 6, 13 and 22.
pgs. 7 and 8.
pg. 1.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
39
相关型号:
IDT72V3680L39268BBGI
FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
IDT
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