IDT72V3690L15PF9 [IDT]
FIFO, 32KX36, 10ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128;
| 型号： | IDT72V3690L15PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX36, 10ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128 先进先出芯片 |
| 文件： | 总46页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
IDT72V3640,IDT72V3650
IDT72V3660,IDT72V3670
IDT72V3680, IDT72V3690
• Zero latency retransmit
FEATURES:
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic
Ball Grid Array (PBGA) (with additional features)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Choose among the following memory organizations:Commercial
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
• Up to 166 MHz Operation of the Clocks
• UserselectableAsynchronous readand/orwriteports (PBGAOnly)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Pin to Pin compatible to the higher density of IDT72V36100 and
IDT72V36110
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
FUNCTIONALBLOCKDIAGRAM
*Available on the PBGA package only.
D0 -Dn (x36, x18 or x9)
LD SEN
WEN
WCLK/WR
*
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FLAG
LOGIC
WRITE CONTROL
LOGIC
ASYW
*
FWFT/SI
PFM
RAM ARRAY
FSEL0
FSEL1
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
RT
READ
CONTROL
LOGIC
RM
ASYR
BM
IW
OW
OUTPUT REGISTER
BUS
*
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK/RD
*
REN
TCK
*
*
TRST
JTAG CONTROL
(BOUNDARY SCAN)
*
TMS
TDI
TDO
4667 drw01
*
Q0 -Qn (x36, x18 or x9)
OE
*
*
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4667/12
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Bus-MatchingSyncFIFOsareparticularlyappropriatefornetwork,video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
bufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera36-bit, 18-bitora9-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are
exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories
withclockedreadandwritecontrolsandaflexibleBus-Matchingx36/x18/x9
dataflow.TheseFIFOs offerseveralkeyuserbenefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Asynchronous/Synchronous translationonthereadorwriteports
• Highdensityofferingsupto1Mbit
PIN CONFIGURATIONS
INDEX
WEN
SEN
DNC(1)
OE
1
2
3
4
102
VCC
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
VCC
DNC(1)
IW
D35
D34
D33
D32
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
VCC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
VCC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
VCC
VCC
Q15
Q14
Q13
Q12
VCC
GND
Q11
Q10
D12
GND
D11
4667 drw02a
TQFP (PK128-1, order code: PF)
TOP VIEW
NOTE:
1. DNC = Do Not Connect.
2
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR, tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
theWENinputshouldbetiedtoitsactivestate,(LOW).
oftheoneclockinputwithrespecttotheother.
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis Standard mode and First Word Fall Through (FWFT) mode.
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
is read from the FIFO on every rising edge of RCLK when REN is asserted. onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits willshiftthewordfrominternalmemorytothedataoutputlines.
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
theFIFOmustbeconfiguredforStandardIDTmode,andtheOEinputused tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
toprovidethree-statecontroloftheoutputs,Qn.
not have to be asserted for accessing the first word. However, subsequent
PINCONFIGURATIONS(CONTINUED)
A1 BALL PAD CORNER
A
ASYW
SEN
WEN
PAF
LD
HF
BM
EF
ASYR
BE
REN
OE
RT
WCLK
FF/IR
RCLK
IP
Q35
Q34
B
C
PRS
MRS
IW
FS0
FS1
PFM
PAE
D35
D32
D29
D34
D31
D28
D33
D30
D27
FWFT/SI
OW
VCC
VCC
RM
Q29
Q26
Q32
Q30
Q27
Q3
3
D
E
VCC
VCC
GND
GND
GND
GND
VCC
VCC
Q31
Q28
VCC
GND
GND
VCC
F
Q23
Q22
Q19
Q16
Q13
D26
D21
D18
D15
D12
D25
D22
D19
D16
D13
D11
D24
D23
D20
D17
D14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Q24
Q21
Q18
Q15
Q12
Q25
Q20
Q17
Q14
Q11
V
CC
VCC
G
VCC
VCC
H
J
VCC
VCC
V
CC
VCC
VCC
VCC
K
L
D3
D0
VCC
VCC
TDO
Q2
D1
TCK
D10
D9
1
D6
D7
3
D4
TMS
TRST
6
Q0
Q1
8
Q3
Q4
9
Q5
Q6
10
Q10
Q7
Q9
Q8
M
D5
D8
D2
TDI
2
4
5
7
11
12
4667 drw02b
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
3
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For serial programming, SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR*)
READ CLOCK (RCLK/RD*)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
(x36, x18, x9) DATA IN (D
0
- D
n
)
(x36, x18, x9) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
SERIAL CLOCK (SCLK)
EMPTY FLAG/OUTPUT READY (EF/OR)
SERIAL ENABLE(SEN)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4667 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 4 for Bus-Matching Byte Arrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymode is selected, thenD8, D17andD26are assumedtobe validbits
andD32,D33,D34andD35areignored. IPmodeisselectedduring Master
ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
writtentoandreadfromthe FIFO.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
BoundaryScanArchitecture.
If zero latency retransmit operation is selected, the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are
fabricatedusingIDT’shighspeedsubmicronCMOStechnology.
RefertoFigure11and12forRetransmitTimingwithnormallatency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
NOTE:
1. Pin status during Master Reset.
5
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (TQFP AND PBGA PACKAGES)
Symbol
Name
I/O
Description
(1)
BM
Bus-Matching
I
I
BMworkswithIWandOWtoselectthebussizesforbothwriteandreadports. SeeTable1forbussizeconfiguration.
(1)
BE
Big-Endian/
Little-Endian
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
selectLittle-Endianformat.
D0–D35
DataInputs
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
EF/OR
EmptyFlag/
OutputReady
O
IntheIDTStandardmode, the EFfunctionis selected. EF indicates whetherornotthe FIFOmemoryis empty.
InFWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
FF/IR
Full Flag/
Input Ready
O
Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis full. Inthe
FWFTmode,theIRfunctionisselected.IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFO
memory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. Thereareuptoeightpossiblesettings available.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
HF
IP(1)
Half-FullFlag
O
I
HF indicates whethertheFIFOmemoryis moreorless thanhalf-full.
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.A HIGHwillselectInterspersedParity
mode.InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnot
effectthedatawrittentoandreadfromtheFIFO.
InterspersedParity
(1)
IW
InputWidth
Load
I
I
This pin, alongwithOWandMB, selects the bus widthofthe write port. See Table 1forbus size configuration.
LD
Thisisadualpurposepin.DuringMasterReset,thestateoftheLD inputalongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
OE
OW
OutputEnable
OutputWidth
MasterReset
I
I
I
OEcontrolstheoutputimpedanceofQn.
This pin, alongwithIWandBM, selects the bus widthofthe readport. See Table 1forbus size configuration.
(1)
MRS
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringMasterReset,
theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
PAE
PAF
Programmable
Almost-EmptyFlag
O
O
I
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister. PAF goes LOWifthenumberoffreelocations intheFIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettingsareall
retained.
Q0–Q35
DataOutputs
O
I
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state.Outputsarenot5VtolerantregardlessofthestateofOE.
RCLK/
RD
ReadClock/
ReadStrobe
If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intotheoffsetregisters is outputonarisingedgeofRCLK.IfAsynchronous operationofthereadporthas been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operationofthe RCLK/RDinputis onlyavailable inthe PBGApackage.
REN
RM
ReadEnable
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
(1)
RetransmitTiming
Mode
RT
Retransmit
I
RT assertedontherisingedgeofRCLKinitializes theREADpointertozero,sets theEFflagtoLOW(OR toHIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
NOTE:
1. Inputs should not change state after Master Reset.
6
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES)
Symbol
Name
I/O
Description
SENenablesserialloadingofprogrammableflagoffsets.
If Synchronous operation of the write port has been selected, when enabled byWEN, the risingedge ofWCLK
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdataintotheFIFO
ona risingedge inanAsynchronous manner, (WEN shouldbe tiedtoits active state). Asynchronous operationof
theWCLK/WRinputisonlyavailableinthePBGApackage.
SEN
WCLK/
WR
SerialEnable
I
I
WriteClock/
WriteStrobe
WEN
VCC
WriteEnable
+3.3VSupply
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
These are VCC supply inputs and must be connected to the 3.3V supply rail.
NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (PBGA PACKAGE ONLY)
Symbol
Name
I/O
Description
ASYR(1)
Asynchronous
ReadPort
I
AHIGHonthis inputduringMasterResetwillselectSynchronous readoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ASYW(1)
Asynchronous
WritePort
I
I
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
(2)
TCK
JTAGClock
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
onthefallingedgeofTCK.IftheJTAGfunctionis notusedthis signalneeds tobetiedtoGND.
(2)
TDI
JTAGTestData
Input
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register.This outputis highimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(2)
JTAGModeSelect
JTAGReset
I
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomaticallyreset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controllerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAGfunctionisused
butthe userdoes notwanttouse TRST, thenTRST canbe tiedwithMRS toensure properFIFOoperation. Ifthe
JTAGfunctionisnotusedthenthissignalneedstobetiedtoGND.
NOTE:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 42-45 and Figures 31-33.
7
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
(2)
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
Symbol
Parameter
Min.
Typ.
Max. Unit
(1)
VCC
SupplyVoltageCom’l/Ind’l
SupplyVoltageCom’l/Ind’l
InputHighVoltageCom’l/Ind’l
InputLowVoltageCom’l/Ind’l
3.15
0
3.3
0
3.45
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND
(2)
VIH
2.0
—
0
—
—
—
5.5
0.8
70
V
DCOutputCurrent
mA
(3)
VIL
V
NOTES:
TA
TA
OperatingTemperature
Commercial
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Industrial
-40
—
85
°C
NOTES:
2. VCC terminal only.
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V3640L
IDT72V3650L
IDT72V3660L
IDT72V3670L
IDT72V3680L
IDT72V3690L
Commercial and Industrial(1)
tCLK = 6, 7.5, 10, 15 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
—
—
1
µ A
µA
V
(3)
ILO
10
—
0.4
40
15
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
V
ICC1(4,5,6)
ICC2(4,7)
mA
mA
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 4.2 + 1.4*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
8
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)—SYNCHRONOUSTIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
(2)
Commercial
Commercial
Commercial
TQFP Only
Com’l & Ind’l
TQFP Only
PBGA & TQFP
PBGA & TQFP
IDT72V3640L6
IDT72V3650L6
IDT72V3660L6
IDT72V3670L6
IDT72V3680L6
IDT72V3690L6
IDT72V3640L7-5 IDT72V3640L10 IDT72V3640L15
IDT72V3650L7-5 IDT72V3650L10 IDT72V3650L15
IDT72V3660L7-5 IDT72V3660L10 IDT72V3660L15
IDT72V3670L7-5 IDT72V3670L10 IDT72V3670L15
IDT72V3680L7-5 IDT72V3680L10 IDT72V3680L15
IDT72V3690L7-5 IDT72V3690L10 IDT72V3690L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
DataAccessTime(5)
Clock Cycle Time
Clock High Time
Clock Low Time
—
166
—
133.3
—
1(5)
100
—
66.7
MHz
tA
1
6
4
1(5)
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
1(5)
15
6
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
4
10
2.7
2.7
2
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
6
DataSetupTime
4
tDH
DataHoldTime
0.5
2
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
0.5
3
1
4
tLDH
tRS
LoadHoldTime
0.5
10
15
10
—
3
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
15
15
15
—
4
tRSS
tRSR
tRSF
tRTS
tOLZ
tOE
15
15
10
10
ResettoFlagandOutputTime
RetransmitSetupTime
—
3.5
0
—
3.5
0
—
—
6
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid(5)
0
0
1
1(5)
1(5)
—
—
—
—
—
—
—
5
1(5)
1(5)
—
—
—
—
—
—
—
7
1(5)
1(5)
—
—
—
—
—
—
—
9
(4,5)
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
OutputEnabletoOutputinHigh-Z
1
4
6
6
8
Write Clock to FF or IR
Read Clock to EF or OR
—
—
—
—
—
—
—
4
4
5
6.5
6.5
16
10
10
20
10
20
10
20
—
—
4
5
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
10
4
12.5
5
6.5
16
10
4
12.5
5
6.5
16
10
—
—
12.5
—
—
tSKEW1
tSKEW2
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
—
—
5
7
10
14
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns, the minimum for tA, tOE, and tOHZ is 2ns.
9
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)—ASYNCHRONOUSTIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
IDT72V3640L6
IDT72V3650L6
IDT72V3660L6
IDT72V3670L6
IDT72V3680L6
IDT72V3690L6
IDT72V3640L7-5
IDT72V3650L7-5
IDT72V3660L7-5
IDT72V3670L7-5
IDT72V3680L7-5
IDT72V3690L7-5
Symbol
Parameter
Cycle Frequency (Asynchronous mode)
DataAccessTime
Min.
—
0.6
10
Max.
Min.
—
0.6
12
Max.
83
Unit
MHz
ns
(4)
fA
100
8
(4)
tAA
10
(4)
tCYC
Cycle Time
—
—
—
—
8
—
—
—
—
10
ns
(4)
tCYH
Cycle HIGH Time
4.5
4.5
8
5
ns
(4)
tCYL
Cycle LOW Time
5
ns
(4)
tRPE
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
10
ns
(4)
tFFA
—
—
—
—
—
—
—
—
ns
(4)
tEFA
8
10
ns
(4)
tPAFA
8
10
ns
(4)
tPAEA
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
8
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Paramaeters apply to the PBGA package only.
10
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACTESTLOADS-6ns,7.5nsSpeedGrades
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
3ns(1)
InputRise/FallTimes
1.5V
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoadfortCLK =10ns,15ns
OutputLoadfortCLK =6ns,7.5ns
1.5V
1.5V
50
Ω
SeeFigure2a
See Figure 2b & 2c
Z0 = 50Ω
I/O
NOTE:
4667 drw04a
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
Figure 2b. AC Test Load
ACTESTLOADS-10ns,15nsSpeedGrades
6
5
4
3
2
1
3.3V
330Ω
D.U.T.
30pF*
510Ω
4667 drw04
20 30 50 80 100
Capacitance (pF)
200
4667 drw04b
Figure 2a. Output Load
* Includes jig and scope capacitances.
Figure 2c. Lumped Capacitive Load, Typical Derating
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
V
2
CC
Output
Normally
LOW
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
4667 drw04c
NOTE:
1. REN is HIGH.
11
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690sup-
porttwodifferenttimingmodesofoperation:IDTStandardmodeorFirstWord
Fall Through (FWFT) mode. The selection of which mode will operate is
determinedduringMasterReset,bythestateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe514thword
fortheIDT72V3640,1,026thwordfortheIDT72V3650,2,050thwordforthe
IDT72V3660, 4,098th word for the IDT72V3670, 8,194th word for the
IDT72V3680,16,386thwordfortheIDT72V3690,respectivelywaswritteninto
theFIFO. ContinuingtowritedataintotheFIFOwillcausethePAFtogoLOW.
Again,ifnoreadsareperformed, thePAFwillgoLOWafter(1,025-m)writes
fortheIDT72V3640, (2,049-m)writesfortheIDT72V3650,(4,097-m)writes
for the IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m)
writesfortheIDT72V3680and(32,769-m)writesfortheIDT72V3690,where
misthefulloffsetvalue. Thedefaultsettingforthesevaluesarestatedinthe
footnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
Dwrites tothe FIFO. D =1,025writes forthe IDT72V3640, 2,049writes for
the IDT72V3650, 4,097 writes for the IDT72V3660 and 8,193 writes for the
IDT72V3670,16,385 writes for the IDT72V3680 and 32,769 writes for the
IDT72V3690,respectively.NotethattheadditionalwordinFWFTmodeisdue
tothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the 513rdwordforIDT72V3640,1,025thwordforIDT72V3650,2,049thword
for IDT72V3660, 4,097th word for IDT72V3670, 8,193th word for the
IDT72V3680and16,385thwordfortheIDT72V3690,respectivelywaswritten
intotheFIFO. ContinuingtowritedataintotheFIFOwillcausetheProgrammable
Almost-Fullflag(PAF)togoLOW.Again,ifnoreadsareperformed, thePAF
willgoLOWafter(1,024-m)writesfortheIDT72V3640,(2,048-m)writesforthe
IDT72V3650,(4,096-m)writesfortheIDT72V3660,(8,192-m)writesforthe
IDT72V3670, (16,384-m)writes forthe IDT72V3680and(32,768-m)writes
fortheIDT72V3690. Theoffset“m”isthefulloffsetvalue.Thedefaultsetting
forthesevaluesarestatedinthefootnoteofTable2.Thisparameterisalsouser
programmable.SeesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 1,024 writes for the IDT72V3640, 2,048 writes for the
IDT72V3650,4,096writesfortheIDT72V3660,8,192writesfortheIDT72V3670,
16,384 writes for the IDT72V3680 and 32,768 writes for the IDT72V3690,
respectively.
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10,12,
and 14.
12
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
TABLE 2 — DEFAULT PROGRAMMABLE
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690haveinternalregisters for
theseoffsets.Thereareeightdefaultoffsetvalues selectableduringMaster
Reset. These offset values are shown in Table 2. Offset values can also be
programmedintotheFIFOinoneoftwoways;serialorparallelloadingmethod.
The selectionofthe loadingmethodis done usingtheLD (Load)pin. During
MasterReset,thestateoftheLDinputdetermineswhetherserialorparallelflag
offsetprogrammingisenabled. AHIGHonLDduringMasterResetselectsserial
loading of offset values. A LOW on LD during Master Reset selects parallel
loadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
FLAG OFFSETS
IDT72V3640, 72V3650
LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Offsets n,m
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
511
255
127
63
31
15
7
3
LD
FSEL1
FSEL0
Program Mode
(3)
H
X
X
Serial
(4)
L
X
X
Parallel
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
selected. Validprogrammingranges are from0toD-1.
IDT72V3660, 72V3670, 72V3680, 72V3690
LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
L
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 can
be configured during the Master Reset cycle with either synchronous or
asynchronous timing for PAF and PAE flags by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK. Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure17forsynchronous
PAF timingandFigure18forsynchronous PAEtiming.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
19forasynchronousPAFtimingandFigure20forasynchronousPAEtiming.
L
H
H
L
H
H
H
31
15
7
H
LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
Parallel
(4)
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
13
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
HF
IDT72V3640
IDT72V3660
FF PAF
PAE EF
IDT72V3650
L
L
0
H
H
H
H
H
L
0
0
1 to n(1)
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
L
H
H
H
H
H
H
(n+1) to 512
H
(n+1) to 1,024
(n+1) to 2,048
H
H
L
H
L
H
H
H
H
H
H
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,024
1,025 to (2,048-(m+1))
(2,048-m) to 2,047
2,048
2,049 to (4,096-(m+1))
(4,096m) to 4,095
4,096
L
L
L
HF
IDT72V3670
IDT72V3690
FF PAF
PAE EF
IDT72V3680
L
L
0
H
H
H
H
H
L
0
0
1 to n(1)
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
L
H
H
H
H
H
H
(n+1) to 4,096
H
(n+1) to 8,192
(n+1) to 16,384
H
H
L
H
L
H
H
H
H
H
H
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
L
to 16,383
to 32,767
(16,384-m)
(32,768-m)
L
L
16,384
32,768
NOTE:
1. See table 2 for values for n, m.
TABLE 4 STATUS FLAGS FOR FWFT MODE
IDT72V3640
IDT72V3650
IDT72V3660
HF
IR PAF
PAE OR
0
0
0
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
Number of
Words in
FIFO
1 to n+1
1 to n+1
1 to n+1
(n+2) to 513
(n+2) to 1,025
(n+2) to 2,049
H
H
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,025
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
2,050 to (4,097-(m+1))
(4,097m) to 4,096
4,097
L
L
H
H
L
L
L
L
HF
PAE OR
IDT72V3670
IDT72V3690
IR PAF
IDT72V3680
0
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
0
0
Number of
Words in
FIFO
1 to n+1
1 to n+1
1 to n+1
(n+2) to 4,097
H
H
(n+2) to 8,193
(n+2) to 16,385
4,098 to (8,193(m+1))
(8,194-m) to 8,192
8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,769
L
L
H
H
L
L
L
L
4667 drw05
NOTE:
1. See table 2 for values for n, m.
14
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
WCLK RCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
Full Offset (MSB)
Serial shift into registers:
X
20 bits for the 72V3640
22 bits for the 72V3650
24 bits for the 72V3660
26 bits for the 72V3670
28 bits for the 72V3680
30 bits for the 72V3690
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
1
No Operation
Write Memory
1
1
1
0
X
1
X
0
1
X
X
X
X
X
Read Memory
No Operation
X
4667 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
15
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
# of Bits Used:
1
1
17 16 15 14 13 12 11 10 9
16 15 14 13 1211 10 9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
Interspersed
Parity
17
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
Note: All unused bits of the
LSB & MSB are don't care
17 16 15 14 13 12 11 10 9
15 14 13 12 11 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Interspersed
Parity
17
9
16
# of Bits Used
IDT72V3640/50/60/70/80/90 x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
1st Parallel Offset Write/Read Cycle
D/Q17
8
7
6
5
4
3
2
10
2
1
Data Inputs/Outputs
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
16 15 14 13 1211 10
13 12 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2nd Parallel Offset Write/Read Cycle
D/Q8
16
Interspersed
Parity
15 14
11
9
D/Q0
9
D/Q8
# of Bits Used
EMPTY OFFSET REGISTER (PAE)
15 13
16
14
12
11
2nd Parallel Offset Write/Read Cycle
D/Q17
3rd Parallel Offset Write/Read Cycle
D/Q8
Data Inputs/Outputs
D/Q16
D/Q0
D/Q0
1
FULL OFFSET REGISTER (PAF)
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14
12 11
13
10
9
9
8
7
7
6
6
5
5
4
4
3
2
2
1
1
8
7
6
5
4
3
16 15
14 13 12 11 10
8
3
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
FULL OFFSET REGISTER (PAF)
15 14 13 12 11
10
IDT72V3640/50/60/70/80/90 x9 Bus Width
IDT72V3640/50/60/70/80/90 x18 Bus Width
4667 drw07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
16
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
Write operations to the FIFO are allowed before and during the parallel
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
programmingofPAEandPAFvaluescanbeachievedbyusingacombination nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
oftheLD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
as follows: whenLD andSEN aresetLOW,dataontheSIinputarewritten, memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
withtheFullOffsetMSB. Atotalof20bitsfortheIDT72V3640,22bitsforthe LD, parallel programming can also be interrupted by setting LD LOW and
IDT72V3650,24bitsfortheIDT72V3660,26bitsfortheIDT72V3670,28bits togglingWEN.
for the IDT72V3680 and 30 bits for the IDT72V3690. See Figure 15, Serial
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
LoadingofProgrammableFlagRegisters,forthetimingdiagramforthismode. during the programming process. From the time parallel programming has
Using the serial method, individual registers cannot be programmed begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
selectively. PAEandPAFcanshowavalidstatusonlyafterthecompleteset wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
of bits (for all offset registers) has been entered. The registers can be therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
RCLK edges plus tPAE plus tSKEW2.
Write operations to the FIFO are allowed before and during the serial
The act of reading the offset registers employs a dedicated read offset
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoes registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
nothavetooccuratonce. AselectnumberofbitscanbewrittentotheSIinput pinswhenLDissetLOWandRENissetLOW.Forx36outputbuswidth,data
andthen,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemory are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN transitionofRCLK.UponthesecondLOW-to-HIGHtransitionofRCLK,dataare
restoredtoaLOW,thenextoffsetbitinsequenceiswrittentotheregistersvia readfromtheFullOffsetRegister.ThethirdtransitionofRCLKreads,onceagain,
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset fromtheEmptyOffsetRegister.Forx18outputbuswidth,atotaloffourread
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. OnceLD cyclesarerequiredtoobtainthevaluesoftheoffsetregisters.Startingwiththe
andSENarebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues. EmptyOffsetRegisterLSBandfinishingwiththeFullOffsetRegisterMSB.For
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag x9outputbuswidth,atotalofsixreadcyclesmustbeperformedontheoffset
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen registers.SeeFigure3,ProgrammableFlagOffsetProgrammingSequence.
written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria; SeeFigure17, ParallelReadofProgrammableFlagRegisters,forthetiming
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid diagramforthismode.
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
PARALLELMODE
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
programmingofPAEandPAFvaluescanbeachievedbyusingacombination the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
Parallelreadingofthe offsetregisters is always permittedregardless of
proceedsasfollows: LDandWENmustbesetLOW.Forx36bitinputbuswidth, whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
dataontheinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-
to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of RETRANSMITOPERATION
WCLK,dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLK
The Retransmit operation allows data that has already been read to be
writes,onceagain,totheEmptyOffsetRegister. Forx18bitinputbuswidth, accessedagain. Thereare2modesofRetransmitoperation,normallatency
dataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSBonthefirst andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
LOW-to-HIGHtransitionofWCLK.Uponthe2ndLOW-to-HIGHtransitionof that resets the read pointer to the first location of memory, then the actual
WCLKdataarewrittenintotheEmptyOffsetRegisterMSB.Thethirdtransition retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
ofWCLKwritestotheFullOffsetRegisterLSB,thefourthtransitionofWCLKthen beginningofmemory.
writestotheFullOffsetRegisterMSB.ThefifthtransitionofWCLKwritesonce
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
againtotheEmptyOffsetRegisterLSB. Atotaloffourwritestotheoffsetregisters REN andWEN mustbe HIGHbefore bringingRT LOW. Whenzerolatency
isrequiredtoloadvaluesusingax18inputbuswidth.Foraninputbuswidth is utilized,RENdoes notneedtobeHIGHbeforebringingRTLOW. Atleast
ofx9bits,atotalofsixwritecyclestotheoffsetregistersisrequiredtoloadvalues. twowords,butnomorethanD-2wordsshouldhavebeenwrittenintotheFIFO,
See Figure 3, Programmable Flag Offset Programming Sequence. See and read from the FIFO, between Reset (Master or Partial) and the time of
Figure 16, Parallel Loading of Programmable Flag Registers, for the timing Retransmitsetup. D =1,024fortheIDT72V3640,2,048fortheIDT72V3650,
diagramforthismode.
4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister IDT72V3680and32,768forthe IDT72V3690. InFWFTmode, D=1,025for
pointer. The act of reading offsets employs a dedicated read offset register theIDT72V2640,2,049fortheIDT72V3650,4,097fortheIDT72V3660,8,193
pointer.Thetwopointersoperateindependently;however,areadandawrite fortheIDT72V3670,16,385fortheIDT72V3680and32,769fortheIDT72V3690.
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
noeffectonthepositionofthesepointers.
17
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode thePAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup thatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
is setup will update PAF. RT is synchronized to RCLK.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
TheRetransmitfunctionhastheoptionoftwomodesofoperation,either
setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set “normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
tothefirstlocationoftheRAMarray. previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the latency”retransmitoperation.Zerolatencybasicallymeansthatthefirstdata
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected, wordtoberetransmitted,isplacedontotheoutputregisterwithrespecttothe
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading RCLKpulsethatinitiatedtheretransmit.
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
18
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ASYNCHRONOUS READ (ASYR)
SIGNALDESCRIPTION
INPUTS:
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
Asynchronousoperationofthereadportwillbeselected.DuringAsynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronous readstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
DATA IN (D0 - Dn)
Datainputsfor36-bitwidedata(D0-D35),datainputsfor18-bitwidedata
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS:
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures25,26,27and28forrelevanttimingand
operationalwaveforms.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessedagain. Thereare2modesofRetransmitoperation,normallatency
andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
REN andWEN mustbe HIGHbefore bringingRT LOW. Whenzerolatency
is utilized, REN does not need to be HIGH before bringing RT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 5, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET ( PRS )
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW. IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 6, PartialResetTiming, forthe relevanttimingdiagram.
ASYNCHRONOUS WRITE (ASYW)
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchronous
operation of the write port the WCLK input becomes WR input, this is the
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
basedinbothawriteoperationandreadoperation.Note,ifAsynchronousmode
is selected, FWFTis notpermissable. RefertoFigures 23, 24, 27and28for
relevanttimingandoperationalwaveforms.
In Retransmit operation, zero latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset. Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
Thisisadualpurposepin.DuringMasterReset,thestateoftheFWFT/SI
inputdetermineswhetherthedevicewilloperateinIDTStandardmodeorFirst
Word Fall Through (FWFT) mode.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
19
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag whenever there is a rising edge on RD. In this mode the REN input must be
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace tiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthethree-
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including stateQnoutputs.
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe READ ENABLE ( REN )
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate register on the rising edge of every RCLK cycle if the device is not empty.
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
rising edges, REN = LOW is not necessary. Subsequent words must be maintainthepreviousdatavalue.
accessed using the Read Enable (REN) and RCLK.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset. furtherreadoperations. RENisignoredwhentheFIFOisempty.Onceawrite
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
StandardandFWFTmodes.
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
inputbehavesasWCLK. allotherwords,areadmustbeexecutedusingREN. TheRCLKLOW-to-HIGH
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ operations. REN is ignored when the FIFO is empty.
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
updating HF flag to LOW). The Write and Read Clocks can either be mustbeheldactive,(tiedLOW).
independentorcoincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). SERIAL ENABLE ( SEN )
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK.
WRITE ENABLE ( WEN )
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
When SEN is HIGH, the programmable registers retains the previous
settings andnooffsets areloaded. SEN functions thesamewayinbothIDT
StandardandFWFTmodes.
OUTPUT ENABLE ( OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
mustbeheldactive,(tiedLOW).
LOAD ( LD )
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD
enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
orparallelloadorreadofthese offsetvalues.
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
the HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
BUS-MATCHING (BM, IW, OW)
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure4forBus-
MatchingByteArrangement.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
20
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
During Master Reset, a LOW on BE will select Big-Endian operation. A countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x36to assert FF in IDT Standard mode.
x18,x36tox9,x18tox36andx9tox36.IfBig-Endianmodeisselected,then
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead doubleregister-bufferedoutputs.
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO EMPTY FLAG ( EF/OR )
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis
configured during master reset by the state of the Big-Endian (BE) pin. See functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
Figure 4 for Bus-Matching Byte Arrangement.
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
flagtimingmode.IfasynchronousPAF/PAEconfigurationisselected(PFM, theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
LOWduringMRS),thePAEisassertedLOWontheLOW-to-HIGHtransition thelastwordfromtheFIFOmemorytotheoutputs. OR goesHIGHonlywith
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
PAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
LOWagain.SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming
If synchronous PAE/PAF configuration is selected (PFM, HIGH during information.
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EFis a double register-bufferedoutput. InFWFT
onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe mode,ORisatripleregister-bufferedoutput.
stateoftheProgrammableFlagMode(PFM)pin.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
INTERSPERSED PARITY (IP)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode. reaches the almost-full condition. In IDT Standard mode, if no reads are
A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
to select the parity bit in the word loaded into the parallel port (D0-Dn) when totheFIFO.ThePAFwillgoLOWafter(1,024-m)writesfortheIDT72V3640,
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe (2,048-m)writesfortheIDT72V3650,(4,096-m)writesfortheIDT72V3660,
FIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26and (8,192-m)writesfortheIDT72V3670,(16,384-m)writesfortheIDT72V3680
D35 duringthe parallelprogrammingofthe flagoffsets. IfNon-Interspersed and(32,768-m)writesfortheIDT72V3690.Theoffset“m”isthefulloffsetvalue.
Paritymodeisselected,thenD8,D17 andD28 areisassumedtobevalidbits ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
In FWFT mode, the PAF will go LOW after (1,025-m) writes for the
ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an IDT72V3640,(2,049-m)writesfortheIDT72V3650,(4,097-m)writesforthe
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata IDT72V3660and(8,193-m)writesfortheIDT72V3670,(16,385-m)writesfor
writtentoandreadfromthe FIFO.
the IDT72V3680and(32,769-m)writes forthe IDT72V3690, where mis the
fulloffsetvalue.Thedefaultsettingforthisvalueisstatedin Table2.
SeeFigure18,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
Figure20,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
Mode).
OUTPUTS:
FULL FLAG ( FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF isHIGH,theFIFOisnotfull. Ifnoreadsareperformed
after a reset (either MRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the
IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and
32,768 for the IDT72V3690. See Figure 7, Write Cycle andFullFlagTiming
(IDTStandardMode),fortherelevanttiminginformation.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
See Figure 19, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IRgoes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
totheFIFO(D = 1,025fortheIDT72V3640,2,049fortheIDT72V3650,4,097
fortheIDT72V3660,8,193fortheIDT72V3670,16,385fortheIDT72V3680
and32,769forthe IDT72V3690. See Figure 9, Write Timing(FWFTMode),
fortherelevanttiminginformation.
21
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH fortheIDT72V3670,16,384fortheIDT72V3680and32,768fortheIDT72V3690.
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT IDT72V3640,2,049fortheIDT72V3650,4,097fortheIDT72V3660,8,193for
Standard and FWFT Mode).
theIDT72V3670,16,385fortheIDT72V3680and32,769fortheIDT72V3690.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
HALF-FULL FLAG ( HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO WCLK,itisconsideredasynchronous.
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth DATAOUTPUTS(Q0-Qn)
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
(Q0-Q35)aredataoutputsfor36-bitwidedata,(Q0-Q17)aredataoutputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
22
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to FIFO
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
A
B
C
D
Read from FIFO
X
L
L
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
L
Q17-Q9
Q8-Q0
C
D
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
L
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
B
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
B
Q8-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Q35-Q27
Q35-Q27
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q17-Q9
Q17-Q9
Q8-Q0
BE BM IW
OW
H
D
1st: Read from FIFO
H
H
L
Q8-Q0
2nd: Read from FIFO
3rd: Read from FIFO
C
Q8-Q0
B
Q8-Q0
A
4th: Read from FIFO
4667 drw08
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement
23
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
1st: Write to FIFO
2nd: Write to FIFO
A
B
D35-D27
D26-D18
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
B
D
Read from FIFO
Read from FIFO
A
C
L
H
H
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to FIFO
2nd: Write to FIFO
D8-D0
B
D8-D0
3rd: Write to FIFO
4th: Write to FIFO
C
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
C
A
Read from FIFO
4667 drw09
D
B
H
H
H
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement (Continued)
24
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
REN
t
RSS
RSS
t
RSR
RSR
t
t
WEN
tRSR
tRSS
FWFT/SI
t
RSS
RSS
tRSR
LD
t
ASYW,
ASYR
tRSS
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
BM,
OW, IW
BE
RM
PFM
tRSS
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4667 drw10
Figure 5. Master Reset Timing
25
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4667 drw11
Figure 6. Partial Reset Timing
26
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
FF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
4667 drw12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
t
OLZ
tOHZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENH
tENH
tENS
tENS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
4667 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
27
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
28
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
29
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
tREF
tREF
EF
PAE
HF
t
PAES
tHF
t
PAFS
PAF
4667 drw16
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
30
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
1
2
t
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENS
tRTS
REN
- Q
t
A
t
A
tA
A
(4)
(4)
(4)
Q0
n
Wx
Wx+1
W
2
W4
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
tREF
tREF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
4667 drw17
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
31
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
2
3
RCLK
t
ENS
tENH
REN
t
A
tA
t
A
t
A
t
A
(3)
(3)
W3
(3)
2
Q0 - Qn
W
4
W1
Wx
W
Wx+1
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
EF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
4667 drw18
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
32
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
4
1
2
5
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
t
A
tA
t
A
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W3
W1
W
2
W
4
W5
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
t
PAES
PAE
HF
tHF
t
PAFS
PAF
4667 drw19
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
tENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4667 drw20
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680 and X = 14 for the IDT72V3690.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
33
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
t
LDH
ENH
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0
- Dn
4667 drw21
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
t
LDH
ENH
LD
t
ENS
tENH
REN
t
A
t
A
DATA IN OUTPUT REGISTER
PAE OFFSET
PAF OFFSET
Q0 - Qn
4667 drw22
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
1
2
WCLK
WEN
PAF
2
1
tENS
tENH
t
PAFS
t
PAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
t
SKEW2(3)
RCLK
tENS
tENH
4667 drw23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768
for the IDT72V3690.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the
IDT72V3690.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
34
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
SKEW2(4)
t
t
PAES
PAES
t
1
2
1
2
RCLK
tENS
tENH
4667 drw24
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
4667 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768
for the IDT72V3690.
In FWFT Mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the
IDT72V3690.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
35
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
(2)
tPAEA
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4667 drw26
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
]
words in FIFO(2)
2
tHF
RCLK
tENS
REN
4667 drw27
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the
IDT72V3680 and 32,768 for the IDT72V3690.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680
and 32,769 for the IDT72V3690.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
36
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
tENH
tA
REN
Qn
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
WD
Dn
WD+1
4667 drw28
NOTE:
1. OE = LOW and WEN = LOW.
Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
REN
tA
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
4667 drw29
NOTE:
1. OE = LOW and WEN = LOW.
Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
37
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
No Write
1
WCLK
WEN
Dn
2
DF+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
4667 drw30
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
Qn
tCYH
tAA
Last Word in Output Register
W0
4667 drw31
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
38
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
4667 drw32
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
4667 drw33
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
39
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separatelyANDingFFofeveryFIFO. InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 29 demonstrates a width expansion using two IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690devices. D0-D35fromeach
device forma 72-bitwide inputbus andQ0-Q35 fromeachdevice forma 72-
bit wide output bus. Any word width can be attained by adding additional
IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
IDT
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
READ ENABLE (REN)
72V3640
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V3650
72V3660
OUTPUT ENABLE (OE)
72V3670
72V3680
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR)
72V3690
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FIFO
#1
FIFO
#2
m + n
n
Qm+1 - Qn
DATA OUT
m
4667 drw34
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72 and 32,768 x 72 Width Expansion
40
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
RCLK
IDT
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
WRITE ENABLE
INPUT READY
OR
WEN
REN
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4667 drw 35
Figure 30. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36 Depth Expansion
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V3640 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660,
8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the
IDT72V3690 with an 36-bit bus width. In FWFT mode, the FIFOs can be
connectedinseries(thedataoutputsofoneFIFOconnectedtothedatainputs
of the next) with no external logic necessary. The resulting configuration
providesatotaldepthequivalenttothesumofthedepthsassociatedwitheach
single FIFO. Figure 30 shows a depth expansion using two IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690devices.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
41
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tTCK
t
4
t
3
t
1
t
2
TCK
TDI/
TMS
tDS
tDH
TDO
TDO
t
6
tDO
4667 drw36
TRST
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t
5
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 31. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
SYSTEMINTERFACEPARAMETERS
Parameter
Symbol
Test
Conditions Min. Max. Units
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRise
tTCKFall
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
DataOutput
tDO = Max
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
42
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V3640/72V3650/
72V3660/72V3670/72V3680/72V3690incorporatesthenecessarytapcon-
trollerandmodifiedpadcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
4667 drw37
Figure 32. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
43
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
4667 drw38
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 33. TAP Controller State Diagram
UPDATE-DR
The shifting process has been completed. The data is latched into their
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
paralleloutputsinthisstatetobeaccessedthroughtheinternalbus.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetailsonTAPcontrollerreset.
EXIT1-DR / EXIT2-DR
Thisisatemporarycontrollerstate.IfTMSisheldhigh,arisingedgeapplied
toTCKwhileinthisstatecausesthecontrollertoentertheUpdate-DRstate.This
terminatesthescanningprocess.Alltestdataregistersselectedbythecurrent
instructionretaintheirpreviousstateunchanged.
CAPTURE-DR
Data is loaded from the parallel input pins or core outputs into the Data
Register.
PAUSE-DR
Thiscontrollerstateallowsshiftingofthetestdataregisterintheserialpath
betweenTDIandTDOtobetemporarilyhalted.Alltestdataregistersselected
bythecurrentinstructionretaintheirpreviousstateunchanged.
SHIFT-DR
Thepreviouslycaptureddataisshiftedinserially,LSBfirstattherisingedge
ofTCLKintheTDI/TDOpathandshiftedoutserially,LSBfirstatthefallingedge
ofTCLKtowardstheoutput.
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similartoDataregisters.Theseinstructionsoperateontheinstructionregisters.
44
IDT72V3640/50/60/70/80/903.3VHIGHDENSITYSUPERSYNCIITM 36-BITFIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
THE INSTRUCTION REGISTER
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
28 27
12 11
1 0(LSB)
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
1
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
IDT72V3640/50/60/70/80/90 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TESTDATAREGISTER
•
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Hex
Value
0x00
0x02
0x01
0x03
0x0F
Instruction
Function
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SAMPLE/PRELOAD SelectBoundaryScanRegister
HI-Z
BYPASS
TEST BYPASS REGISTER
JTAG
SelectBypassRegister
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
Table 6. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
EXTEST
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
The mandatoryEXTESTinstructionis providedforexternalcircuityand
boardlevelinterconnectioncheck.
IDCODE
THE DEVICE IDENTIFICATION REGISTER
ThisinstructionisprovidedtoselectDeviceIdentificationRegistertoread
outmanufacture’sidentity,partnumberandversionnumber.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
SAMPLE/PRELOAD
ThemandatorySAMPLE/PRELOADinstructionallowsdatavaluestobe
loadedontothelatchedparalleloutputsoftheboundary-scanshiftregisterprior
toselectionofthe boundary-scantestinstruction. The SAMPLEinstruction
allowsasnapshotofdataflowingfromthesystempinstotheon-chiplogicorvice
versa.
For the IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690,
thePartNumberfieldcontainsthefollowingvalues:
Device
Part# Field
04E5
04E4
04E3
04E2
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
HIGH-Z
Thisinstructionplacesalltheoutputpinsonthedeviceintoahighimpedance
state.
BYPASS
04E1
04E0
TheBypassinstructioncontainsasingleshift-registerstageandissetto
provideaminimum-lengthserialpathbetweentheTDIandtheTDOpinsofthe
device whennotestoperationofthe device is required.
45
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BB
Thin Plastic Quad Flatpack (TQFP, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1)
Commercial, PBGA & TQFP Only
Commercial, PBGA & TQFP Only
Commercial, TQFP Only
6
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
7-5
10
15
Com’l & Ind’l, TQFP Only
L
Low Power
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
4667 drw 39
NOTE:
1. Industrial temperature range is available by special order for speed grades faster than 15ns.
DATASHEETDOCUMENTHISTORY
05/25/2000
07/28/2000
12/14/2000
03/27/2001
04/06/2001
12/14/2001
12/20/2001
03/25/2002
04/19/2002
05/24/2002
01/20/2003
02/11/2003
07/15/2003
09/29/2003
pgs. 1, 6, 7, 8, 34, and 35.
pgs. 13, 14, and 34.
pgs. 6, 7, and 8.
pg. 7.
pgs. 4, 5, and 18.
pgs. 1-46.
pg. 9.
pg. 42.
pg. 3.
pgs. 3, and 11.
pgs. 1, 7, 9, 10, and 16.
pgs. 7, and 44.
pgs. 3, 19, and 37-39.
pg. 8.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
www.idt.com
46
相关型号：
IDT72V3690L6BB
FIFO, 32KX36, 4ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
IDT
IDT72V3690L6BBG
FIFO, 32KX36, 4ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
IDT
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