IDT72V3693L10PFG [IDT]
FIFO, 32KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128;
| 型号： | IDT72V3693L10PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片 |
| 文件： | 总30页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
16,384 x 36
32,768 x 36
65,536 x 36
IDT72V3683
IDT72V3693
IDT72V36103
• Big- or Little-Endian format for word and byte bus sizes
• Retransmit Capability
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
FEATURES
• Memory storage capacity:
IDT72V3683
IDT72V3693
IDT72V36103 – 65,536 x 36
–
–
16,384 x 36
32,768 x 36
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Clock frequencies up to 100 MHz (6.5 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643/72V3653/72V3663/72V3673
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
W/RA
Control
ENA
Logic
MBA
36
RAM ARRAY
36
36
FIFO1
Mail1,
Mail2,
Reset
Logic
16,384 x 36
32,768 x 36
65,536 x 36
RS1
RS2
PRS
36
RT
RTM
FIFO
Retransmit
Logic
Write
Pointer
Read
Pointer
A0-A35
B0-B35
Status Flag
Logic
EF/OR
AE
FF/IR
AF
36
36
FS2
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
Timing
Mode
FWFT
16
CLKB
CSB
W/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
SIZE
Mail 2
Register
4678 drw 01
MBF2
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFO isatrademarkofIntegratedDeviceTechnology,Inc.
COMMERICAL TEMPERATURE RANGE
NOVEMBER 2003
1
DSC-4678/3
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
datafromPortAtoPortB. FIFOdataonPortBcanoutputin36-bit,18-bit,or
9-bitformatswithachoiceofBig-orLittle-Endianconfigurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
each port are independent of one another and can be asynchronous or
DESCRIPTION
TheIDT72V3683/72V3693/72V36103aredesignedtorunoffa3.3Vsupply
forexceptionallylowpowerconsumption. Thesedevicesaremonolithic,high-
speed,low-power,CMOSunidirectionalSynchronous(clocked)FIFOmemory
whichsupportsclockfrequenciesupto100MHzandhasreadaccesstimesas
fastas6.5ns. The16,384/32,768/65,536x36dual-portSRAMFIFObuffers
PIN CONFIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
B25
B24
BM
A24
A23
BE/FWFT
GND
A22
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
4678 drw 02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
coincident. The enables for each port are arranged to provide a simple areselectedintheFirstWordFallThroughmode. IRindicateswhetherornot
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- theFIFOhasavailablememorylocations. ORshowswhethertheFIFOhas
nouscontrol.
data available for reading or not. It marks the presence of valid data on the
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox outputs.
registers. Themailboxregisters'widthmatchestheselectedPortBbuswidth.
Eachmailboxregisterhas a flag(MBF1 andMBF2)tosignalwhennewmail Almost-Fullflag(AF).AE indicateswhenaselectednumberofwordsremain
has beenstored.
TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogrammable
intheFIFOmemory. AFindicateswhentheFIFOcontainsmorethanaselected
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset. numberofwords.
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray
andselectsserialflagprogramming,parallelflagprogramming,oroneoffive intoitsarray. EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
possibledefaultflagoffsetsettings,8,16,64,256or1,024.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
readsdatafromitsarray. ProgrammableoffsetsforAEandAFareloaded in
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe parallelusingPortAorinserialviatheSDinput.Fivedefaultoffsetsettingsare
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e., alsoprovided. TheAEthresholdcanbesetat8,16, 64,256or1,024locations
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset fromtheemptyboundaryandtheAFthresholdcanbesetat8,16,64,256or
is useful since it permits flushing of the FIFO memory without changing any 1,024locationsfromthefullboundary. Allthesechoicesaremadeusingthe
configurationsettings.
FS0, FS1 and FS2 inputs during Reset.
TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfourclock
InterspersedParityisavailableandcanbeselectedduringaMasterReset
cycles of CLKA and CLKB, by taking the Retransmit pin, RT LOW while the oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming
RetransmitModepin,RTMisHIGH.WhenaRetransmitisperformedtheread oftheflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
pointerisresettothefirstmemorylocation.
Parityis selectedthendatalineA8willbecomeavalidbit.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,the
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths. In
firstwordwrittentoanemptyFIFOisdepositedintothememoryarray. Aread First Word Fall Through mode, more than one device may be connected in
operationisrequiredtoaccessthatword(alongwithallotherwordsresiding seriestocreategreaterworddepths. Theadditionofexternalcomponentsis
inmemory). IntheFirstWordFallThroughmode(FWFT),thefirstwordwritten unnecessary.
to an empty FIFO appears automatically on the outputs, no read operation
If, at any time, the FIFO is not actively performing a function, the chip will
required (Nevertheless, accessing subsequent words does necessitate a automatically power down. During the power down state, supply current
formalreadrequest). ThestateoftheBE/FWFTpinduringResetdetermines consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
themodeinuse.
inputs)willimmediatelytakethedeviceoutofthePowerDownstate.
TheIDT72V3683/72V3693/72V36103arecharacterizedforoperationfrom
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a
combinedFull/InputReadyFlag(FF/IR). TheEFandFFfunctionsareselected 0°Cto70°C. Industrialtemperature range (-40°Cto+85°C)is available by
inthe IDTStandardmode. EF indicates whetherornotthe FIFOmemoryis specialorder. TheyarefabricatedusingIDT’shighspeed,submicronCMOS
empty. FFshowswhetherthememoryisfullornot. TheIRandORfunctions technology.
3
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
PortAData
36-bitbidirectionaldataportforsideA.
Almost-EmptyFlag
(Port B)
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsin
theFIFOis less thanorequaltothevalueintheAlmost-EmptyBoffsetregister,X.
AF
Almost-FullFlag
(Port A)
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
locations intheFIFOis less thanorequaltothevalueintheAlmost-FullAoffsetregister,Y.
B0-B35
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
Inthis case, dependingonthe bus size, the mostsignificantbyte orwordwrittentoPortAis read
fromPortBfirst. ALOWonBEwillselectLittle-Endianoperation. Inthiscase,theleastsignificant
byteorwordwrittentoPortAisreadfromPortBfirst. AfterMasterReset,thispinselectsthetiming
mode. A HIGH onFWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Oncethetimingmodehasbeenselected,thelevelonFWFTmustbestaticthroughout
deviceoperation.
Fall Through
(1)
BM
Bus-MatchSelect
(Port B)
I
I
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endianarrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.
CLKA
CLKB
PortAClock
PortBClock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbe
asynchronous orcoincidenttoCLKA. EF/ORand AE are synchronizedtothe LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The
A0-A35outputs areinthehigh-impedancestatewhenCSAis HIGH.
CSB
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
The B0-B35outputs are inthe high-impedance state whenCSB is HIGH.
EF/OR
Empty/Output
Ready Flag
(Port B)
O
This is adualfunctionpin.IntheIDTStandardmode,theEFfunctionis selected. EFindicates
whetherornottheFIFOmemoryisempty. IntheFWFTmode,the ORfunctionisselected. ORindicates
thepresenceofvaliddataontheB0-B35outputs,availableforreading. EF/ORissynchronizedtothe
LOW-to-HIGHtransitionofCLKB.
ENA
ENB
FF/IR
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
Full/Input
Ready Flag
(Port A)
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FF functionis selected. FF indicates
whetherornotthe FIFOmemoryis full. Inthe FWFTmode, the IRfunctionis selected. IR
indicates whether or not there is space available for writing to the FIFO memory. FF/IRis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FS0/SD
FlagOffsetSelect0/
SerialData,
I
FS1/SEN andFS0/SDare dual-purpose inputs usedforflagoffsetregisterprogramming. During
Reset,FS1/SENandFS0/SD,togetherwithFS2selecttheflagoffsetprogrammingmethod.
Threeoffsetregisterprogrammingmethodsareavailable:automaticallyloadoneoffivepreset
values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.
FS1/SEN
FlagOffsetSelect1/
SerialEnable
I
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenable
synchronous totheLOW-to-HIGHtransitionofCLKA. WhenFS1/SEN is LOW,arisingedgeon
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
toprogramthe offsetregisters is 28forthe 72V3683, 30forthe 72V3693, and32forthe 72V36103.
ThefirstbitwritestorestheY-registerMSBandthelastbitwritestorestheX-registerLSB.
FS2(1)
FlagOffsetSelect2
MBA
MBB
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputand
aLOWlevelselectsFIFOdataforoutput.
4
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
MBF1
Name
I/O
Description
Mail1RegisterFlag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
followingeithera Reset(RS1)orPartialReset(PRS).
MBF2
Mail2RegisterFlag
Resets
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.
Writes tothe mail2 registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
followingeithera Reset(RS2)orPartialReset(PRS).
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransitiononRS1selectstheprogramming
method(serialorparallel)andoneoffiveprogrammableflag defaultoffsets. ItalsoconfiguresPort
Bforbus sizeandendianarrangement. FourLOW-to-HIGHtransitions ofCLKAandfourLOW-to-
HIGHtransitionsofCLKBmustoccurwhileRS1isLOW.
RS1, RS2
PRS/
RT
PartialReset/
Retransmit
I
ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM
pin.IfRTMisLOW,thenaLOWonthispininitializestheFIFOreadandwritepointerstothefirstlocation
ofmemoryandsets thePortBoutputregistertoallzeroes. DuringPartialReset, thecurrently
selectedbussize,endian arrangement,programmingmethod(serialorparallel),andprogrammable
flagsettingsareallretained.IfRTMisHIGH,thenaLOWonthispinperformsaRetransmitandinitializes
thereadpointeronly,tothefirstmemorylocation.
RTM
RetransmitMode
I
I
This pinis usedinconjunctionwiththe RT pin. WhenRTMis HIGHa Retransmitis performedwhen
RT is taken HIGH.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
andendianarrangementforPortB. The levelofSIZEmustbe staticthroughoutdevice operation.
(1)
SIZE
BusSizeSelect
(Port B)
W/RA
W/RB
NOTE:
PortAWrite/
ReadSelect
I
I
A HIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGH impedancestatewhenW/RAisHIGH.
PortBWrite/
ReadSelect
A LOWselects a write operationanda HIGHselects a readoperationonPortBfora LOW-to-HIGH
transitionofCLKB. The B0-B35outputs are inthe HIGHimpedance state whenW/RBis LOW.
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATING
CONDITIONS
Symbol
Parameter
SupplyVoltage
Min. Typ.
Max.
3.45
VCC+0.5
0.8
Unit
V
(1)
VCC
3.15 3.3
VIH
VIL
IOH
IOL
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
2
—
—
—
—
—
V
—
—
—
0
V
–4
mA
mA
°C
8
TA
70
NOTES:
1. Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3683
IDT72V3693
IDT72V36103
Commercial
tCLK = 10, 15 ns
(2)
Symbol
VOH
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
2.4
—
—
—
—
—
—
Typ.
—
—
—
—
—
4
Max.
—
0.5
±5
±5
5
Unit
V
VCC = 3.0V,
IOH = –4 mA
VOL
OutputLogic"0"Voltage
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
IOL = 8 mA
V
ILI
Input Leakage Current (Any Input)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
VI = VCC = 0.2V or 0v
VI = VCC - 0.2V or 0
f = 1 MHz
µA
µA
mA
mA
pF
pF
ILO
ICC2(3)
ICC3(3)
Standby Current (with CLKA and CLKB running)
Standby Current (no clocks running)
InputCapacitance
5
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant
4. Characterized values, not currently tested.
6
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3683/72V3693/72V36103withCLKA
andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected
tonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT72V3683/72V3693/72V36103
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
CL
fo
switching frequency of an output
100
90
VCC = 3.6V
80
70
60
VCC = 3.0V
VCC = 3.3V
fdata = 1/2 fS
TA
= 25°C
CL
= 0 pF
50
40
30
20
10
0
100
0
10
20
30
40
50
Clock Frequency MHz
60
70
90
80
4678 drw 03
fS
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C;JEDEC JESD8-A compliant)
IDT72V3683L10 IDT72V3683L15
IDT72V3693L10 IDT72V3693L15
IDT72V36103L10 IDT72V36103L15
Symbol
fS
Parameter
Min.
—
10
4.5
4.5
3
Max.
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
—
15
6
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
ns
PulseDuration, CLKAandCLKBLOW
6
ns
SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑
SetupTime, CSAandW/RA before CLKA↑;CSBandW/RBbefore CLKB↑
Setup Time, ENA, and MBA before CLKA↑;ENBandMBBbefore CLKB↑
4
ns
tENS1
tENS2
tRSTS
tFSS
4
4.5
4.5
5
ns
3
ns
(1)
SetupTime, RS1 orPRS LOWbeforeCLKA↑ orCLKB↑
5
ns
Setup Time, FS0, FS1 and FS2 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
SetupTime,FS0/SDbeforeCLKA↑
SetupTime,FS1/SENbeforeCLKA↑
SetupTime,FWFTbeforeCLKA↑
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
Setup Time, RTM before RT1; RTM before RT2
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;CSB, W/RB, ENB, and MBB
afterCLKB↑
Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑
Hold Time, FS0, FS1 and FS2 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
HoldTime, FS0/SDafterCLKA↑
HoldTime,FS1/SENHIGHafterCLKA↑
Hold Time, FS1/SEN HIGH after RS1 HIGH
Hold Time, RTM after RT1; RTM after RT2
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
7.5
7.5
3
7.5
7.5
4
ns
tBES
ns
tSDS
ns
tSENS
tFWS
tDH
3
4
ns
0
0
ns
0.5
5
1
ns
tRTMS
tENH
5
ns
0.5
1
ns
(1)
tRSTH
tFSH
4
2
—
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBEH
2
2
tSDH
0.5
0.5
2
1
tSENH
tSPH
1
2
tRTMH
tSKEW1(2)
5
5
5
7.5
12
tSKEW2(2,3) Skew Time between CLKA↑ and CLKB↑ for AE and AF
12
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
8
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C;JEDEC JESD8-A compliant)
IDT72V3683L10 IDT72V3683L15
IDT72V3693L10 IDT72V3693L15
IDT72V36103L10 IDT72V36103L15
Symbol
tA
Parameter
Min.
2
Max.
6.5
6.5
6.5
6.5
6.5
6.5
Min.
2
Max.
10
8
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
PropagationDelayTime, CLKA↑toFF/IR
PropagationDelayTime,CLKB↑toEF/OR
PropagationDelayTime,CLKB↑toAE
PropagationDelayTime,CLKA↑toAF
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 and CLKB↑ to MBF2
LOW or MBF1 HIGH
PropagationDelayTime, CLKA↑ toB0-B35(1) andCLKB↑toA0-A35(2)
tWFF
tREF
tPAE
tPAF
tPMF
2
2
ns
1
1
8
ns
1
1
8
ns
1
1
8
ns
0
0
8
ns
tPMR
tMDV
tRSF
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
6.5
10
Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1 HIGH
and MBF2 HIGH
tEN
tDIS
Enable Time, CSA andW/RA LOWtoA0-A35Active andCSB LOWandW/RBHIGH
2
1
6
6
2
1
10
8
ns
ns
toB0-B35Active
Disable Time, CSA or W/RA HIGHto A0-A35 athigh-impedance and CSB HIGH
orW/RBLOWtoB0-B35athigh-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
SIGNALDESCRIPTION
— ENDIAN SELECTION
RESET (RS1, RS2)
Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionisactive,
permittingachoiceofBig-orLittle-Endianbytearrangementfordatareadfrom
PortB. Thisselectiondeterminestheorderbywhichbytes(orwords)ofdata
aretransferredthroughthisport. Forthefollowingillustrations,assumethata
byte(orword)bus sizehas beenselectedforPortB. (NotethatwhenPortB
isconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
pulsetoRS1andRS2simultaneously. Afterwards,theFIFOmemoryofthe
IDT72V3683/72V3693/72V36103undergoes a complete resetbytakingits
Reset(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour
PortBclock(CLKB)LOW-to-HIGHtransitions.TheResetinputs canswitch
asynchronouslytothe clocks. AResetinitializes the internalreadandwrite
pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output
Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Fullflag(AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe
parallelmailboxregisterHIGH,andatthesametimetheRS2andMBF2operate
likewise. AfteraReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwo
writeclockcyclestobeginnormaloperation.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferredthroughPortB.
ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe
valuesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag
Programming, and Almost-Empty and Almost-Full flag offset programming
section). The relevantResettimingdiagramcanbe foundinFigure 3.
1
and the BE input is a “don’t care” .)
AHIGHontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaBig-Endianarrangement. Inthiscase,themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBfirst;the
leastsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom
PortBlast.
ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBfirst;the
mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom
PortBlast. RefertoFigure2foranillustrationoftheBEfunction.SeeFigure
3(Reset)foranEndianselecttimingdiagram.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT
inputduringthenextLOW-to-HIGHtransitionofCLKA andCLKB willselect
IDTStandardmode. ThismodeusestheEmptyFlagfunction(EF)toindicate
whetherornotthereareanywords presentintheFIFOmemory. Ituses the
FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
includingthefirst,mustberequestedusingaformalreadoperation.
OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring
thenextLOW-to-HIGHtransitionofCLKA andCLKBwillselectFWFTmode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReadyfunction
(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
PARTIAL RESET (PRS)
The FIFOmemoryofthe IDT72V3683/72V3693/72V36103undergoes a
limitedresetbytakingitsPartialReset(PRS)inputLOWforatleastfourPortA
clock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.TheRTM
pinmustbeLOWduringthetimeofPartialReset. ThePartialResetinputcan
switchasynchronouslytotheclocks. APartialResetinitializestheinternalread
andwritepointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/
OutputReadyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andthe
Almost-Fullflag(AF)HIGH. APartialResetalsoforcestheMailboxflag(MBF1,
MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,theFIFO’s
Full/InputReadyflagissetHIGHaftertwoWriteClockcyclestobeginnormal
operation. See Figure 4, PartialReset(IDTStandardandFWFTModes)for
therelevanttimingdiagram.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogrammingaFIFOfollowingaResetwouldbeinconvenient.
Following Reset, the level applied to the BE/FWFT input to choose the
desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto
Figure 3(Reset)fora FirstWordFallThroughselecttimingdiagram.
RETRANSMIT (RT)
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
TworegistersintheIDT72V3683/72V3693/72V36103areusedtoholdthe
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag
(AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled
Y.Theoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofthe
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).FS2 FS0/
SD, and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
The FIFOmemoryofthese devices undergoes a Retransmitbytakingits
associatedRetransmit (RT)inputLOWforatleastfourPortAClock(CLKA)and
fourPortBClock(CLKB)LOW-to-HIGHtransitions.TheRetransmitinitializes
thereadpointerofFIFOtothefirstmemorylocation.
TheRTMpinmustbeHIGHduringthetimeofRetransmit.Notethatthe RT
inputismuxedwiththePRSinput,thestateoftheRTMpindeterminingwhether
thispinperformsaRetransmitoraPartialReset.SeeFigure19forRetransmit
(Standard IDT mode) and figure 20 for Retransmit (FWFT mode) timing
diagrams.
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
TABLE 1 — FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
H
H
H
↑
64
H
H
L
L
L
H
L
H
L
H
L
H
L
L
L
H
H
H
L
↑
↑
↑
↑
↑
↑
↑
16
8
256
1,024
SerialprogrammingviaSD
(2,4)
L
ParallelprogrammingviaPortA
IP Mode(3,4)
L
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
theflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith ParityisselectedthendatalineA8willbecomeavalidbit.IfInterspersedParity
oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel
orLOWduringareset. Forexample,toloadthepresetvalueof64intoXand programmingcanbedone.
Y,FS0,FS1andFS2mustbeHIGHwhenRS1returnsHIGH. Fortherelevant
presetvalueloadingtimingdiagram, seeFigure3.
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,FS0/
SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1. After
— PARALLEL LOAD FROM PORT A
ToprogramtheXandYregistersfromPortA,performaResetwithFS2HIGH thisresetiscomplete,theXandYregistervaluesareloadedbit-wisethrough
orLOWandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1. theFS0/SDinputoneachLOW-to-HIGHtransitionofCLKAthattheFS1/SEN
The state of FS2 at this point of reset will determine whether the parallel input is LOW. There are 28-, 30- or 32-bit writes needed to complete the
programming method has Interspersed Parity or Non-Interspersed Parity. programmingfortheIDT72V3683,IDT72V3693ortheIDT72V36103,respec-
RefertoTable1forFlagProgrammingFlagOffsetsetup.Itisimportanttonote tively. ThetworegistersarewrittenintheorderY,X. Eachregistervaluecan
thatonceparallelprogramminghasbeenselectedduringaMasterResetby beprogrammedfrom1to16,380(IDT72V3683),1to32,764(IDT72V3693)
holding both FS0 & FS1 LOW, these inputs must remain LOW during all or 1 to 65,532 (IDT72V36103).
subsequent FIFO operation. They can only be toggled HIGH when future
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
MasterResetsareperformedandotherprogrammingmethodsaredesired. InputReady(FF/IR)flagremainsLOWuntilallregisterbitsarewritten. FF/IR
Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredata issetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded
inRAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On toallownormalFIFOoperation.
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused FIFO WRITE/READ OPERATION
bytheOffsetregistersare(A13-A0),(A14-A0),or(A15-A0)fortheIDT72V3683,
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
IDT72V3693,orIDT72V36103,respectively.ForInterspersedParitymode (CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-
thePortAdatainputsusedbytheOffsetregistersare(A14-A9,A7-A0),(A15- impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
A9, A7-A0), or (A16-A9, A7-A0) for the IDT72V3683, IDT72V3693, or activeoutputs whenbothCSA andW/RAareLOW.
IDT72V36103,respectively. Thehighestnumberedinputisusedasthemost
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
significantbitofthebinarynumberineachcase. Validprogrammingvaluesfor transitionofCLKAwhenCSA is LOW, W/RA is HIGH, ENAis HIGH, MBAis
theregisters rangefrom1to16,380fortheIDT72V3683;1to32,764forthe LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
IDT72V3693;and1to65,532fortheIDT72V36103. Afteralltheoffsetregisters of any concurrent reads on Port B.
areprogrammedfromPortA,theFIFObegins normaloperation.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read
select(W/RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
INTERSPERSED PARITY
InterspersedParityis selectedduringaMasterResetoftheFIFO.Refer PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB). TheB0-B35
toTable1fortheset-upconfigurationofInterspersedParity.TheInterspersed linesareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBisLOW.
Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH.
loaded into the parallel port (A0-An) during programming of the flag offset
DataisreadfromtheFIFOtotheB0-B35outputsbyaLOW-to-HIGHtransition
values.IfInterspersedParityisselectedthenduringparallelprogrammingof ofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,MBBisLOW,and
11
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Functions
X
X
↑
None
H
L
X
None
L
H
H
L
Input
FIFOWrite
L
H
H
H
↑
Input
Mail1Write
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
None
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 Read (Set MBF2 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
Port Functions
X
X
↑
None
L
L
X
None
L
L
H
L
Input
None
Mail2Write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO read
L
H
L
H
X
↑
Output
None
L
H
H
H
Output
Mail1 Read (Set MBF1 HIGH)
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT72V3683(3)
0
IDT72V3693(3)
IDT72V36103(3)
0
EF/OR
AE
AF
H
H
H
L
FF/IR
H
0
L
H
H
H
H
L
L
1 to X
1 to X
1 to X
H
(X+1)to[16,384-(Y+1)]
(16,384-Y)to16,383
16,384
(X+1)to[32,768-(Y+1)]
(32,768-Y)to32,767
32,768
(X+1)to[65,536-(Y+1)]
(65,536-Y)to65,535
65,536
H
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
EF/ORisHIGH(seeTable3). FIFOreadsonPortBareindependentofany WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemoryarray
concurrentwrites onPortA.
isclockedtotheoutputregisteronlywhenareadisselectedusingtheport’s
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects ChipSelect,Write/Readselect,Enable,andMailboxselect.
andWrite/Readselects areonlyforenablingwriteandreadoperations and When operating the FIFO in IDT Standard mode, regardless of whether
arenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay clocked to the output register only when a read is selected using the port’s
changestatesduringthesetupandholdtimewindowofthecycle.
Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, timing diagram can be found in Figure 7. Relevant Port B Read timing
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe diagrams together with Bus-Matching and Endian select can be found in
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. Figure 8, 9 and 10.
12
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthan
twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince
the next memory write location has been read. The second LOW-to-HIGH
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
theFull/InputReadyflagHIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 13 and 14).
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages.
This is done to improve flag-signal reliability by reducing the probability of
metastable events when CLKA and CLKB operate asynchronously to one
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronizedtoCLKB. Table4 shows therelationshipofeachportflagtothe
numberofwords storedinmemory.
EMPTY/OUTPUTREADYFLAGS(EF/OR)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
intheFIFOoutputregister. WhentheOutputReadyflagisLOW,theprevious
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare
ignored.
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When
theEmptyFlagisHIGH,dataisavailableintheFIFO’smemoryforreadingto
the outputregister. Whenthe EmptyFlagis LOW, the previous data wordis
presentinthe FIFOoutputregisterandattemptedFIFOreads are ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclockthat
readsdatafromitsarray(CLKB). ForboththeFWFTandIDTStandardmodes,
theFIFOreadpointerisincrementedeachtimeanewwordisclockedtoitsoutput
register. ThestatemachinethatcontrolsanOutputReadyflagmonitorsawrite
pointerandreadpointercomparatorthatindicateswhentheFIFOmemorystatus
isempty,empty+1,orempty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshiftedto
theFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwaswritten. TheOutputReadyflagoftheFIFOremainsLOWuntilthe
thirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simultaneously
forcingthe OutputReadyflagHIGHandshiftingthe wordtothe FIFOoutput
register.
ALMOST-EMPTYFLAG(AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray(CLKB). ThestatemachinethatcontrolsanAlmost-Empty
flagmonitorsawritepointerandreadpointercomparatorthatindicateswhen
theFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.
TheAlmost-EmptystateisdefinedbythecontentsofregisterX. Theseregisters
areloadedwithpresetvaluesduringaFIFOreset,programmedfromPortA,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programmingsection). AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
XorlesswordsandisHIGHwhenitsFIFOcontains(X+1)ormorewords. Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-
nizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFO
to(X+1)words. Otherwise,thesubsequentsynchronizingclockcyclemaybe
thefirstsynchronizationcycle.(SeeFigure15).
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
ifawordinmemoryis thenextdatatobesenttotheFlFOoutputregisterand
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil
thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing
the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 11 and 12).
ALMOST-FULL FLAG (AF)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstate
isdefinedbythecontentsofregisterY.Theseregistersareloadedwithpreset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section). AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOis
greater than or equal to (16,384-Y), (32,768-Y), or (65,536-Y) for the
IDT72V3683, IDT72V3693, or IDT72V36103 respectively. An Almost-Full
flag is HIGH when the number of words in its FIFO is less than or equal to
[16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3683,
IDT72V3693,orIDT72V36103respectively. Notethatadatawordpresent
inthe FIFOoutputregisterhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
requiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewleveloffill.
Therefore,theAlmost-FullflagofaFIFOcontaining[16,384/32,768/65,536-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[16,384/32,768/65,536-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecond
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reducesthenumberofwordsinmemoryto[16,384/32,768/65,536-(Y+1)]. A
LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe
FULL/INPUT READY FLAGS (FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function
isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For
bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation
is free in the FIFO to receive new data. No memory locations are free when
theFull/InputReadyflagisLOWandattemptedwritestotheFIFOareignored.
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
datatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,eachtime
awordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFO memorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
13
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
Thedatainamailregisterremainsintactafteritisreadandchangesonlywhen
reduces the number of words in memory to [16,384/32,768/65,536-(Y+1)]. newdataiswrittentotheregister. TheEndianselectfeaturehasnoeffecton
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro- mailboxdata. Formailregisterandmailregisterflagtimingdiagrams,seeFigure
nization cycle (see Figure 16).
17 and 18.
MAILBOX REGISTERS
BUS SIZING
Two36-bitbypassregistersareontheIDT72V3683/72V3693/72V36103
The Port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
topasscommandandcontrolinformationbetweenPortAandPortBwithout bitbyteformatfordatareadfromtheFIFO. ThelevelsappliedtothePortBBus
puttingitinqueue. TheMailboxselect(MBA,MBB)inputs choosebetween Sizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbussize.
amailregisterandaFIFOforaportdatatransferoperation. Theusablewidth These levels should be static throughout FIFO operation. Both bus size
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB. selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen Ready flag is set HIGH, as shown in Figure 2.
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
TwodifferentmethodsforsequencingdatatransferareavailableforPortB
selectedPortBbussizeis 36bits,theusablewidthoftheMail1Registeremploys whenthebus sizeselectionis eitherbyte-orword-size. Theyarereferredto
datalinesA0-A35. IftheselectedPortBbussizeis18bits,thentheusablewidth asBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificantbyte
oftheMail1RegisteremploysdatalinesA0-A17. (Inthiscase,A18-A35are first). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-to-
don’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidth HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduringFIFO
oftheMail1RegisteremploysdatalinesA0-A8. (Inthiscase,A9-A35aredon’t operation. BEisadon’tcareinputwhenthebussizeselectedforPortBislong
careinputs.)
ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatotheMail2Register the Full/Input Ready flag is set HIGH, as shown in Figure 2.
whenaPortBwriteis selectedbyCSB, W/RB,andENBwithMBBHIGH. If Only 36-bit long word data is written to or read from the FIFO memory on the
word. TheendianmethodisimplementedatthecompletionofReset,bythetime
theselectedPortBbussizeis36bits,theusablewidthoftheMail2employs IDT72V3683/72V3693/72V36103. Bus-matching operations are done after
datalinesB0-B35. IftheselectedPortBbussizeis18bits,thentheusablewidth data is read from the FIFO RAM. These bus-matching operations are not
oftheMail2RegisteremploysdatalinesB0-B17. (Inthiscase,B18-B35are available when transferring data via mailbox registers. Furthermore, both the
don’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidth word-andbyte-sizebusselectionslimitthewidthofthedatabusthatcanbeused
oftheMail2RegisteremploysdatalinesB0-B8. (Inthiscase,B9-B35aredon’t for mail register operations. In this case, only those byte lanes belonging to the
careinputs.)
selected word- or byte-size bus can carry mailbox data. The remaining data
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2) outputswillbeindeterminate. Theremainingdatainputswillbedon’tcareinputs.
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW. For example, when a word-size bus is selected, then mailbox data can be
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe transmitted only between A0-A17 and B0-B17. When a byte-size bus is
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe selected, then mailbox data can be transmitted only between A0-A8 and B0-
mailregisterwhentheportMailboxselectinputisHIGH.
B8. (See Figures 17 and 18).
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadis selectedbyCSB,W/RB,andENBwithMBB BUS-MATCHING FIFO READS
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
Data is read from the FIFO RAM in 36-bit long word increments. If a long
Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17. (Inthis wordbussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFO
case,B18-B35areindeterminate.) Fora9-bitbussize,9bitsofmailboxdata output register. If byte or word size is implemented on Port B, only the first one
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
or two bytes appear on the selected portion of the FIFO output register, with the
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
onCLKAwhenaPortAreadis selectedbyCSA,W/RA,andENAwithMBA reads output the rest of the long word to the FIFO output register in the order
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
shown by Figure 2.
Whenreadingdata fromFIFOinbyte orwordformat, the unusedB0-B35
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17. (Inthiscase, outputsareindeterminate.
A18-A35are indeterminate.) Fora 9-bitbus size, 9bits ofmailboxdata are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
14
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
BYTE ORDER ON PORT A:
A35 A27
A26 A18
A17 A9
A8 A0
Write to FIFO
A
B
C
D
B35 B27
B26 B18
B
B17 B9
B8 B0
BYTE ORDER ON PORT B:
BE BM SIZE
D
A
C
Read from FIFO
X
L
X
(a) LONG WORD SIZE
B35 B27
B35 B27
B26 B18
B26 B18
B17 B9
B8 B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
A
B
H
H
L
B17 B9
B8 B0
C
D
(b) WORD SIZE
BIG-ENDIAN
B17 B9
C
B35 B27
B35 B27
B26 B18
B8 B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
D
L
H
L
B26 B18
B17 B9
B8 B0
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35 B27
B35 B27
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
BE BM SIZE
A
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B26 B18
B26 B18
B26 B18
B17 B9
B17 B9
B17 B9
B8 B0
B
B8 B0
C
3rd: Read from FIFO
4th: Read from FIFO
B8 B0
D
(d) BYTE SIZE
BIG-ENDIAN
B35 B27 B26 B18
B35 B27 B26 B18
B35 B27 B26 B18
B35 B27 B26 B18
B17 B9
B8 B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B17 B9
B17 B9
B8 B0
C
2nd: Read from FIFO
3rd: Read from FIFO
B8 B0
B
B17 B9
B8 B0
A
4th: Read from FIFO
4678 drw 04
(e) BYTE SIZE
LITTLE-ENDIAN
Figure 2. Bus sizing
15
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
1
2
CLKA
CLKB
t
RSTS
tRSTH
RS1, RS2
BE/FWFT
t
BEH
t
BES
tFWS
BE
0,1
FWFT
t
FSH
t
FSS
FS2,
FS1,FS0
t
WFF
t
WFF
FF/IR
EF/OR
AE
(2)
tREF
t
t
RSF
RSF
AF
t
RSF
MBF1,
MBF2
RTM
LOW
4678 drw 05
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS
t
WFF
t
WFF
FF/IR
(2)
REF
t
EF/OR
AE
t
RSF
t
RSF
AF
t
RSF
MBF1,
MBF2
RTM LOW
4678 drw 06
NOTES:
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKA
2
1
4
RS1
t
FSS
t
FSH
FS2
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FF/IR
tENS2
tENH
ENA
tDH
tDS
A0-A35
4678 drw 07
AE Offset
First Word to FIFO1
AF Offset
(Y)
(X)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
CLKA
RS1
FS2
4
t
t
FSS
FSS
t
FSH
t
WFF
FF/IR
t
SENS
t
SENH
SDH
t
SENS
t
SENH
SDH
tSPH
FS1/SEN
tSDS
t
t
tSDS
FS0/SD(2)
4678 drw 08
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
17
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
FF/IRA HIGH
tENS1
tENH
CSA
tENS1
t
ENH
ENH
ENH
W/RA
t
ENS2
t
MBA
ENA
tENS2
tENH
t
tENS2
tENS2
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0-A35
4678 drw 09
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR HIGH
CSB
W/RB
MBB
ENB
t
ENS2
tENH
t
ENH
t
ENS2
tENH
t
ENS2
No Operation
W2(1)
tDIS
t
MDV
tA
t
A
t
EN
Previous Data
W1 (1)
W2 (1)
B0-B35
(Standard Mode)
t
MDV
tDIS
OR
t
A
t
A
t
EN
B0-B35
W1(1)
W3 (1)
(FWFT Mode)
4678 drw 10
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKB
FF/OR HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
Read 2
t
DIS
t
MDV
t
A
t
A
B0-B17
t
EN
(Standard Mode)
Previous Data
Read 1
Read 2
t
DIS
OR
t
MDV
t
A
t
A
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
4678 drw 11
NOTE:
1. Unused word B18-B35 are indeterminate.
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
SIZE
DATA WRITTEN TO FIFO 1
READ
NO.
DATA READ FROM FIFO
BM
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKB
EF/OR HIGH
CSB
W/RB
MBB
t
ENS2
t
ENH
A
ENB
No Operation
t
MDV
tDIS
t
A
tA
t
t
A
t
EN
B0-B8
(Standard Mode)
Read 1
Read 4
Read 5
Previous Data
Read 2
Read 3
tDIS
OR
tA
t
MDV
tA
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
4678 drw 12
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
READ
DATA READ FROM FIFO
B8-B0
NO.
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
A
B
C
D
1
2
3
4
D
C
B
A
H
H
L
A
B
C
D
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
LOW
HIGH
CSA
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
t
IR HIGH
A0-A35
tDS
tDH
W1
t
tSKEW1
CLKtCLKL
(1)
tCLKH
CLKB
1
2
3
t
REF
tREF
FIFO Empty
LOW
OR
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
B0-B35
NOTES:
tA
Old Data in FIFO Output Register
W1
4678 drw 13
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
CSA
W/RA HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
FF HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
t
REF
t
REF
EF
FIFO Empty
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0-B35
NOTES:
W1
4678 drw 14
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENH
tENS2
ENB
OR HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
CLKA
tCLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
t
WFF
t
WFF
IR
FIFO Full
LOW
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
To FIFO
4678 drw 15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB HIGH
LOW
MBB
tENS2
tENH
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
SKEW1
Next Word From FIFO
B0-B35
(1)
t
tCLK
tCLKH
tCLKL
CLKA
1
2
WFF
ENH
WFF
t
t
FIFO Full
LOW
FF
CSA
HIGH
W/RA
t
t
ENS2
ENS2
MBA
t
tENH
ENA
tDS
tDH
A0-A35
4678 drw 16
To FIFO
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Words in FIFO
(X+1) Words in FIFO
ENS2
t
tENH
ENB
4678 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKA
1
2
(1)
tENH
tENS2
tSKEW2
ENA
AF
t
PAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
CLKB
tENH
tENS2
ENB
4678 drw 18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3683, 32,768 for the IDT72V3693, 65,536 for the IDT72V36103.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENH
t
ENS1
t
t
ENS2
tENH
ENS2
tENH
ENA
tDH
tDS
W1
A0-A35
CLKB
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
tDIS
t
PMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
4678 drw 19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKB
tENH
tENS1
CSB
tENH
tENS1
W/RB
t
ENH
t
ENS2
ENS2
MBB
ENB
tENH
t
tDH
tDS
W1
B0-B35
CLKA
MBF2
t
PMF
t
PMF
CSA
W/RA
MBA
ENA
tENH
tENS2
t
EN
tPMR
t
DIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
4678 drw 20
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid
data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
26
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
4
1
2
3
2
3
4
1
tENS2
tENH
ENB
tRSTH
t
RSTS
RT
t
RTMS
t
RTMH
RTM
(2)
REF
(2)
REF
t
t
EF
tA
B0-Bn
Wx
W1
4678 drw 21
NOTE:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be LOW throughout the Retransmit setup procedure.
D = 16,384, 32,768 and 65,536 for the IDT72V3683, IDT72V3693 and IDT72V36103 respectively.
Figure 19. Retransmit Timing (IDT Standard Mode)
CLKA
CLKB
4
1
2
3
2
3
4
1
ENB
RT
LOW
t
RSTH
t
RSTS
t
RTMS
t
RTMH
RTM
OR
(2)
REF
(2)
REF
t
t
t
A
B0-Bn
Wx
W1
4678 drw 22
NOTE:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after OR returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 16,384, 32,768 and 65,536 for the IDT72V3683, IDT72V3693 and IDT72V36103 respectively.
Figure 20. Retransmit Timing (FWFT Mode)
27
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
READ CLOCK (CLKB)
CHIP SELECT (CSB)
EMPTY FLAG/
OUTPUT READY (EF/OR)
CLKB
CLKA
CHIP SELECT (CSA)
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
EF/OR
ENA
V
CC
FF/IR
ENB
READ ENABLE (ENB)
V
CC
CSB
CSA
READ SELECT (W/RB)
IDT
IDT
72V3683
72V3693
72V36103
72V3683
72V3693
72V36103
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A
0
-A35
n
B
0
-B35
B0-B35
n
FULL FLAG/
INPUT READY (FF/IR)
DATA OUT (Qn)
Qn
Dn
V
CC
V
CC
W/RA
MBA
W/RB
MBB
4678 drw 23
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 21. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
28
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3 V
330Ω
From Output
Under Test
30 pF (1)
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
1.5 V
Timing
Input
1.5 V
High-Level
Input
GND
1.5 V
1.5 V
GND
t
S
th
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈ 3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4678 drw 24
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms.
29
ORDERING INFORMATION
IDT
X
XX
X
X
XXXXXX
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0oC to +70oC)
BLANK
PF
Thin Quad Flat Pack (TQFP, PK128-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
16,384 x 36 3.3V SyncFIFO with Bus-Matching
72V3683
72V3693 32,768 x 36 3.3V SyncFIFO with Bus-Matching
72V36103
65,536 x 36 3.3V SyncFIFO with Bus-Matching
4678 drw 25
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
11/05/2001
11/04/2003
pgs. 4-9, 12 and 30.
pg. 1.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
30
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