IDT72V70200J8 [IDT]
Digital Time Switch, PQCC84, 1.150 X 1.150 INCH, 1.27 MM PITCH, PLASTIC, LCC-84;
| 型号： | IDT72V70200J8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch, PQCC84, 1.150 X 1.150 INCH, 1.27 MM PITCH, PLASTIC, LCC-84 电信 电信集成电路 |
| 文件： | 总24页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
IDT72V70200
512 x 512
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack
(PQFP) and 100-pin Thin Quad Flatpack (TQFP)
3.3V Power Supply
ꢀEATURES:
•
•
•
•
•
•
•
•
•
•
•
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512 x 512 channel non-blocking switching at 2.048 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS®/GCI interfaces
Accept 16 serial data streams of 2.048 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
•
•
Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT72V70200 is a non-blocking digital switch that has a capacity of
512x512channels at2.048Mb/s.Someofthemainfeatures are:program-
mablestreamandchannelcontrol,ProcessorMode,inputoffsetdelayandhigh-
impedanceoutputcontrol.
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip
switchesthattransportbothvoicechannelandconcatenateddatachannels.In
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
ꢀUNCTIONALBLOCKDIAGRAM
RESET
TRST
VCC GND
TMS
TDI
TDO TCK
IC
ODE
Test Port
Loopback
RX0
TX0
TX1
RX1
RX2
RX3
TX2
TX3
RX4
TX4
Receive
Serial Data
Streams
RX5
RX6
Transmit
Serial Data
Streams
TX5
TX6
Output
MUX
RX7
Data Memory
TX7
RX8
TX8
RX9
TX9
RX10
RX11
RX12
RX13
RX14
RX15
TX10
TX11
TX12
TX13
TX14
TX15
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
DS/
RD
F0i
DTA
D8-D15/
CLK
FE
IC
AS/ IM
ALE
R/W/ A0-A7
WR
CCO
CS
AD0-AD7
5711 drw01
AUGUST 2001
IDT,theIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5711/3
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
PINCONꢀIGURATIONS
A1 BALL PAD CORNER
A
RX0 TX13 TX11 TX10 TX8
TX7 TX4 TX3 TX0 CCO
B
C
D
E
F
RX2 RX1 TX14 TX12 TX9 TX6 TX5 TX2 ODE D14
RX5 RX4 RX3 TX15 VCC VCC DNC TX1 D15 D12
DTA
RX7 RX8 RX6 VCC GND GND VCC
D13
D11
D9
RX10 RX9 VCC GND GND GND GND VCC D10
RX11 RX12 VCC GND
RX13 RX15 CLK VCC
VCC
GND GND GND
AD7
D8
G
H
J
GND GND VCC AD4 AD6 AD5
RESET
CS
RX14
FE
TCK
VCC VCC
AD1 AD2 AD3
IM
AD0
F0i
TRST
TDI
A0
A4
A7
A1
R/W/RW
K
TMS TDO
IC
IC
A2
A3
A5
A6 DS/RD AS/ALE
1
2
3
4
5
6
7
8
9
10
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BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
TOP VIEW
INDEX
7
8
6
5
4
3
2
84 83 82 81 80 79 78 77 76 75
11 10 9
1
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
F0i
CCO
74
73
72
71
70
69
68
67
66
65
12
DTA
D15
D14
D13
D12
D11
D10
D9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
64
63
62
61
60
59
58
57
56
FE
GND
CLK
VCC
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
5711 drw03
NOTES:
PLCC: 0.05in. pitch, 1.15in. x 1.15in. (PL84-1, order code: J)
TOP VIEW
1. DNC - Do Not Connect
2. IC - Internal Connection, tie to GROUND for normal operation.
3. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
2
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
PINCONꢀIGURATIONS(CONTINUED)
DNC
DNC
RX0
76
77
78
79
90
81
82
83
84
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DNC
DNC
CCO
DTA
D15
D14
D13
D12
D11
D10
D9
RX1
RX2
RX3
RX4
RX5
RX6
RX7
85
RX8
86
87
88
89
90
91
RX9
D8
RX10
RX11
RX12
RX13
RX14
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
DNC
DNC
92
93
94
95
RX15
F0i
FE/HCLK
GND
CLK
96
97
98
99
100
VCC
DNC
DNC
INDEX
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TQFP: 0.50mm pitch, 14mm x 14mm (PN100-1, order code: PF)
TOP VIEW
50
49
48
RX0
DTA
81
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
F0i
82
83
84
D15
D14
D13
47
46
45
44
43
42
D12
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D11
D10
D9
D8
41
40
39
38
37
36
35
34
33
32
31
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
FE
GND
CLK
INDEX
5711 drw05
PQFP: 0.65mm pitch, 14mm x 20mm (PQ100-2, order code: PQF)
TOP VIEW
3
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
SYMBOL
GND
NAME
Ground.
Vcc
I/O
DESCRIPTION
Ground Rail.
Vcc
+3.3 Volt Power Supply.
TX0-15(1) TX Output 0 to 15
(Three-state Outputs)
O
Serial data output stream. These streams have a data rate of 2.048 Mb/s.
RX0-15(1) RX Input 0 to 15
I
I
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS®
and GCI specifications.
(1)
F0i
Frame Pulse
FE(1)
Frame Evaluation
Clock
I
I
I
This pin is the frame measurement input.
(1)
CLK
TMS
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). This input accepts a 4.096 MHz clock.
Test Mode Select
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
TDI
Test Serial Data In
Test Serial Data Out
I
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
(1)
TCK
Test Clock
Test Reset
I
I
Provides the clock to the JTAG test logic.
TRST
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70200 is in the normal functional mode.
IC(1)
InternalConnection
I
I
ConnecttoGNDfornormaloperation. ThispinmustbeLOWfortheIDT72V70200tofunctionnormallyandto
complywithIEEE1114(JTAG)boundaryscanrequirements.
(1)
RESET
Device Reset
(Schmitt Trigger Input)
This input (active LOW) puts the IDT72V70200 in its reset state that clears the device internal counters, registers
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET
pin must be held LOW for a minimum of 100ns to reset the device.
A0-7(1)
Address 0-7
I
I
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
(1)
DS/RD
Data Strobe/Read
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.
This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed
bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
(1)
R/W / WR Read/Write / Write
I
(1)
CS
Chip Select
I
I
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70200.
AS/ALE(1) Address Strobe or
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
Latch Enable
(1)
IM
CPU Interface Mode
I
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
AD0-7(1)
Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
D8-15(1)
Data Bus 8-15
I/O These pins are the eight most significant data bits of the microprocessor port.
(1)
DTA
Data Transfer
Acknowledgment
O
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
(1)
CCO
Control Output
O
I
This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by
the CCO bit in the connection memory. See External Drive Control Section.
ODE(1)
Output Drive Enable
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
NOTE:
1. These pins are 5V tolerant.
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IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
serialconverteronetime-slotbeforeitistobeoutput.Thisdatawillbeoutput
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
AstheIDT72V70200canbeusedinawidevarietyofapplications,thedevice
alsohas memorylocations tocontrolthe outputs basedonoperatingmode.
Specifically, the IDT72V70200provides five per-channelcontrolbits forthe
followingfunctions:processororconnectionmode,constantorvariabledelay,
enables/three-statetheTXoutputdriversandenables/disabletheloopback
function.Inaddition,oneofthesebitsallowstheusertocontroltheCCOoutput.
Ifanoutputchannelissettoahigh-impedancestatethroughtheconnection
memory,theTXoutputwillbeinahigh-impedancestateforthedurationofthat
channel.Inadditiontotheper-channelcontrol,allchannelsontheST-BUS®
outputscanbeplacedinahighimpedancestatebyeitherpullingtheODEinput
pinloworprogrammingtheOutputStand-By(OSB)bitintheinterfacemode
selectionregister.Thisactionoverridestheper-channelprogramminginthe
connectionmemorybits.
ꢀUNCTIONALDESCRIPTION
The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or
N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channelbasis.
The serial input streams of the IDT72V70200 can have a bit rate of
2.048Mb/sandarearrangedin125µswideframes,whichcontain32channels
respectively.Thedataratesoninputandoutputstreamsareidentical.
InProcessorMode,themicroprocessorcanaccessinputandoutputtime-
slotsonaperchannelbasisallowingfortransferofcontrolandstatusinformation.
TheIDT72V70200automaticallyidentifiesthepolarityoftheframesynchroni-
zationinputsignalandconfigurestheserialstreamstoeitherST-BUS® orGCI
formats.
Withthevarietyofdifferentmicroprocessorinterfaces,IDT72V70200has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessorbasedenvironments:Non-multiplexedorMultiplexed.These
interfacesprovidecompatibilitywithmultiplexedandMotorolanon-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
ofglue logicnecessarytoconvertthe signals (R/W/WR, DS/RD, AS/ALE).
Theframeoffsetcalibrationfunctionallowsuserstomeasuretheframeoffset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 8.
The connection memory data can be accessed via the microprocessor
interface.Theaddressingofthedevicesinternalregisters,dataandconnection
memoriesisperformedthroughtheaddressinputpinsandtheMemorySelect
(MS)bitofthecontrolregister.Fordetailsondeviceaddressing,seeSoftware
ControlandControlRegisterbits description(Table 3and5).
SERIAL DATA INTERFACE TIMING
Themasterclockfrequencymustalwaysbetwicethedatarate.Forserial
datarates of2.048Mb/s,themasterclock(CLK)mustbeat4.096MHz.The
inputandoutputstreamdatarateswillalwaysbeidentical.
TheinternalloopbackallowstheTXoutputdatatobeloopedaroundtothe
RXinputsfordiagnosticpurposes.
Theinput8KHzframepulsecanbeineitherST-BUS® orGCIformat.The
IDT72V70200automaticallydetectsthepresenceofaninputframepulseand
identifiesitaseitherST-BUS® orGCI.InST-BUS® format,everysecondfalling
edgeofthemasterclockmarksabitboundaryandthedataisclockedinonthe
risingedgeofCLK,threequarters ofthewayintothebitcell,seeFigure7.In
GCIformat,everysecondrisingedgeofthemasterclockmarksthebitboundary
anddata is clockedinonthe fallingedge ofCLKatthree quarters ofthe way
intothe bitcell, see Figure 8.
AfunctionalBlockDiagramofthe IDT72V70200is showninFigure 1.
DATAANDCONNECTIONMEMORY
Thereceivedserialdatais convertedtoparallelformatbyinternalserial-
to-parallelconvertersandstoredsequentiallyinthedatamemory.The8KHz
inputframepulse(F0i)isusedtogeneratechannelandframeboundariesof
theinputserialdata. Dependingontheinterfacemodeselect(IMS)register,
the usable data memory may be as large as 512 bytes.
Datatobeoutputontheserialstreams(TX0-15)maycomefromeitherthe
data memory or connection memory. For data output from data memory
(connectionmode),addressesintheconnectionmemoryareused.Fordata
tobeoutputfromconnectionmemory,theconnectionmemorycontrolbitsmust
settheparticularTXoutputinProcessorMode. Onetime-slotbeforethedata
is tobe output, data fromeitherconnectionmemoryordata memoryis read
internally. Thisallowsenoughtimeformemoryaccessandparallel-to-serial
conversion.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Althoughallinputdatacomesinatthesamespeed,delayscanbecausedby
variable path serial backplanes and variable path lengths which may be
implementedinlargecentralizedanddistributedswitchingsystems. Because
dataisoftendelayed,thisfeatureisusefulincompensatingfortheskewbetween
clocks.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR).Themaximumallowableskewis+4.5master
clock(CLK)periodsforwardwithresolutionof½clockperiod.Theoutputframe
offsetcannotbeoffsetoradjusted.SeeFigure5,Table8and9fordelayoffset
programming.
CONNECTION AND PROCESSOR MODES
IntheConnectionMode,theaddressesoftheinputsourcedataforalloutput
channels are stored in the connection memory. The connection memory is
mappedinsuchawaythateachlocationcorrespondstoanoutputchannelon
theoutputstreams.Fordetailsontheuseofthesourceaddressdata(CABand
SABbits),seeTable10.Oncethesourceaddressbitsareprogrammedbythe
microprocessor,thecontentsofthedatamemoryattheselectedaddressare
transferredtotheparallel-to-serialconvertersandthenontoaTXoutputstream.
By having the each location in the connection memory specify an input
channel,multipleoutputscanspecifythesameinputaddress. Thiscanbea
powerfultoolusedforbroadcastingdata.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
TheIDT72V70200providestheframeevaluation(FE)inputtodetermine
differentdatainputdelayswithrespecttotheframepulseF0i.
Ameasurementcycleisstartedbysettingthestartframeevaluation(SFE)
bitlowforatleastoneframe.WhentheSFEbitintheIMSregisterischanged
fromlowtohigh,theevaluationstarts.Twoframeslater,thecompleteframe
evaluation(CFE)bitoftheframealignmentregister(FAR)changesfromlow
tohightosignalthatavalidoffsetmeasurementisreadytobereadfrombits0
In Processor Mode, the microprocessor writes data to the connection
memory. Eachlocationintheconnectionmemorycorrespondstoaparticular
outputstreamandchannelnumberandistransferreddirectlytotheparallel-to-
5
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
to 11 of the FAR register. The SFE bit must be set to zero before a new delaymodewillbeoneframe.Forexample,wheninputtime-slot31isswitched
measurementcyclestarted.
tooutputtime-slot0.Themaximumdelayof94time-slotsofdelayoccurswhen
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(FE) time-slot0inaframeisswitchedtotime-slot31intheframe.SeeTable2.
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
SeeTable7andFigure4forthedescriptionoftheframealignmentregister.
MICROPROCESSORINTERꢀACE
TheIDT72V70200providesaparallelmicroprocessorinterfaceformulti-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorolanon-multiplexedandmultiplexedbuses.
MEMORYBLOCKPROGRAMMING
TheIDT72V70200providesuserswiththecapabilityofinitializingtheentire
connectionmemoryblockintwoframes.Tosetbits11to15ofeveryconnection
memorylocation,firstprogramthedesiredpatterninbits5to9oftheIMSregister.
The block programming mode is enabled by setting the memory block
program(MBP)bitofthecontrolregisterhigh.Whentheblockprogramming
enable(BPE)bitoftheIMSregisterissettohigh,theblockprogrammingdata
willbeloadedintothebits11to15ofeveryconnectionmemorylocation.The
otherconnectionmemorybits(bit0tobit10)areloadedwithzeros.Whenthe
memoryblockprogrammingiscomplete,thedeviceresetstheBPEbittozero.
IftheIMpinislowaMotorolanon-multiplexedbusshouldbeconnectedto
thedevice.IftheIMpinishigh,thedevicemonitorstheAS/ALEandDS/RDto
determinewhatmodetheIDT72V70200shouldoperatein.
IfDS/RDislowattherisingedgeofAS/ALE,thenthemode1multiplexed
timingisselected.IfDS/RDishighattherisingedgeofAS/ALE,thenthemode
2multiplexedbustimingisselected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable(AS/ALE),Datastrobe/Read(DS/RD),Read/Write/Write(R/W/WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 11 and
Figure12formultiplexedparallelmicroporttiming.
LOOPBACKCONTROL
FortheMotorolanon-multiplexedbus,therequiredsignalsarethe16-bit
data bus (AD0-AD7, D8-D15), 8-bitaddress bus (A0-A7)and4controllines
(CS,DS,R/WandDTA).SeeFigure13and14forMotorolanon-multiplexed
microporttiming.
The IDT72V70200 microport provides access to the internal registers,
connectionanddatamemories.Alllocationsprovideread/writeaccessexcept
forthe data memoryandthe frame alignmentregisterwhichare readonly.
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
theTXoutputdatatobeloopedbackedinternallytotheRXinputfordiagnostic
purposes.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,datafromTXnchannelmroutesto
the RXnchannelminternally);ifthe LPBKbitis low, the loopbackfeature is
disabled. Forproperper-channelloopbackoperation, thecontents offrame
delayoffsetregistersmustbesettozero.
MEMORYMAPPING
The address bus on the microprocessor interface selects the internal
registersandmemoriesoftheIDT72V70200.
DELAYTHROUGHTHEIDT72V70200
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesontheper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
IftheA7addressinputislow,thenA6throughA0areusedtoaddressthe
interfacemodeselection(IMS),control(CR),framealignment(FAR)andframe
inputoffset(FOR)registers(Table4).IftheA7ishigh,A6andA5arelow,then
A4throughA0areusedtoselect32locationscorrespondingtodatarateofthe
ST-BUS®. The address input lines and the stream address bits (STA) of the
controlregisterallowaccesstotheentiredataandconnectionmemories.The
controlandIMSregisterstogethercontrolallthemajorfunctionsofthedevice,
see Figure 3.
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigura-
tionssections,aftersystempower-up,theIMSregistershouldbeprogrammed
immediatelytoestablishthedesiredswitchingconfiguration.
Thedatainthecontrolregisterconsistsofthememoryblockprogramming
bit(MBP),thememoryselectbit(MS)andthestreamaddressbits(STA).As
explainedintheMemoryBlockProgrammingsection,theMBPbitallowsthe
entireconnectionmemoryblocktobeprogrammed. Thememoryselectbitis
used to designate the connection memory or the data Memory. The stream
addressbitsselectinternalmemorysubsectionscorrespondingtoinputoroutput
serialstreams.
The delay through the device varies according to the type of throughput
delayselectedintheV/Cbitoftheconnectionmemory.
VARIABLE DELAY MODE (V/C BIT = 0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination channels and is independent of input and output streams. The
minimumdelayachievableintheIDT72V70200isthreetime-slots.Iftheinput
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifinput
channel n is switched to output channel n+1 or n+2. If the input channel n is
switchedtooutputchanneln+3,n+4,...,thenewoutputdatawillappearinthe
same frame. Table 1shows the possible delays forthe IDT72V70200inthe
variable delay mode.
The data in the IMS register consists of block programming bits (BPD0-
BPD4),blockprogrammingenablebit(BPE),outputstandbybit(OSB)andstart
frameevaluationbit(SFE).Theblockprogrammingandtheblockprogramming
enablebitsallowsuserstoprogramtheentireconnectionmemory(seeMemory
BlockProgrammingsection).IftheODEpinislow,theOSBbitenables(ifhigh)
ordisables(iflow)allST-BUS® outputdrivers.IftheODEpinishigh,thecontents
of the OSB bit is ignored and all TX output drivers are enabled.
CONSTANT DELAY MODE (V/C BIT = 1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
thedatamemorybuffers duringframenwillbereadoutduringframen+2.In
theIDT72V70200,theminimumthroughputdelayachievableintheconstant
6
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information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
fromdatamemory.
TheV/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
allows theper-channelselectionbetweenvariableandconstantthroughput
delaymodes.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,RXnchannelmdatacomesfromthe
TXnchannelm). Ifthe LPBKbitis low, the loopbackfeature is disabled. For
properper-channelloopbackoperation,thecontentsoftheframedelayoffset
registersmustbesettozero.
CONNECTIONMEMORYCONTROL
TheCCOpinisa4.096Mb/soutput,whichcarries512bits.Thecontents
oftheCCObitofeachconnectionmemorylocationareoutputontheCCOpin
onceeveryframe. ThecontentsoftheCCObitsoftheconnectionmemoryare
transmittedsequentiallyontotheCCOpinandaresynchronouswiththedata
ratesontheotherserialstreams.
The CCObitis outputone channelbefore the correspondingchannelon
theserialstreams.Forexample, thecontentsoftheCCObitinposition0(TX0,
CH0)oftheconnectionmemoryisoutputonthefirstclockcycleofchannel31
throughCCOpin.ThecontentsoftheCCObitinposition32(TX1,CH0)ofthe
connectionmemoryisoutputonthesecondclockcycleofchannel31viaCCO
pin.
IftheODEpinortheOSBbitishigh,theOEbitofeachconnectionmemory
locationcontrols the outputdrivers-enables (ifhigh)ordisables (iflow). See
Table 4fordetail.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
ProcessorModeandConnectionMode. Ifhigh,thecontentsoftheconnection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
thechanneladdressbit(CAB)oftheconnectionmemorydefinesthesource
INITIALIZATIONOꢀTHEIDT72V70200
Afterpowerup,thestateoftheconnectionmemoryisunknown.Assuch,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODEis low, the microprocessorcaninitialize the device, programthe active
paths,anddisableunusedoutputsbyprogrammingtheOEbitinconnection
memory. Oncethedeviceisconfigured,theODEpin(orOSBbitdepending
oninitialization)canbeswitched.
7
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CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
Control Register
b
b
b
b
b
b
b
b
CR 4
b
1
0
The Control Register is only accessed when A7-A0 are all
zeroed. When A7 =1, up to 32 bytes are randomly accessable
via A0-A4 at any one instant. Of which stream these
bytes (channels) are accessed is determined by the state of
CR 3 -CR 0.
b
b
Connection Memory
Data Memory
CR 3 CR 2 CR 1 CR 0
Stream
b
b
b
b
0
0
0
0
0
1
2
3
4
5
6
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
0
0
0
1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
7
8
9
10
11
12
13
14
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
1
1
1
1
15
10000001
10000010
External Address Bits
A7-A0
10000000
10011111
5711 drw06
Figure 3. Addressing Internal Memories
8
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TABLE1VARIABLETHROUGHPUT
DELAYVALUE
TABLE2CONSTANTTHROUGHPUT
DELAYVALUE
Delay for Constant Throughput Delay Mode
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
32 + (32 – n) + m time-slots
Input Rate
(m – output channel number)
(n – input channel number)
m < n
m = n, n+1, n+2
m > n+2
2.048Mb/s
2.048Mb/s 32–(n-m)time-slots m-n+32time-slots m-ntime-slots
TABLE 3INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
(1)
A7
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
0
.
0
0
0
0
1
1
1
0
0
.
0
0
1
1
0
0
1
0
0
.
0
1
0
1
0
1
0
0
1
.
ControlRegister,CR
InterfaceModeSelectionRegister,IMS
FrameAlignmentRegister,FAR
FrameInputOffsetRegister0,FOR0
FrameInputOffsetRegister1,FOR1
FrameInputOffsetRegister2,FOR2
FrameInputOffsetRegister3,FOR3
Ch0
Ch1
.
Ch30
Ch31
1
1
1
1
1
1
1
1
0
1
NOTE:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
TABLE 4OUTPUT HIGH IMPEDANCECONTROL
OE bit in Connection
ODE pin
OSB bit in IMS
Register
TX Output Driver
Status
Memory
0
Don’tCare
Don’tCare
Per Channel
High-Impedance
1
1
1
1
0
0
1
1
0
1
1
0
High-Impedance
Enable
Enable
Enable
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TABLE 5CONTROL REGISTER (CR) BITS
Read/WriteAddress:
ResetValue:
00H,
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
MBP MS STA3 STA2 STA1 STA0
Bit
15-6
5
Name
Unused
Description
Mustbezerofornormaloperation.
MBP
When1,theconnectionmemoryblockprogrammingfeatureisreadyfortheprogrammingofConnection
(MemoryBlockProgram) Memoryhighbits,bit11tobit15.When0,this featureis disabled.
4
MS
When0,connectionmemoryisselectedforreadorwriteoperations.When1,thedatamemoryisselected
forreadoperationsandconnectionmemoryisselectedforwriteoperations.
(Nomicroprocessorwriteoperationis allowedforthedatamemory.)
(MemorySelect)
3-0
STA3-0
(StreamAddressBits)
The binaryvalue expressedbythese bits refers tothe inputoroutputdata stream, whichcorresponds
tothesubsectionofmemorymadeaccessibleforsubsequentoperations.(STA3=MSB,STA0=LSB)
TABLE 6INTERꢀACE MODE SELECTION (IMS) REGISTER BITS
Read/WriteAddress:
ResetValue:
01H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE
0
0
Bit
Name
Description
15-10 Unused
Mustbezerofornormaloperation.
9-5
BPD4-0
(BlockProgrammingData)
These bits carrythe value tobe loadedintothe connectionmemoryblockwheneverthe memoryblock
programmingfeatureisactivated.AftertheMBPbitinthecontrolregisterissetto1andtheBPEbitis
setto1,thecontents ofthebits BPD4-0areloadedintobit15and11oftheconnectionmemory.Bit10to
bit0oftheconnectionmemoryaresetto0.
4
BPE
Azerotoonetransitionofthisbitenablesthememoryblockprogrammingfunction.TheBPEand
BPD4-0bits inthe IMSregisterhave tobe definedinthe same write operation. Once the BPEbitis set
HIGH,thedevicerequirestwoframestocompletetheblockprogramming.Aftertheprogrammingfunction
has finished,theBPEbitreturns tozerotoindicatetheoperationis completed. WhentheBPE=1, theBPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
mustnotbechangedfortwoframes toensureproperoperation.
(BeginBlockProgramming
Enable)
3
2
OSB
(OutputStandBy)
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
outputdriversfunctionnormally.
SFE
Azerotoone transitioninthis bitstarts the frame evaluationprocedure. Whenthe CFEbitinthe FAR
registerchangesfromzerotoone,theevaluationprocedurestops. Tostartanotherfameevaluation
cycle,setthisbittozeroforatleastoneframe.
(StartFrameEvaluation)
1-0
Unused
Mustbezerofornormaloperation.
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TABLE 7ꢀRAME ALIGNMENT REGISTER (ꢀAR) BITS
Read/WriteAddress:
ResetValue:
02H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bit
15-13 Unused
Name
Description
Mustbezerofornormaloperation.
12
CFE
WhenCFE=1,theframeevaluationiscompletedandbitsFD10toFD0bitscontainsavalidframealignment
(CompleteFrameEvaluation) offset. This bitis resettozero, whenSFEbitinthe IMSregisteris changedfrom1to0.
11
FD11
(Frame Delay Bit 11)
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0
(Frame DelayBits)
The binaryvalue expressedinthese bits refers tothe measuredinputoffsetvalue. These bits are restto
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[10:0] = 06
H)
(FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[10:0] = 09
H)
(FD11 = 1, sample at CLK HIGH phase)
5711 drw07
Figure 4. Example for Frame Alignment Measurement
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TABLE 8ꢀRAME INPUT OꢀꢀSET REGISTER (ꢀOR) BITS
Read/WriteAddress:
03H for FOR0 register,
04H for FOR1 register,
05H for FOR2 register,
06H for FOR3 register,
0000H forallFORregisters.
ResetValue:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR0 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR1 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR2 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 Register
Name(1)
Description
OFn2, OFn1, OFn0
(OffsetBits2,1&0)
These three bits define howlongthe serialinterface receivertakes torecognize andstore bit0fromthe RXinputpin:i.e., to
startanewframe.Theinputframeoffsetcanbeselectedto+4.5clockperiodsfromthepointwheretheexternalframepulse
inputsignalis appliedtothe F0i inputofthe device. See Figure 5.
DLEn
(DataLatchEdge)
ST-BUS® mode:
GCImode:
DLEn=0, ifclockrisingedge is atthe ¾pointofthe bitcell.
DLEn=1, ifwhenclockfallingedge is atthe ¾ofthe bitcell.
DLEn=0,ifclockfallingedgeis atthe¾pointofthebitcell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
NOTE:
1. n denotes an input stream number from 0 to 15.
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TABLE 9OꢀꢀSET BITS (Oꢀn2, Oꢀn1, Oꢀn0, DLEn) & ꢀRAME DELAY BITS
(ꢀD11,ꢀD2-0)
MeasurementResultfrom
FrameDelayBits
Corresponding
OffsetBits
InputStream
Offset
FD11
FD2
0
FD1
0
FD0
0
OFn2
OFn1
OFn0
DLEn
Noclockperiodshift(Default)
+0.5clockperiodshift
+1.0clockperiodshift
+1.5clockperiodshift
+2.0clockperiodshift
+2.5clockperiodshift
+3.0clockperiodshift
+3.5clockperiodshift
+4.0clockperiodshift
+4.5clockperiodshift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
ST-BUS F0i
CLK
RX Stream
RX Stream
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
Bit 7
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 7
RX Stream
RX Stream
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
RX Stream
RX Stream
RX Stream
RX Stream
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
Bit 0
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
5711 drw08
Figure 5. Examples for Input Offset Delay Timing
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TABLE10CONNECTIONMEMORYBITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LPBK V/C
PC
CCO
OE
SAB3 SAB2 SAB1 SAB0
0
0
CAB4 CAB3 CAB2 CAB1 CAB0
Bit
Name
Description
15
LPBK
When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
operations,setthedelayoffsetregisterbitsOFn[2:0]tozeroforthestreamswhichareintheloopbackmode.
(Per Channel Loopback)
14
V/C
This bitis usedtoselectbetweenthe variable (LOW)andconstantdelay(HIGH)mode ona
per-channelbasis.
(Variable/Constant
Throughput Delay)
13
PC
When1,thecontentsoftheconnectionmemoryareoutputonthecorrespondingoutputchannelandstream.
Onlythe lowerbyte (bit7–bit0)willbe outputtothe TXoutputpins. When0, the contents ofthe connection
memoryarethedatamemoryaddressoftheswitchedinputchannelandstream.
(ProcessorChannel)
12
11
CCO
This bitis outputonthe CCOpinone channelearly. The CCObitforstream0is outputfirst.
(ControlChannelOutput)
OE
This bitenables the TXoutputdrivers ona per-channelbasis. When1, the outputdriverfunctions
normally.When0,theoutputdriverisinahigh-impedancestate.
(OutputEnable)
10-8,7(1) SAB3-0
(SourceStreamAddressBits)
Unused
4-0(1) CAB4-0
(SourceChannelAddressBits)
The binaryvalue is the numberofthe data streamforthe source ofthe connection.
(1)
6,5
Mustbezerofornormaloperation.
The binary value is the number of the channel for the source of the connection.
NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, bits 6-5, CAB4 - CAB0) are output on the
output channel and stream associated with this location.
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INSTRUCTION REGISTER
JTAGSUPPORT
In accordance with the IEEE 1149.1 standard, the IDT72V70200 uses
public instructions. The IDT72V70200 JTAG Interface contains a two-bit
instructionregister.Instructionsareseriallyloadedintotheinstructionregister
fromtheTDIwhentheTAPControllerisinitsshifted-IRstate.Subsequently,
theinstructionsaredecodedtoachievetwobasicfunctions:toselectthetestdata
registerthatmayoperatewhiletheinstructioniscurrent,andtodefinetheserial
testdataregisterpath,whichisusedtoshiftdatabetweenTDIandTDOduring
dataregisterscanning. SeeTablebelowforInstructiondecoding.
TheIDT72V70200JTAGinterfaceconformstotheBoundary-Scanstan-
dardIEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechnique
called Boundary-Scan Test (BST). The operation of the boundary-scan
circuitryis controlledbyanexternaltestaccess port(TAP)Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V70200.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovides theclockforthetestlogic.TheTCKdoes notinterferewith
anyon-chipclockandthusremainindependent.TheTCKpermitsshiftingoftest
data into or out of the Boundary-Scan register cells concurrently with the
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•TestMode SelectInput(TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse.This pinis internallypulledtoVccwhenitis not
driven from an external source.
Value Instruction
000 EXTEST
001 EXTEST
Function
SelectBoundaryScanRegister
SelectBoundaryScanRegister
010 Sample/preload SelectBoundaryScanRegister
011 Sample/preload SelectBoundaryScanRegister
100 Sample/preload SelectBoundaryScanRegister
101 Sample/preload SelectBoundaryScanRegister
110 Bypass
111 Bypass
SelectBypassRegister
SelectBypassRegister
•Test Data Input (TDI)
Serialinputdataappliedtothisportisfedeitherintotheinstructionregister
orintoatestdataregister,dependingonthesequencepreviouslyappliedto
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internallypulledtoVccwhenitis notdrivenfromanexternalsource.
•TestDataOutput(TDO)
Depending on the sequence previously applied to the TMS input, the
contentsofeithertheinstructionregisterordataregisterareseriallyshiftedout
towardstheTDO.ThedataoutoftheTDOisclockedonthefallingedgeofthe
TCKpulses.Whennodataisshiftedthroughtheboundaryscancells,theTDO
driverissettoahighimpedancestate.
JTAG Instruction Register Decoding
TESTDATAREGISTER
AsspecifiedinIEEE1149.1,theIDT72V70200JTAGInterfacecontainstwo
testdataregisters:
•The Boundary-Scan register
TheBoundary-ScanregisterconsistsofaseriesofBoundary-Scancells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V70200core
logic.
•The Bypass Register
•Test Reset (TRST)
ResettheJTAGscanstructure.This pinis internallypulledtoVCC.
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bit
pathfromTDItoitsTDO.TheIDT72V70200boundaryscanregistercontains
118bits.Bit0inTable11BoundaryScanRegisteris thefirstbitclockedout.
Allthree-stateenablebitsareactivehigh.
15
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TABLE 11 BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to bit 117
Boundary Scan Bit 0 to bit 117
Device Pin
Three-State
Control
Output
Input
Scan Cell
76
Device Pin
Three-State
Output
Input
Scan Cell
Control
Scan Cell
Scan Cell
A4
A3
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
ODE
CCO
DTA
D15
D14
D13
D12
D11
D10
D9
0
2
1
3
77
A2
78
4
5
A1
79
6
7
A0
80
8
9
IC
81
10
12
14
11
13
15
RESET
CLK
FE
82
83
84
16
F0i
85
17
18
19
21
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
TX15
TX14
TX13
TX12
TX11
TX10
TX9
TX8
86
87
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
22
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
68
69
70
71
72
73
74
75
88
89
90
91
92
93
94
D8
95
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
IM
96
97
98
99
100
101
102
104
106
108
110
112
114
116
103
105
107
109
111
113
115
117
AD/ALE
CS
R/W / WR
DS/RD
A7
A6
A5
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ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
VIH
Parameter
Min.
3.0
Typ.
Max. Units
VCC
Vi
SupplyVoltage
-0.3
5.0
5.5
20
V
V
Positive Supply
3.6
VCC
5.5
V
V
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
GND -0.3
Input HIGH Voltage (3.3V)
Input HIGH Voltage (5.0V)
InputLOWVoltage
2.0
IO
mA
°C
W
VIH
2.0
V
TS
-65
+125
1
VIL
GND
-40
0.8
V
PD
PackagePowerDissapation
TOP
OperatingTemperature
Commercial
+85
°C
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
NOTE:
1.Voltagesarewithrespecttogroundunlessotherwisestated.
DCELECTRICALCHARACTERISTICS
Symbol
Characteristics
Min.
Typ.
Max.
10
Units
mA
µA
µA
pF
(1)
ICC
SupplyCurrent
@ 2.048 Mb/s
7
(2)
IIL
InputLeakage(inputpins)
InputLeakage(I/Opins)
InputPinCapacitance
High-impedanceLeakage
OutputHIGHVoltage
OutputLOWVoltage
OutputPinCapacitance
15
IBL
CI
50
10
IOZ
VOH
VOL
CO
5
µA
V
2.4
0.4
10
V
pF
NOTE:
1. Outputs Unloaded.
2. For TDI, TMS, and TRST pins, the maximum leakage current is 50µA.
Test Point
VCC
R
L
Output
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
Pin
S
2
S
1
C
L
S2 is switched to VCC or GND when testing
outputlevelsorhighimpedancestates.
GND
GND
5711 drw09
Figure 6. Output Load
17
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - ꢀRAME PULSE AND CLK
Symbol
tFPW
tFPS
tFPH
tCP
Characteristics
Min.
Typ.
Max.
Units
ns
Frame Pulse Width (ST-BUS®, GCI) Bit rate = 2.048 Mb/s
Frame Pulse Setup time before CLK falling (ST-BUS® or GCI)
Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI)
26
295
5
ns
10
ns
CLK Period
Bit rate = 2.048 Mb/s
Bit rate = 2.048 Mb/s
Bit rate = 2.048 Mb/s
190
85
300
150
150
10
ns
tCH
CLK Pulse Width HIGH
CLK Pulse Width LOW
ClockRise/FallTime
ns
tCL
85
ns
tr,tf
ns
AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1)
Symbol
tSIS
Characteristics
Min.
0
Typ.
Max.
Unit
ns
Test Conditions
RXSetupTime
tSIH
RXHoldTime
10
ns
tSOD
TX Delay – Active to Active
30
40
ns
ns
CL = 30pF
CL = 200pF
tDZ
tZD
TX Delay – Active to High-Z
TX Delay – High-Z to Active
Output Driver Enable (ODE) Delay
CCO Output Delay
32
32
32
ns
ns
ns
RL = 1KΩ, CL = 200pF
RL = 1KΩ, CL = 200pF
RL = 1KΩ, CL = 200pF
tODE
tXCD
30
40
ns
ns
CL = 30pF
CL = 200pF
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
18
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
t
FPW
F0i
t
CH
t
FPS
t
r
tf
t
FPH
t
CL
t
CP
CLK
t
SOD
(1)
TX
RX
Bit 0, Last Ch
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
t
SIS
t
SIH
(1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
Bit 0, Last Ch
5711 drw10
Figure 7. ST-BUS® Timing
NOTE:
1. last channel = ch 31.
t
FPW
F0i
t
CL
t
CH
t
FPS
t
FPH
t
r
tf
t
CP
CLK
t
SOD
Bit 7, Last Ch(1)
Bit 7, Last Ch(1)
TX
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
t
SIS
t
SIH
RX
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
5711 drw11
Figure 8. GCI Timing
NOTE:
1. last channel = ch 31.
CLK
(ST-BUS or
WFPS mode)
CLK
(GCI mode)
tDZ
VALID DATA
TX
TX
tZD
ODE
TX
VALID DATA
tODE
tODE
t
XCD
VALID DATA
CCO
5711 drw13
5711 drw12
Figure 10. Output Driver Enable (ODE)
Figure 9. Serial Output and External Control
19
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
Symbol
tALW
tADS
Parameter
Min.
20
3
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
ALE Pulse Width
AddressSetupfromALEfalling
Address HoldfromALEfalling
RD Active afterALEfalling
Data SetupfromDTA LOWonRead
CS Hold after RD/WR
tADH
3
tALRD
tDDR
3
5
CL = 150pF
tCSRW
tRW
5
RDPulseWidth(FastRead)
CS Setup from RD
45
0
tCSR
(1)
tDHR
DataHoldafterRD
10
45
3
20
CL = 150pF, RL = 1K
tWW
WRPulseWidth(FastWrite)
WRDelayafterALEfalling
CS Setup from WR
tALWR
tCSW
tDSW
tSWD
tDHW
tAKD
0
DataSetupfromWR(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldafterWR Inactive
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
20
122
5
43/43
760/750
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
t
ALW
ALE
tADS
tADH
AD0-AD7
D8-D15
DATA
ADDRESS
tALRD
tCSRW
CS
RD
tDHR
tCSR
tRW
t
WW
tDHW
tCSW
tDSW
WR
tAKH
tDDR
t
ALWR
tSWD
tAKD
DTA
5711 drw14
Figure 11. Multiplexed Bus Timing (Intel Mode)
20
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MULTIPLEXEDBUSTIMING(MOTOROLA)
Symbol
tASW
tADS
Parameter
Min.
20
3
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
ALE Pulse Width
AddressSetupfromASfalling
Address HoldfromASfalling
Data SetupfromDTA LOWonRead
CS HoldafterDSfalling
tADH
3
tDDR
5
CL = 150pF
tCSH
0
tCSS
CS Setup from DS rising
DataHoldafterWrite
0
tDHW
tDWS
tSWD
tRWS
tRWH
5
DataSetupfromDS–Write(FastWrite)
ValidData DelayonWrite (SlowWrite)
R/W Setup from DS Rising
R/W Hold from DS Rising
DataHoldafterRead
20
122
20
60
5
(1)
tDHR
10
10
CL = 150pF, RL = 1K
tDSH
tAKD
DS Delay after AS falling
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
43/43
760/750
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tRWH
tRWS
R/W
tASW
tDSH
AS
tADS
tDHW
tSWD
tADH
tDWS
AD0-AD7
D8-D15
WR
ADDRESS
DATA
tDHR
DATA
AD0-AD7
D8-D15
RD
ADDRESS
tCSS
tCSH
CS
tDDR
tAKD
tAKH
DTA
5711 drw15
Figure 12. Multiplexed Bus Timing (Motorola Mode)
21
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MOTOROLANON-MULTIPLEXEDBUSMODE
Symbol
tCSS
Parameter
Min.
0
Typ.
Max.
Units
ns
Test Conditions
CS Setup from DS falling
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
R/W Hold after DS Rising
Address HoldafterDSRising
DataSetupfromDTALOWonRead
DataHoldonRead
tRWS
tADS
10
2
ns
ns
tCSH
0
ns
tRWH
tADH
2
ns
2
ns
tDDR
2
ns
CL = 150pF
tDHR
10
0
20
ns
CL = 150pF, RL = 1K
tDSW
tSWD
tDHW
tAKD
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
ns
122
ns
5
ns
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
43/43
760/750
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tCSS
tCSH
tCSS
tCSH
CS
tRWS
tRWH
tRWS
tRWH
R/W
tADH
tADS
tADH
tADS
A0-A7
VALID READ ADDRESS
VALID WRITE ADDRESS
tSWD
t
DSW
t
DHR
t
DHW
AD0-AD7/
D8-D15
VALID WRITE
DATA
VALID READ DATA
DDR
t
tAKH
tAKD
tAKH
tAKD
DTA
5711 drw16
Figure 13. Motorola Non-Multiplexed Asyncrounous Bus Timing
22
IDT72V702003.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
CLK GCI
CLK ST-BUS
t
DSS
tDSS
t
DSPW
DS
CS
tCSS
tCSS
tCSH
tCSH
tRWH
tRWS
tRWH
tRWS
R/W
tADH
tADS
tADH
tADS
VALID READ
ADDRESS
VALID WRITE
ADDRESS
A0-A7
tSWD
tDHW
tDHR
VALID WRITE
DATA
VALID READ
DATA
AD0-AD7/
D8-D15
tDDR
tCKAK
tCKAK
tAKH
tAKH
DTA
5711 drw17
Figure 14. Motorola Non-Multiplexed Syncrounous Bus Timing
23
ORDERINGINꢀORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
Commercial (-40°C to +85°C)
BLANK
J
Plastic Leaded Chip Carrier (PLCC, J84-1)
Ball Grid Array (BGA, BC100-1)
Plastic Quad Flatpack (PQFP, PQ100-2)
Thin Quad Flat Pack (TQFP, PN100-1)
BC
PQF
PF
72V70200
512 x 512
3.3V Time Slot Interchange Digital Switch
5711 drw18
DATASHEETDOCUMENTHISTORY
5/19/2000
8/15/2000
9/22/2000
1/04/2001
1/25/2001
08/06/2001
pgs. 1, 3, 17 and 23.
pgs. 1, 2, 3, 5, 12 and 23.
pgs. 3, 12 and 17.
pgs. 6, 11, 17, 19, 20, 21 and 22.
pgs. 17 and 22.
pgs. 4, 10, 15, and 22.
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800-345-7015 or 408-727-6116
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408-330-1753
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www.idt.com
24
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