IDT72V71643 [IDT]
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING; 3.3伏时隙交换数字交换速率匹配
| 型号： | IDT72V71643 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING |
| 文件： | 总30页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING
IDT72V71643
4,096 x 4,096
•
•
Internal Loopback for testing
Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V tolerant inputs and TTL compatible outputs
FEATURES:
•
•
•
Up to 32 serial input and output streams
Maximum 4,096 x 4,096 channel non-blocking switching
Accepts data streams at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s
•
•
•
•
•
•
•
•
•
•
•
Rate matching capability: Mux/Demux mode and Split mode
Output Enable Indication Pins
Per-channel Variable Delay mode for low-latency applications
DESCRIPTION:
The IDT72V71643 has a maximum non-blocking switch capacity of
Per-channel Constant Delay mode for frame integrity applications 4,096x4,096channelswithdatarates at 2.048Mb/s,4.096Mb/s,8.192Mb/s
Automatic identification of ST-BUS® and GCI serial streams
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high-impedance output control
Per-channel Processor mode to allow microprocessor writes to
TXstreams
or16.384Mb/s. With32inputsand32outputs,avarietyofratecombinations
is supported, under either Mux/Demux mode or Split mode, to allow for
switchingbetweenstreamsofdifferentdatarates.
Outputenableindicationsareprovidedthroughoptionalpins(onepinper
outputstream, only16outputstreams canbe usedinthis mode)tofacilitate
externaldatabuscontrol.
•
•
•
Direct microprocessor access to all internal memories
Memory block programming for quick setup
IEEE-1149.1 (JTAG) Test Port
For applications requiring 32 streams and 32 per-stream Output Enable
indicators,thereisalsoanAllOutputEnableFeature.
FUNCTIONAL BLOCK DIAGRAM
TRST
Vcc GND
TMS TDI
TDO TCK
ODE
RESET
Test Port
RX0
TX0
RX1
TX1
Loopback
RX2
RX3
TX2
TX3
RX4
TX4
RX5
TX5
RX6
TX6
RX7
RX8
TX7
Output
MUX
TX8
TX9
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
TX10
TX11
TX12
Data Memory
TX13
TX14
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
TX15
TX16/OEI0
TX17/OEI1
TX18/OEI2
TX19/OEI3
TX20/OEI4
TX21/OEI5
TX22/OEI6
TX23/OEI7
TX24/OEI8
TX25/OEI9
TX26/OEI10
TX27/OEI11
TX28/OEI12
TX29/OEI13
TX30/OEI14
TX31/OEI15
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
5902 drw01
CLK
FE/ WFPS
HCLK
R/W A0-A14
D0-D15
F0i
DS
CS
DTA
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.
MAY 2002
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5902/6
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
RX0
CLK
F0i
RX1
ODE
RX3
RX2
RESET
TDI
RX6
RX5
RX4
VCC
VCC
VCC
VCC
A14
D15
D9
TX1
TX0
RX7
VCC
GND
GND
GND
GND
VCC
D6
TX4
TX3
TX2
VCC
GND
GND
GND
GND
VCC
D3
TX7
TX6
TX5
VCC
GND
GND
GND
GND
VCC
D0
RX10
RX9
RX12
RX13
RX11
VCC
VCC
VCC
VCC
VCC
GND
RX15
RX14
TX8
TX10
TX9
TX11
TX12
TX14
RX17
B
C
FE/HCLK
WFPS
TCK
RX8
TX13
RX16
RX20
RX23
D
E
TMS
TD0
DS
VCC
GND
GND
GND
GND
VCC
TX15
RX19
RX22
TRST
R/W
A2
RX21
RX18
F
CS
G
A0
A3
A1
A4
TX16/
OEI10
TX17/
OEI1
TX18/
OEI2
H
J
A5
TX19/
OEI3
TX20/
OEI4
TX21/
OEI5
A6
A7
A8
TX22/
OEI6
RX24
RX25
RX28
RX31
11
TX23/
OEI7
K
L
DTA
A9
A10
A12
D14
2
TX29/
OEI13
TX26/
OEI10
RX26
RX29
RX30
RX27
A11
A13
1
D12
D13
3
D4
TX30/
OEI14
TX27/
OEI11
TX24/
OEI8
D11
D10
4
D7
D8
5
D1
D2
7
M
TX31/
OEI15
TX28/
OEI12
TX25/
OEI9
D5
6
8
9
10
12
5902 drw02
BGA: 1mm pitch, 13mm x 13mm (BC144-1, order code: BC)
TOP VIEW
NOTES:
1. IC - Internal Connection, tie to Ground for normal operation.
2. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
2
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PINCONFIGURATIONS(CONTINUED)
109
VCC
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
TX11
TX24/OEI8
TX25/OEI9
GND
TX26/OEI10
TX27/OEI11
VCC
TX28/OEI12
TX29/OEI13
GND
TX30/OEI14
TX31/OEI15
VCC
D0
D1
GND
D2
D3
VCC
D4
D5
GND
D6
D7
VCC
D08
D09
GND
D10
D11
VCC
D12
D13
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
TX10
GND
TX9
TX8
VCC
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
GND
TX7
TX6
VCC
TX5
TX4
GND
TX3
TX2
VCC
TX1
TX0
GND
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
VCC
138
139
140
141
142
143
144
GND
D14
D15
39
38
37
5902 drw03
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
NOTES:
1. IC - Internal Connection, tie to Ground for normal operation.
2. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
3
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
SYMBOL
GND
NAME
I/O
DESCRIPTION
Ground.
Vcc
Ground Rail.
Vcc
+3.3 Volt Power Supply.
TX0-15
TX Output 0 to 15
(Three-state Outputs)
O
O
Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,
or 16.384 Mb/s.
TX16-31/ TX Output 16 to 31/
OEI0-15 Output Enable
Indication 0 to 15
When all 32 output streams are selected via control register, these pins (TX16-31) are output streams 16 to 31
and may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s. When output enable
indicationfunctionisselected,thesepins(OEI0-15)reflecttheactiveorthree-statestatusforthecorresponding,
(TX0-15) output streams.
(Three-state Outputs)
RX0-31 RX Input 0 to 31
I
I
I
Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,
or 16.384 Mb/s.
F0i
Frame Pulse
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS® and GCI specifications.
FE/HCLK Frame Evaluation/
HCLK Clock
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
(4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.
CLK
TMS
Clock
I
I
Serial clock for shifting data in/out on the serial streams (RX/TX 0-31).
Test Mode Select
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
TDI
Test Serial Data In
Test Serial Data Out
I
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
TCK
Test Clock
Test Reset
I
I
Provides the clock to the JTAG test logic.
TRST
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V71643 is in the normal functional mode.
RESET
Device Reset
I
I
Thisinput(activeLOW)putstheIDT72V71643initsresetstatethatclearsthedeviceinternalcounters,registers
and brings TX0-31 and microport data outputs to a high-impedance state. In normal operation, the RESET
pin must be held LOW for a minimum of 100ns to reset the device.
WFPS
Wide Frame Pulse Select
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS® /GCI mode.
DS
R/W
CS
A0-14
D0-15
DTA
Data Strobe
I
I
I
I
This active LOW input works in conjunction with CS to enable the read and write operations.
This input controls the direction of the data bus lines during a microprocessor access.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V71643.
These pins allow direct access to Connection Memory, Data Memory and internal control registers.
Read/Write
Chip Select
Address Bus 0 to 14
Data Bus 0-15
I/O These pins are the data bits of the microprocessor port.
Data Transfer
Acknowledgment
O
This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives
HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up
resistor is required to hold a HIGH level when the pin is in high-impedance.
ODE
Output Drive Enable
I
This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the IMS register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the Connection Memory.
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IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
OPERATINGMODES
DESCRIPTION(CONTINUED)
InadditiontoRegularmodewhereinputandoutputstreamsareoperating
atthesamerate,theIDT72V71643incorporatesaratematchingfunctionintwo
differentmodes:SplitmodeandMux/Demuxmode.InSplitmodesomeofthe
inputstreamsaresetatonerate,whileothersaresettoanotherrate. Bothinput
andoutputstreamsaresymmetrical. InMux/Demuxmode,allinputstreams
areoperatingatthesamerate,whileoutputstreamsareoperatingatadifferent
rate. Allconfigurations arenon-blocking. Thesetwomodes canbeentered
bysettingthe DR3-0bits inthe ControlRegister, see Table 5.
The IDT72V71643 is capable of switching up to 4,096 x 4,096 channels
withoutblocking. Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per channel basis.
The serial input streams (RX) and serial output streams (TX) of the
IDT72V71643canberunupto16.384Mb/sallowing256channelsper125µs
frame. Dependingontheinputandoutputdataratesthedevicecansupport
upto32serialstreams.
Withtwomainoperatingmodes,ProcessormodeandConnectionMode,
theIDT72V71643caneasilyswitchdatafromincomingserialstreams(Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessormode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
Withthreemainconfigurationmodes,Regular,Mux/Demux,andSplitmode
the IDT72V71643 is designed to work in a mixed data-rate environment. In
Mux/Demuxmode,alloftheinputstreamsworkatonedatarateandtheoutput
streamsatanother. Dependingontheconfiguration,moreorlessserialstreams
willbeavailableontheinputsoroutputstomaintainanon-blockingswitch. In
SplitMode,halfoftheinputstreamsaresetatonerate,whiletheotherhalfare
settoanotherrate. Inthismode,bothinputandoutputstreamsaresymmetrical.
Withdatacomingfrommultiplesourcesandthroughdifferentpaths,data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V71643
hasaframeevaluationfeaturetoallowindividualstreamstobeoffsetfromthe
framepulseinhalfclock-cycleintervalsupto+4.5clockcyclesforspeedsup
to8Mb/sor+2.5clockcyclesfor16Mb/s.(SeeTable8formaximumallowable
skew).
OUTPUTIMPEDANCECONTROL
Inordertoputallstreamsinthree-state,allper-channelthree-statecontrol
bitsintheConnectionMemoryareset(MOD0andMOD1=1)orboththeODE
pinandtheOSBbitoftheControlRegistermustbezero. Ifanycombination
otherthan0-0,fortheODEpinandtheOSBbit,isused,thethree-statecontrol
ofthestreamswillbelefttothestateoftheMOD1andMOD0bitsoftheConnection
Memory. The IDT72V71643 incorporates a memory block programming
featuretofacilitatethree-statecontrolafterreset.SeeTable1forOutputHigh-
ImpedanceControl.
SERIAL DATA INTERFACE TIMING
Whena16Mb/sserialdatarateisrequired,themasterclockfrequency
willbe runningat16.384MHzresultingina single-bitperclock. Forallother
cases,2Mb/s,4Mb/s,and8Mb/s,themasterclockfrequencywillbetwicethe
fastestdatarateontheserialstreams.UseTable5todetermineclockspeed
andDR3-0bitsintheControlRegistertosetupthedevice.TheIDT72V71643
provides two different interface timing modes, ST-BUS® or GCI. The
IDT72V71643automaticallydetectsthepresenceofaninputframepulseand
identifies itas eitherST-BUS® orGCI.
The IDT72V71643 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface andautomaticST-BUS®/GCIsensingtoshortensetuptime, aidin
debuggingandeaseuseofthedevicewithoutsacrificingcapabilities.
In ST-BUS®, when running at 16.384MHz, data is clocked out on the
fallingedgeandisclockedinonthesubsquentrising-edge. Atallotherdata
rates,therearetwoclockcycles perbitandeverysecondfallingedgeofthe
masterclockmarksabitboundaryandthedataisclockedinontherisingedge
ofCLK, three quarters ofthe wayintothe bitcell. See Figure 17fortiming.
In GCI format, when running at 16.384MHz, data is clocked out on the
risingedgeandis clockedinonthesubsquentfallingedge. Atallotherdata
rates, there are twoclockcycles perbitand everysecondrisingedge ofthe
masterclockmarksthebitboundaryanddataisclockedinonthefallingedge
FUNCTIONALDESCRIPTION
DATAANDCONNECTIONMEMORY
AlldatathatcomesinthroughtheRXinputsgothroughaserial-to-parallel
conversionbeforebeingstoredintointernalDataMemory.The8KHzframe
pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
addresstheinputchannelsinDataMemory. TheDataMemoryisonlywritten
bythedevicefromtheRXstreamsandcanbereadfromeithertheTXstreams
ofCLKatthree quarters ofthe wayintothe bitcell. See Figure 18fortiming.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Although input data is synchronous, delays can be caused by variable path
serialbackplanesandvariablepathlengths,whichmaybeimplementedinlarge
centralizedanddistributedswitchingsystems.Becausedataisoftendelayed
thisfeatureisusefulincompensatingfortheskewbetweenclocks.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR,Table7).Theframeoffsetshownisafunction
ofthedatarate,andcanbeaslargeas+4.5masterclock(CLK)periodsforward
witharesolutionof½clockperiod.Todeterminethemaximumoffsetallowed
see Table 8.
orthemicroprocessor.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(DataMemory)orfromthemicroprocessor(ConnectionMemory).Inthecase
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
tospecifyastreamandchanneloftheinput.TheConnectionMemoryissetup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessormode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
byte(8leastsignificantbits)oftheConnectionMemoryisoutputeveryframe
untilthemicroprocessorchangesthedataormodeofthechannel.Byusingthis
Processormodecapability,themicroprocessorcanaccessinputandoutput
time-slotsonaperchannelbasis.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
TheIDT72V71643providestheframeevaluation(FE)inputtodetermine
differentdatainputdelayswithrespecttotheframepulseF0i.Settingthestart
frameevaluation(SFE)bitlowforatleastoneframestartsameasurementcycle.
ThemostsignificantbitsoftheConnectionMemoryareusedtocontrolper
channelfunctionssuchasProcessormode,ConstantorVariableDelaymode,
three-stateofoutputdrivers,andtheLoopbackfunction.
5
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
delayequatesto12outputchanneltimeslots.SeeFigure2forthisexampleand
otherexamplesofminimumdelaytoguaranteetransmissioninthesameframe.
When the SFE bit in the Control Register is changed from low to high, the
evaluationstarts.Twoframeslater,thecompleteframeevaluation(CFE)bitof
theframealignmentregister(FAR)changesfromlowtohightosignalthatavalid
offsetmeasurementisreadytobereadfrombits0to11oftheFARregister.The
SFEbitmustbesettozerobeforeanewmeasurementcycleisstarted.
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(FE)
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
CONSTANT DELAY MODE (MOD1-0 = 0x1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipleDataMemorybuffer.Inputchanneldataiswritteninto
the Data Memory buffers during frame n will be read out during frame n+2.
Figure 1shows examples ofConstantDelaymode.
SeeTable6andFigure6forthedescriptionoftheframealignmentregister.
MICROPROCESSORINTERFACE
MEMORYBLOCKPROGRAMMING
TheIDT72V71643providesuserswiththecapabilityofinitializingtheentire
ConnectionMemoryblockintwoframes.Tosetbits15to13ofeveryConnection
Memorylocation,firstprogramthedesiredpatterninbits9to7oftheControl
Register.
Setting the memory block program (MBP) bit of the control register high
enablestheblockprogrammingmode.Whentheblockprogrammingenable
(BPE)bitoftheControlRegisterissettohigh,theblockprogrammingdatawill
beloadedintothebits15to13ofeveryConnectionMemorylocation.Theother
ConnectionMemorybits(bit12tobit0)areloadedwithzeros.Whenthememory
blockprogrammingiscomplete,thedeviceresetstheBPEbittozero.
TheIDT72V71643’smicroprocessorinterfacelookslikeastandardRAM
interfacetoimproveintegrationintoasystem.Witha15-bitaddressbusanda
16-bitdatabus,readandwritesaremappeddirectlyintoDataandConnection
memoriesandrequireonlyoneMasterClockcycletoaccess.Byallowingthe
internal memories to be randomly accessed in one cycle, the controlling
microprocessorhas more time tomanage otherperipheraldevices andcan
moreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table2showsthemappingoftheaddressesintointernalmemoryblocks,
Table3showstheControlRegisterinformationandFigure13andFigure14
showsasynchronousandsynchronousmicroprocessoraccesses.
LOOPBACKCONTROL
MEMORYMAPPING
Theloopbackcontrol(LPBK)bitofeachConnectionMemorylocationallows
theTXoutputdatatobeloopedbackedinternallytotheRXinputfordiagnostic
purposes.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,datafromTXnchannelmroutesto
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. Forproperper-channelloopbackoperation, thecontents offrame
delayoffsetregistersmustbesettozeroandthedevicemustbeinregularswitch
mode (DR3-0 = 0x0, 0x1 or 0x2).
The address bus on the microprocessor interface selects the internal
registersandmemoriesoftheIDT72V71643.Thetwomostsignificantbitsofthe
addressselectbetweentheregisters,DataMemory,andConnectionMemory.
IfA14andA13areHIGH,A12-A0areusedtoaddresstheDataMemory(Read
Only).IfA14isHIGHandA13isLOW,A12-A0areusedtoaddressConnection
Memory(Read/Write).IfA14isLOWandA13isHIGHA12-A9areusedtoselect
theControlRegister,FrameAlignmentRegister,andFrameOffsetRegisters.
See Table 2formappings.
CONTROL REGISTER
DELAYTHROUGHTHEIDT72V71643
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigura-
tions sections, after system power-up, the Control Register should be pro-
grammedimmediatelytoestablishthedesiredswitchingconfiguration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit(MBP),theBlockProgrammingData(BPD)bits,theBeginBlockProgram-
mingEnable(BPE),theOutputStandBy(OSB),StartFrameEvaluation(SFE),
and Data Rate Select bits (DR 3-0). As explained in the Memory Block
Programmingsection,theBPEbeginstheprogrammingiftheMBPbitisenabled.
This allows the entire ConnectionMemoryblocktobe programmedwiththe
BlockProgrammingDatabits.
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesonaper-channelbasis.Forvoiceapplications,Variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,Constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
The delay through the device varies according to the type of throughput
delayselectedintheMOD1andMOD0bits oftheConnectionMemory.
CONNECTIONMEMORYCONTROL
IftheODEpinortheOSBbitishigh,theMOD1-0bitsofeachConnection
Memory location controls the output drivers. See Table 1 for detail. The
Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the
ConnectionMemory.InProcessorChannelMode,thisallowsthemicroproces-
sortoaccessTXoutputchannels. OncetheMOD1-0bitsareset,thelower8
bits ofthe ConnectionMemorywillbe outputonthe TXserialstreams. Also
controlledintheConnectionMemoryistheVariableDelaymodeorConstant
Delay mode. Each Connection Memory location allows the per-channel
selection between Variable and Constant throughput Delay modes and
Processormode.
VARIABLE DELAY MODE (MOD1-0 = 0x0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destinationserialstreamspeed. Althoughtheminimumdelayachievableis
dependent on the input and output serial stream speed, if data is switched
out+3channelsoftheslowestdatarate,thedatawillbeswitchedoutinthesame
frameexceptiftheinputandoutputdataratesareboth16Mb/s(DR3-0=0x3).
(See Figure 2 for example).
Forexample,giventheinputdatarateis2Mb/sandtheoutputdatarateis
8Mb/s,inputchannelCH0 canbeswitchoutbyoutputchannelCH12. Inthe
aboveexampletheinputstreamsareslowerthantheoutputstreams. Also,for
every2Mb/stimeslottherearefour8Mb/stimeslots,thusathree2Mb/schannel
6
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally actsastheswitchandtheotherasathree-statecontroldevice. SeeFigure8.
loopedbacktotheRXinputchannel(i.e.,RXnchannelmdatacomesfromthe ItisimportanttonoteiftheTSIdeviceisprogrammedforAOEandtheOEIis
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For alsoset, the device willbe inthe AOEmode notOEI.
properper-channelloopbackoperation,thecontentsoftheframedelayoffset
registers mustbe settozeroandthe device mustbe inregularswitchmode
INITIALIZATIONOFTHEIDT72V71643
(DR3-0 = 0x0, 0x1 or 0x2).
Afterpowerup,theIDT72V71643shouldbereset.Duringreset,theinternal
registersareputintotheirdefaultstateandallTXoutputsareputintothree-state.
Afterresethowever,thestateofConnectionMemoryisunknown.Assuch,the
OUTPUT ENABLE INDICATION
TheIDT72V71643hasthecapabilitytoindicatethestateoftheoutputs(active
outputsshouldbeputinhigh-impedancebyholdingtheODElow.WhiletheODE
orthree-state)byenablingthe OutputEnable Indication(OEI)inthe control
islow,themicroprocessorcaninitializethedevice,programtheactivepaths,
register. IntheOEImodehowever,onlyhalfoftheoutputstreamsareavailable.
anddisableunusedoutputsbyprogrammingtheOEbitinConnectionMemory.
Ifthissamecapabilityisdesiredwithall32streams,thiscanbeaccomplished
Once the device is configured, the ODE pin (or OSB bit depending on
byusingtwoIDT72V71643devices. Inonedevice,theAllOutputEnable(AOE)
initialization)canbeswitched.
bitissettoaonewhileintheothertheAOEissettozero. Inthisway,onedevice
7
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE1—OUTPUTHIGH-IMPEDANCECONTROL
MOD1-0 BITS IN
CONNECTION MEMORY
1 and 1
ODE PIN
OSB BIT IN CONTROL
REGISTER
OUTPUT DRIVER
STATUS
PerChannelHigh-Impedance
Don’tCare
Don’tCare
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
0
0
1
1
0
1
0
1
High-Impedance
Enable
Enable
Enable
TABLE 2—INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A14 A13
A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
R
Location
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
STA4 STA3 STA2 STA1 STA0 CH7
CH6
CH5 CH4
CH3 CH2
CH1 CH0
Data Memory
STA4 STA3 STA2 STA1 STA0 CH7
CH6
x
CH5 CH4
CH3 CH2
CH1 CH0
R/W ConnectionMemory
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R/W
R
ControlRegister
FrameAlignRegister
FOR0
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
FOR1
x
FOR2
x
FOR3
x
FOR4
x
FOR5
x
FOR6
x
FOR7
8
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
2 Mb/s → 4 Mb/s
1Frame(125µsec)
DR3-0 = DH
1Frame(125µsec)
1Frame(125µsec)
RX 2 Mb/s
A
• • • •
Q
(1)
(2)
• • • •
TX 4 Mb/s
Q
• • • •
A
2 Mb/s → 16 Mb/s
1Frame(125µsec)
DR3-0 = 9H
1Frame(125µsec)
1Frame(125µsec)
A
• • • •
Q
RX 2 Mb/s
(1)
(2)
• • • •
TX 16 Mb/s
Q
• • • •
A
NOTES:
1. Timeslot Q 2 Frames minimum delay.
2. Timeslot A 3 Frames - 1 output channel period maximum delay.
Figure 1. Constant Delay Mode Examples
(3)
2 Mb/s → 8 Mb/s
DR3-0 = 4H
DR3-0 = CH 2 Mb/s → 8 Mb/s
1 Channel @ 2 Mb/s
A
B
C
D
E
F
RX 2 Mb/s
TX 8 Mb/s
1 Channel @ 8 Mb/s
(1,2)
A
(3)
16 Mb/s → 8 Mb/s
DR3-0 = AH
DR3-0 = FH 16 Mb/s → 8 Mb/s
1 Channel @ 16 Mb/s
RX 16 Mb/s
TX 8 Mb/s
A
B
C
D
E
F
G
H
I
J
1 Channel @ 8 Mb/s
(1,2)
A or B
C or D
(3,4)
16 Mb/s → 16 Mb/s
DR3-0 = 3H
RX 16 Mb/s
A
B
C
D
E
F
G
H
B
I
J
K
A
L
M
N
O
P
Q
R
TX 16 Mb/s
A
B
B
NOTES:
1. If data is switched at least +3 channel periods of the slower data rate, the data will transmit out in the same frame except if the input and output data rates are both 16 Mb/s
(DR3-0 = 0x3).
2. Delay is a function of input channel and output channel combinations, and input and output stream data rate.
3. See switching mode table for input and output speed combinations.
4. When the input and output data rates are both 16 Mb/s, the minimum delay achievable is 6 time slots.
Figure 2. Variable Delay Mode Examples
9
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 3—CONTROL REGISTER (CR) BITS
ResetValue:
4000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
SRS
OEI
OEP
AOE
MBP
0
BPD2 BPD1 BPD0
BPE
OSB
SFE
DR3
DR2
DR1
DR0
Bit
15
14
Name
Description
Reset(SoftwareReset)
OEI
Aone willresetthe device andhave the same effectas ofthe RESETpin. Mustbe zerofornormaloperation.
When1,TX16-31/OEI0-15willbehaveasOEI0-15.Theseoutputswillreflect theactiveorhigh-impedancestateofthecorresponding
(OutputEnableIndication) outputdatastreamsTX0-15.When0,TX16-31/OEI0-15willbehaveasTX16-31andreactinthesamewayasTX0-15.
13
12
11
OEPOL
(OutputEnablePolarity)
When1,aoneonOEIpindenotesanactivestateontheoutputdatastream;zeroonOEIpindenoteshigh-impedancestate.
When0,aonedenoteshigh-impedanceandazerodenotesanactivestate.
AOE
When1,TX0-31willbehaveasOEI0-31accordingly.Theseoutputswillreflecttheactiveorhigh-impedancestateofthe
correspondingoutputdatastreams(TX0-31)inanotherIDT72V71643ifprogrammedidentically.
MBP
When1,theConnectionMemoryblockprogrammingfeatureisreadyfortheprogrammingofConnectionMemoryhighbits,
(Memory Block Program) bit13tobit15.When0,thisfeatureisdisabled.
10
Unused
BPD2-0
Mustbezerofornormaloperation.
9-7
ThesebitscarrythevaluetobeloadedintotheConnectionMemoryblockwheneverthememoryblockprogrammingfeatureis
(BlockProgrammingData) activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents
ofthebitsBPD2-0areloadedintobit15and13oftheConnectionMemory.Bit12tobit0oftheConnectionMemoryaresetto0.
6
BPE
Azerotoonetransitionofthisbitenablesthememoryblockprogrammingfunction.TheBPEandBPD2-0bitsintheCRregister
(BeginBlockProgramming have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the
Enable)
blockprogramming.Aftertheprogrammingfunctionhasfinished,theBPEbitreturnstozerotoindicatetheoperationiscompleted.
WhentheBPE=1,theotherbitinthecontrolregistermustnotbechangedfortwoframestoensureproperoperation.
5
4
OSB
(OutputStandBy)
WhenODE=0andOSB=0,theoutputdriversoftransmitserialstreamsareinhigh-impedancemode.WhenODE=1orOSB=1,
theoutputserialstreamdriversfunctionnormally.
SFE
Azerotoonetransitioninthisbitstartstheframeevaluationprocedure.WhentheCFEbitintheFARregisterchangesfromzero
toone,theevaluationprocedurestops.Tostartanotherframeevaluationcycle,setthisbittozeroforatleastoneframe.
(StartFrameEvaluation)
3-0
DR3-0
Input/Outputdatarateselection.SeeTable5fordetailedprogramming.
TABLE 4—CONNECTION MEMORY BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LPBK MOD1 MOD0 SAB4 SAB3 SAB2 SAB1 SAB0 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
Name
Description
15
LPBK
(PerChannelLoopback)
When1,theRXnchannelmdatacomesfromtheTXnchannelm.Forproperperchannelloopbackoperations,setthedelay
offsetregisterbitsOFn[2:0]tozeroforthestreamswhichareintheloopbackmode.Thisfeatureisofferedonlywhen
DR3-0=0000,0001or0010isselectedviathecontrolregister.
14,13 MOD1-0
(SwitchingModeSelection)
MOD1 MOD0
MODE
0
0
1
1
0
1
0
1
VariableDelaymode
ConstantDelaymode
Processormode
OutputHigh-Impedance
12-8 SAB4-0
Thebinaryvalueisthenumberofthedatastreamforthesourceoftheconnection.UnusedSABbitsmustbezeroforproper
(SourceStreamAddressBits) operation.
7-0 CAB7-0 The binaryvalueis thenumberofthechannelforthesourceoftheconnection.UnusedCABbits mustbezeroforproper
(SourceChannelAddressBits) operation.
10
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 5 — SWITCH MODES
Switching
Mode
ControlBits
DR3 DR2 DR1 DR0
DataRatebits/s
ReceiveStreams TransmitStreams
ClockRate
MHz
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
2 M on RX0-31
4 M on RX0-31
8 M on RX0-31
16 M on RX0-15
2MonTX0-31
4MonTX0-31
8MonTX0-31
16MonTX0-15
4
8
16
16
Regular
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 M on RX0-31
8 M on RX0-7
4 M on RX0-31
8 M on RX0-15
16 M on RX0-3
2 M on RX0-31
16 M on RX0-15
8 M on RX0-31
8 M on TX0-7
2MonTX0-31
8MonTX0-15
4MonTX0-31
2MonTX0-31
16MonTX0-3
8MonTX0-31
16MonTX0-15
16
16
16
16
16
16
16
16
Mux/Demux
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2 M on RX0-15;
8 M on RX16-31
2 M on TX0-15;
8MonTX16-31
16
2 M on RX0-15;
4 M on RX16-31
2 M on TX0-15;
4MonTX16-31
8
Split
4 M on RX0-15;
8 M on RX16-31
4 M on TX0-15;
8MonTX16-31
16
16
8 M on RX0-15;
8 M on TX0-15;
16MonRX16-23
16MonTX16-23
11
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
DR3-0 = 0
H
, 1H
, 2H
DR3-0 = 3H
2 Mb/s → 2 Mb/s, 4 Mb/s → 4 Mb/s, 8 Mb/s → 8 Mb/s
16 Mb/s → 16 Mb/s
RX0
TX0
RX0
TX0
16 Mb/s
16 Mb/s
RX15
RX16
TX15
TX16
2, 4, 8 Mb/s
2, 4, 8 Mb/s
OPEN
RX31
TX31
RX31
TX31
5902 drw04
Figure 3. Regular Switch Mode
16 Mb/s → 2 Mb/s
DR3-0 = 8H
2 Mb/s → 8 Mb/s
DR3-0 = 4H
RX0
TX0
RX0
TX0
16 Mb/s
8 Mb/s
RX3
RX4
TX7
TX8
2 Mb/s
2 Mb/s
OPEN
RX31
TX31
RX31
TX31
5902 drw05
Figure 4. Mux/Demux Mode
8 Mb/s → 8 Mb/s & 16 Mb/s → 16 Mb/s
DR3-0 = FH
2 Mb/s → 8 Mb/s & 8 Mb/s → 8 Mb/s
DR3-0 = CH
RX0
TX0
RX0
TX0
8 Mb/s
8 Mb/s
2 Mb/s
2 Mb/s
RX15
RX16
TX15
TX16
RX15
RX16
TX15
TX16
16 Mb/s
16 Mb/s
RX23
RX24
TX23
TX24
8 Mb/s
RX31
8 Mb/s
OPEN
RX31
TX31
TX31
5902 drw06
Figure 5. Split Mode
12
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 6—FRAME ALIGNMENT REGISTER (FAR) BITS
ResetValue:
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
CFE
FD11 FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15-13 Unused
Willbe zerowhenread.
12
11
CFE (Complete
FrameEvaluation)
WhenCFE=1,theframeevaluationis completedandbits FD10toFD0bits contains avalidframealignmentoffset.This bitis resetto
zero, when SFE bit in the CR register is changed from 1 to 0.
FD11
The fallingedge ofFE(orrisingedge forGCImode)is sampledduringthe CLK-highphase (FD11=1)orduringthe CLK-lowphase
(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0 Thebinaryvalueexpressedinthesebitsreferstothemeasuredinputoffsetvalue.ThesebitsareresttozerowhentheSFEbitofthe
(Frame DelayBits) CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[10:0] = 06
H)
(FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[10:0] = 09
H)
(FD11 = 1, sample at CLK HIGH phase)
5902 drw07
Figure 6. Example for Frame Alignment Measurement
13
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 7— FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value:
0000H forallFORregisters.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32
OF31
OF30
DLE3
OF22
OF21
OF20
DLE2
OF12
OF11
OF10
DLE1
OF02
OF01
OF00
DLE0
FOR0Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72
OF71
OF70
DLE7
OF62
OF61
OF60
DLE6
OF52
OF51
OF50
DLE5
OF42
OF41
OF40
DLE4
FOR1Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112
OF111
OF110
DLE11
OF102
OF101
OF100
DLE10
OF92
OF91
OF90
DLE9
OF82
OF81
OF80
DLE8
FOR2Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF312
OF311
OF310
DLE31
OF142
OF141
OF140
DLE14
OF132
OF131
OF130
DLE13
OF122
OF121
OF120
DLE12
FOR3Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF192
OF191
OF190
DLE19
OF182
OF181
OF180
DLE18
OF172
OF171
OF170
DLE17
OF162
OF161
OF160
DLE16
FOR4Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF232
OF231
OF230
DLE23
OF222
OF221
OF220
DLE22
OF212
OF211
OF210
DLE21
OF202
OF201
OF200
DLE20
FOR5Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF272
OF271
OF270
DLE27
OF262
OF261
OF260
DLE26
OF252
OF251
OF250
DLE25
OF242
OF241
OF240
DLE24
FOR6Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF312
OF311
OF310
DLE31
OF302
OF301
OF300
DLE30
OF292
OF291
OF290
DLE29
OF282
OF281
OF280
DLE28
FOR7Register
Name(1)
Description
OFn2, OFn1, OFn0
(Offset Bits 2, 1 & 0)
Thesethreebitsdefinehowlongtheserialinterfacereceivertakestorecognizeandstorebit0fromtheRXinputpin:i.e.,tostartanewframe.
Theinputframeoffsetcanbeselectedto+4.5clockperiodsfromthepointwheretheexternalframepulseinputsignalisappliedtotheF0i
inputofthe device. See Figure 7.
DLEn
ST-BUS® mode:
(DataLatchEdge)
DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.
GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
NOTE:
1. n denotes an input stream number from 0 to 31.
14
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE8— MAXIMUM ALLOWABLE SKEW
Switching
Mode
ControlBits
DataRatebits/s
TransmitStreams
Maximum
allowableskew
DR3
DR2
DR1
DR0
ReceiveStreams
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
2 M on RX0-31
4 M on RX0-31
8 M on RX0-31
16 M on RX0-15
2MonTX0-31
4MonTX0-31
8MonTX0-31
16MonTX0-15
+4.5
+4.5
+4.5
+2.5
Regular
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 M on RX0-31
8 M on RX0-7
4 M on RX0-31
8 M on RX0-15
16 M on RX0-3
2 M on RX0-31
16 M on RX0-15
8 M on RX0-31
8 M on TX0-7
2MonTX0-31
8MonTX0-15
4MonTX0-31
2MonTX0-31
16MonTX0-3
8MonTX0-31
16MonTX0-15
+1.5
+4.5
+1.5
+4.5
+2.5
+1.5
+4.5
+4.5
Mux/Demux
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2 M on RX0-15;
8 M on RX16-31
2 M on TX0-15;
8MonTX16-31
+1.5
+4.5
2 M on RX0-15;
4 M on RX16-31
2 M on TX0-15;
4MonTX16-31
+1.5
+4.5
Split
4 M on RX0-15;
8 M on RX16-31
4 M on TX0-15;
8MonTX16-31
+1.5
+4.5
8 M on RX0-15;
16MonRX16-23
8 M on TX0-15;
16MonTX16-23
+4.5
+2.5
15
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 9—OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS
(FD11,FD2-0)
MeasurementResultfrom
Frame Delay Bits
Corresponding
OffsetBits
InputStream
Offset
FD11
FD2
0
FD1
0
FD0
0
OFn2
OFn1
OFn0
DLEn
Noclockperiodshift(Default)
+0.5clockperiodshift
+1.0clockperiodshift
+1.5clockperiodshift
+2.0clockperiodshift
+2.5clockperiodshift
+3.0clockperiodshift
+3.5clockperiodshift
+4.0clockperiodshift
+4.5clockperiodshift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
NOTE:
1. See Table 8 for maximum allowable offsets.
ST-BUS F0i
16.384 MHz CLK
RX Stream
(16.384 Mb/s)
Bit 5
Bit 6
Bit 4
Bit 5
Bit 7
Bit 6
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
Bit 4
offset = 0, DLE = 1
Bit 7
Bit 6
Bit 5
GCI F0i
16.384 MHz CLK
RX Stream
(16.384 Mb/s)
Bit 0
Bit 1
Bit 0
Bit 2
Bit 1
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(16.384 Mb/s)
Bit 2
RX Stream
(16.384 Mb/s)
Bit 2
offset = 0, DLE = 1
Bit 0
Bit 1
5902 drw08
Figure 7. Examples for Input Offset Delay Timing in 16 Mb/s mode
16
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
ST-BUS F0i
CLK
RX Stream
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
Bit 7
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 7
RX Stream
RX Stream
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
RX Stream
RX Stream
RX Stream
RX Stream
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
Bit 0
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
5902 drw09
Figure 7. Examples for Input Offset Delay Timing in 8 Mb/s, 4 Mb/s and 2 Mb/s mode (Continued)
17
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
INSTRUCTION REGISTER
JTAGSUPPORT
In accordance with the IEEE-1149.1 standard, the IDT72V71643 uses
public instructions. The IDT72V71643 JTAG Interface contains a two-bit
instructionregister.Instructionsareseriallyloadedintotheinstructionregister
fromtheTDIwhentheTAPControllerisinitsshifted-IRstate.Subsequently,
theinstructionsaredecodedtoachievetwobasicfunctions:toselectthetestdata
registerthatmayoperatewhiletheinstructioniscurrent,andtodefinetheserial
testdataregisterpath,whichisusedtoshiftdatabetweenTDIandTDOduring
dataregisterscanning.
TheIDT72V71643JTAGinterfaceconformstotheBoundary-Scanstan-
dardIEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechnique
called Boundary-Scan test (BST). The operation of the boundary-scan
circuitryis controlledbyanexternaltestaccess port(TAP)Controller.
TEST ACCESS PORT (TAP)
The TestAccess Port(TAP)provides access tothe testfunctions ofthe
IDT72V71643.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovidestheclockforthetestlogic.TheTCKdoesnotinterferewith
anyon-chipclockandthusremainindependent.TheTCKpermitsshiftingof
testdataintooroutoftheBoundary-Scanregistercellsconcurrentlywiththe
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•TestMode SelectInput(TMS)
Value
00
11
Instruction
EXTEST
BYPASS
01 or 10
SAMPLE/PRELOAD
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse.ThispinisinternallypulledtoVCCwhenitisnot
driven from an external source.
JTAG Instruction Register Decoding
TESTDATAREGISTER
AsspecifiedinIEEE-1149.1,theIDT72V71643JTAGInterfacecontains
twotestdataregisters:
•Test Data Input (TDI)
Serialinputdataappliedtothisportisfedeitherintotheinstructionregister
orintoatestdataregister,dependingonthesequencepreviouslyappliedto
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•TestDataOutput(TDO)
Depending on the sequence previously applied to the TMS input, the
contentsofeithertheinstructionregisterordataregisterareseriallyshiftedout
towardstheTDO.ThedataoutoftheTDOisclockedonthefallingedgeofthe
TCKpulses.Whennodataisshiftedthroughtheboundaryscancells,theTDO
driverissettoahigh-impedancestate.
•The Boundary-Scan register
TheBoundary-ScanregisterconsistsofaseriesofBoundary-Scancells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V71643core
logic.
•The Bypass Register
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bit
pathfromTDItoitsTDO.TheIDT72V71643boundaryscanregisterbitsare
showninTable10.Bit0isthefirstbitclockedout.Allthree-stateenablebitsare
activehigh.
•Test Reset (TRST)
Resetthe JTAGscanstructure. This pinis internallypulledtoVCC.
18
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 10—BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to bit 168
Boundary Scan Bit 0 to bit 168
Device Pin
Three-State
Control
Output
Scan Cell
Input
Scan Cell
Device Pin
Three-State
Control
Output
Scan Cell
Input
Scan Cell
RX27
RX26
RX25
RX24
TX23/OEI7
TX22/OEI6
TX21/OEI5
TX20/OEI4
TX19/OEI3
TX18/OEI2
TX17/OEI1
TX16/OEI0
RX23
RX22
RX21
RX20
RX19
RX18
RX17
RX16
TX15
TX14
TX13
TX12
TX11
TX10
TX9
93
94
95
96
ODE
RESET
CLK
F0i
FE/HCLK
WFPS
DS
CS
R/W
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DTA
D15
D14
D13
D12
D11
0
1
2
3
4
5
6
7
8
97
99
98
100
102
104
106
108
110
112
101
103
105
107
109
111
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
113
114
115
116
117
118
119
120
121
123
125
127
129
131
133
135
122
124
126
128
130
132
134
136
24
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
76
78
80
82
84
86
88
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
75
77
79
81
83
85
87
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
TX8
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
RX7
RX6
RX5
137
138
139
140
141
142
143
144
D10
D9
D8
D7
D6
D5
D4
D3
145
147
149
151
153
155
157
159
146
148
150
152
154
156
158
160
D2
D1
D0
TX31/OEI15
TX30/OEI14
TX29/OEI13
TX28/OEI12
TX27/OEI11
TX26/OEI10
TX25/OEI9
TX24/OEI8
RX31
RX30
RX29
RX28
161
162
163
164
165
166
167
168
RX4
RX3
RX2
RX1
89
90
91
92
RX0
19
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
Using OEI
AOE=0
RX0-15
RX0-15
TX0-15
TX0-15
RX16-31
OEI0-15
OEI0-15
AOE=0
RX0-15
TX0-15
TX16-31
RX16-31
RX16-31
AOE=0
RX0-15
RX16-31
TX0-15
OEI0-15
OEI16-31
RX16-31
AOE=0
RX0-15
TX0-15
RX16-31
RX16-31
AOE=0
Using AOE
RX0
RX0
TX0
RX31
RX31
TX31
AOE=1
RX0
RX0
OEI0
RX31
RX31
OEI31
5902 drw10
Figure 8. Using All Output Enable (AOE)
20
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min.
3.0
2.0
Typ.
3.3
Max.
3.6
Unit
V
VCC
Vi
SupplyVoltage
3.0
GND -0.3
-50
3.6
5.3
50
V
V
Positive Supply
Input HIGH Voltage
InputLOWVoltage
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
VIH
5.3
V
IO
mA
° C
W
VIL
0.8
V
TS
-55
+125
2
TOP
OperatingTemperature
Commercial
-40
25
+85
°C
PD
PackagePowerDissapation
NOTE:
NOTE:
1. Voltages are with respect to Ground unless otherwise stated.
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
75
Units
mA
µA
µA
V
(2)
ICC
SupplyCurrent
-
-
-
-
-
-
-
(3,4)
IIL
InputLeakage(inputpins)
High-impedanceLeakage
OutputHIGHVoltage
OutputLOWVoltage
60
(3,4)
IOZ
-
60
(5)
VOH
2.4
-
-
(6)
VOL
0.4
V
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
ACELECTRICALCHARACTERISTICS-TIMINGPARAMETER
MEASUREMENTVOLTAGELEVELS
Symbol Rating
Level Unit
VTT
VHM
VLM
TTLThreshold
1.5
2.0
0.8
V
V
V
TTLRise/FallThresholdVoltageHIGH
TTLRise/FallThresholdVoltageLOW
Test Point
VCC
R
L
Output
Pin
S1isopencircuitexceptwhentestingoutput
levelsorhigh-impedancestates.
S
2
S
1
C
L
GND
GND
S2isswitchedtoVCCorGNDwhentesting
outputlevelsorhigh-impedancestates.
5902 drw11
Figure 9. Output Load
21
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
Symbol
Parameter
Min.
Typ.
Max.
Units
Frame Pulse Width (ST-BUS®, GCI)
Bit rate = 2.048 Mb/s
(1)
tFPW
26
26
26
295
145
65
ns
ns
ns
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s or 16.384 Mb/s
tFPS(1)
Frame Pulse Setup time before CLK falling (ST-BUS® or GCI)
Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI)
5
ns
ns
(1)
tFPH
10
tCP(1)
CLK Period
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s or 16.384 Mb/s
190
110
58
300
150
70
ns
ns
ns
(1)
tCH
CLK Pulse Width HIGH
Bit rate = 2.048 Mb/s
85
50
20
150
75
40
ns
ns
ns
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s or 16.384 Mb/s
(1)
tCL
CLK Pulse Width LOW
Bit rate = 2.048 Mb/s
85
50
20
150
75
40
ns
ns
ns
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s or 16.384 Mb/s
tr,tf
ClockRise/FallTime
10
ns
(2)
tHFPW
WideFramePulseWidth
HCLK = 4.096 MHz
HCLK = 8.192 MHz
244
122
ns
ns
tHFPS(2)
Frame Pulse Setup Time before HCLK 4 MHz falling
Frame Pulse Hold Time from HCLK 4 MHz falling
Frame Pulse Setup Time before HCLK 8 MHz rising
Frame Pulse Hold Time from HCLK 8 MHz rising
50
50
45
45
150
150
90
ns
ns
ns
ns
(2)
tHFPH
tHFPS(2)
(2)
tHFPH
90
tHCP(2)
HCLK Period
@ 4.096 MHz
@ 8.192 MHz
244
122
ns
ns
tHr,tHf
tDIF(2)
HCLK Rise/Fall Time
10
10
ns
ns
Delaybetweenfallingedge ofHCLKandfallingedge ofCLK
-10
NOTES:
1. WFPS Pin = 0.
2. WFPS Pin = 1.
22
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
RESET
t
ZR
t
RZ
t
RZ
tRS
TX
t
ODE
ODE
5902 drw12
Figure 10. Reset and ODE Timing
CLK
(ST-BUS or
WFPS mode)
CLK
(GCI mode)
tDZ
ODE
TX
TX
VALID DATA
t
ODE
t
ODE
tZD
TX
VALID DATA
VALID DATA
5902 drw14
5902 drw13
Figure 11. Serial Output and External Control
Figure 12. Output Driver Enable (ODE)
23
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MICROPROCESSORINTERFACETIMING
Symbol
tCSS
Parameter
Min.
0
Typ.
15
Max.
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Setup from DS falling
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
R/W Hold after DS Rising
Address HoldafterDSRising
Data SetupfromDTA LOWonRead
DataHoldonRead
tRWS
3
tADS
2
tCSH
0
tRWH
tADH
3
2
(1)
tDDR
2
(1,2,3)
tDHR
10
10
-
tDSW
tSWD
tDHW
tDSPW
tCKAK
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
0
5
35
DSPulse Width
5
Clock to ACK
(1)
tAKD
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
30
ns
ns
ns
ns
@ 2.048 Mb/s
@ 4.096 Mb/s
@ 8.192 Mb/s or 16.384 Mb/s
345
200
120
(1,2,3)
tAKH
AcknowledgmentHoldTime
Data Strobe Setup Time
15
ns
ns
(4)
tDSS
2
NOTES:
1. CL= 150pF
2. RL = 1K
3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
4. To achieve one clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst case memory access operation is determined by tAKD.
24
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
DS
tCSS
tCSH
tCSS
tCSH
CS
tRWS
tRWH
tRWS
tRWH
R/W
A0-A14
D0-D15
t
ADH
tADS
t
ADH
tADS
VALID READ ADDRESS
VALID WRITE ADDRESS
tDSW
tDHR
tDHW
VALID WRITE
DATA
VALID READ DATA
tDDR
tAKH
tAKD
tAKH
tAKD
DTA
5902 drw15
Figure 13. Asyncronous Bus Timing
CLK GCI
CLK ST-BUS
t
DSS
tDSS
t
DSPW
DS
CS
tCSS
tCSS
tCSH
tCSH
tRWH
tRWS
tRWH
tRWS
R/W
tADH
tADS
tADH
tADS
VALID READ
ADDRESS
VALID WRITE
ADDRESS
A0-A14
tSWD
tDHW
tDHR
VALID WRITE
DATA
VALID READ
DATA
D0-D15
tDDR
tCKAK
tCKAK
tAKH
tAKH
5902 drw16
DTA
Figure 14. Syncronous Bus Timing
25
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
26
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
27
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS(1) SERIAL STREAM (ST-BUS® and GCI)
Symbol
Parameter
Min.
Typ.
Max.
22
Units
tSIS
RXSetupTime
2
ns
tSIH
RXHoldTime
10
ns
tSOD
TX Delay – Active to Active
TX Delay – Active to High-Z
TX Delay – High-Z to Active
Output Driver Enable (ODE) Delay
OutputEnableIndicator(OEI)Enable
OutputEnableIndicator(OEI)Disable
Active toHigh-ZonMasterReset
High-ZtoActive onMasterReset
Resetpulsewidth
100
ns
(1)
tDZ
22
ns
(1)
tZD
22
ns
(1)
tODE
30
ns
tOEIE
tOEID
tRZ
40
ns
25
ns
30
ns
tZR
30
ns
tRs
ns
NOTE:
1. High-Impedance is measured by pulling to the appropriate rail with RL (1KΩ), with timing corrected to cancel time taken to discharge CL (150 pF).
28
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
29
ORDERINGINFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Ball Grid Array (BGA, BC144-1)
Thin Quad Flatpacks (TQFP, DA144-1)
BC
DA
72V71643
4,096 x 4,096 3.3V Time Slot Interchange Digital Switch with Rate Matching
5902 drw21
DATASHEETDOCUMENTHISTORY
5/01/2000
6/07/2000
10/10/2000
11/20/2000
03/09/2001
08/20/2001
10/22/2001
1/04/2002
05/17/2002
pg. 1
pgs. 3 and 4.
pgs. 1 through 30.
pgs.10.
pg. 21
pg. 24.
pg. 1.
pgs. 1 and 21.
pg. 28
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:TELECOMhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
30
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