IDT72V8985JG [IDT]
Digital Time Switch, PQCC44, 0.65 X 0.65 INCH, 0.05 INCH PITCH, PLASTIC, LCC-44;
| 型号： | IDT72V8985JG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch, PQCC44, 0.65 X 0.65 INCH, 0.05 INCH PITCH, PLASTIC, LCC-44 电信 电信集成电路 |
| 文件： | 总14页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT72V8985
andwriteaccesstoindividualchannels. Asanimportantfunctionofadigital
switchis tomaintainsequenceintegrityandminimizethroughputdelay, the
IDT72V8985isanidealsolutionformostswitchingneeds.
FEATURES:
•
•
•
•
•
•
•
•
•
256 x 256 channel non-blocking switch
Automatic signal identification (ST-BUS®, GCI)
8 RX inputs—32 channels at 64 Kbit/s per serial line
8 TX outputs—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
3.3V Power Supply
FUNCTIONALDESCRIPTION
Framesequence,constantthroughputdelay,andguaranteedminimum
delayarehighpriorityrequirementsintoday’sintegrateddataandmultimedia
networks. TheIDT72V8985providesthesefunctionsonaper-channelbasis
usingastandardmicroprocessorcontrolinterface. Eachoftheeightseriallines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
InProcessorMode,themicroprocessorcanaccesstheinputandoutputtime
slotstocontrolotherdevicessuchasISDNtransceiversandtrunkinterfaces.
SupportingbothGCIandST-BUS® formats,IDT72V8985hasincorporatedan
internal circuit to automatically identify the polarity and format of the frame
synchronization.
Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic
Quad Flatpack (PQFP)
•
•
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
AfunctionalblockdiagramoftheIDT72V8985deviceisshownonpage1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µswideframeseachcontaining32,8-bitchannels. Eightinput(RX0-7)and
eight output (TX0-7) serial streams are provided in the IDT72V8985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. Theserialinterfaceclockforthedeviceis 4.096MHz.
DESCRIPTION:
TheIDT72V8985isaST-BUS®/GCIcompatibledigitalswitchcontrolledby
amicroprocessor. TheIDT72V8985canhandleasmanyas256,64Kbit/sinput
andoutputchannels. Those256channelsaredividedinto8serialinputsand
outputs,eachofwhichconsistsof32channels.TheIDT72V8985providesper-
channelvariableorconstantthroughputdelaymodesandmicroprocessorread
FUNCTIONAL BLOCK DIAGRAM
RESET(1)
ODE
C4i F0i
VCC GND
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
Timing
Unit
RX0
Output MUX
RX1
RX2
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
RX3
Data
Memory
RX4
RX5
RX6
RX7
Connection
Memory
Control Register
Microprocessor Interface
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CCO
DS
A0/
A5
CS
R/W
D0/
D7
DTA
NOTE:
1. The RESET Input is only provided on the SSOP package.
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.
AUGUST 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5707/5
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
PINCONFIGURATION
INDEX
INDEX
RX3
RX3
7
TX3
TX4
TX5
TX6
TX7
GND
39
38
37
36
1
33
32
31
30
TX3
TX4
TX5
TX6
TX7
GND
RX4
RX5
RX6
8
RX4
RX5
RX6
2
3
4
9
10
11
12
13
14
35
34
33
32
RX7
RX7
5
6
7
8
29
28
27
26
VCC
VCC
D
0
1
F0i
C4i
F0i
C4i
D
D
D
D
0
1
D
A
A
A
0
25
24
23
2
3
9
A
0
15
16
17
31
30
29
D2
D3
D4
1
10
A1
2
2
D4
11
A
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PLCC: 0.05in. pitch, 0.65in. x 0.65in
(J44-1, order code: J)
TOP VIEW
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
GND
CCO
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
DTA
RX0
RX1
RX2
ODE
TX0
TX1
TX2
DNC(1)
TX3
TX4
TX5
2
3
4
5
DNC(1)
RX3
RX4
RX5
RX6
6
7
8
9
TX6
TX7
GND
10
11
12
RX7
VCC
RESET(2)
F0i
VCC
13
14
15
16
17
18
19
20
21
22
23
D0
D1
D2
D3
D4
C4i
A0
A1
A2
33
32
31
30
29
28
27
26
25
DNC(1)
DNC(1)
D5
D6
D7
A3
A4
A5
DS
CS
GND
2
4
R/W
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TOP VIEW
PackageType
SSOP: 0.025in. pitch, 0.625in. x 0.295in.
ReferenceIdentifier Order Code
SO48-1 PV
NOTES:
1. DNC - Do Not Connect
2. The RESET Input is only provided on the SSOP package.
2
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
PINDESCRIPTIONS
SYMBOL
NAME
I/O
DESCRIPTION
GND
Ground.
VCC
Ground Rail.
VCC
+3.3 Volt Power Supply.
DTA
Data Acknowledgment
(Open Drain)
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
RX0-7
RX Input 0 to 7
Frame Pulse
I
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
F0i
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS® and GCI.
C4i
A0-A5
Clock
I
I
I
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT72V8985 internal registers.
Address 0 to 5
Data Strobe
DS
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/W
CS
Read/Write
I
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Chip Select
Active LOW input enabling a microprocessor read or write of control register or internal memories.
D0-D7
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-7
ODE
TX Outputs 0 to 7
(Three-state Outputs)
O
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
I
This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
CCO
Control Channel Output
O
I
This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
RESET Device Reset
(Schmitt Trigger Input)
This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters,
registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
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IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
OUTPUT DRIVE ENABLE (ODE)
FUNCTIONALDESCRIPTION(Cont'd)
TheODEpinisthemasteroutputthree-statecontrolpin. IftheODEinput
isheldLOWallTDM(TimeDivisionMultiplexed) outputswillbeplacedinhigh
impedanceregardlessConnectionMemoryHighprogramming. However,if
ODEisHIGH,thecontentsofConnectionMemoryHighcontroltheoutputstate
on a per-channel basis.
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 256-position Data
Memory.Byusinganinternalcounterthatisresetbytheinput8KHzframepulse,
F0i,theincomingserialdatastreamscanbeframedandsequentiallyaddressed.
Dependingonthetypeofinformationtobeswitched,theIDT72V8985device
canbeprogrammedtoperformtimeslotinterchangefunctionswithdifferent
throughput delay capabilities on a per-channel basis. The Variable Delay
mode,mostcommonlyusedforvoiceapplications,canbeselectedensuring
SERIAL INTERFACE TIMING
TheIDT72V8985masterclock(C4i)is4.096MHzsignalallowingserialdata
minimumthroughputdelaybetweeninputandoutputdata.InConstantDelay link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can
mode,usedinmultipleorgroupedchanneldataapplications,theintegrityofthe automaticallydetectthepresenceofaninputframepulse,identifythetypeof
informationthroughtheswitchismaintained.
backplanepresentontheserialinterface,andformatthesynchronizationpulse
accordingtoST-BUS® orGCIinterfacespecifications(activeHIGHinGCIor
activeLOWinST-BUS®). UpondeterminingthecorrectinterfaceConnected
CONNECTIONMEMORY
Datatobeoutputontheserialstreamsmaycomefromtwosources:Data totheserialport,theinternaltimingunitestablishestheappropriateserialdata
MemoryorConnectionMemory. TheConnectionMemoryis splitintoHIGH bittransmitandsamplingedges. InST-BUS® mode,everysecondfallingedge
andLOWpartsandisassociatedwithparticularTXoutputstreams. InProcessor ofthe 4.096MHzclockmarks a boundaryandthe inputdata is clockedinby
Mode,dataoutputontheTXstreamsistakenfromtheConnectionMemoryLow therisingedge,threequarters ofthewayintothebitcell. InGCImodeevery
andoriginates fromthe microprocessor(Figure 2). Where as inConnection secondrisingedgeofthe4.096MHzclockmarksthebitboundarywhiledata
Mode (Figure 1), data is read from Data Memory and originated from the sampling is performed during the falling edge, at three quarters of the bit
incomingRXstreams. Datadestinedforaparticularchannelontheserialoutput boundaries.
streamisreadinternallyduringthepreviouschanneltimeslottoallowtimefor
memoryaccessandinternalparallel-to-serialconversion.
DELAYTHROUGHTHEIDT72V8985
Thetransferofinformationfromtheinputserialstreamstotheoutputserial
CONNECTIONMODE
streams results in a delay through the device. The delay through the
IDT72V8985devicevariesaccordingtothemodeselectedintheV/Cbitofthe
ConnectionMemoryHigh.
InConnectionMode,theaddressesofinputsourceforalloutputchannels
are stored in the Connection Memory Low. The Connection Memory Low
locationsaremappedtocorresponding8-bitx32-channeloutput. Thecontents
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-
to-serialconvertersbeforebeingoutput. Byhavingtheoutputchanneltospecify
the input channel through the Connection Memory, input channels can be
broadcasttoseveraloutputchannels.
VARIABLEDELAYMODE
The delayinVariable DelayMode is dependentonlyonthe combination
ofsourceanddestinationontheinputandoutputstreams. Theminimumdelay
achievableintheIDT72V8985deviceisthreetimeslots. IntheIDT72V8985
device,theinformationthatistobeoutputinthesamechannelpositionasthe
information is input (position n), relative to frame pulse, will be output in the
followingframe(channeln,framen+1). Thesameoccursiftheinputchannels
succeeding(n+1,n+2)thechannelpositionastheinformationisinput.
Theinformationswitchedtothethirdtimeslotaftertheinputhasenteredthe
device(forinstance,inputchannel0tooutputchannel3orinputchannel30to
outputchannel1),isalwaysoutputthreechannelslater.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locationswhichcorrespondtotheoutputlinkandchannelnumber. Thecontents
of the Connection Memory Low are transferred to the parallel-to-serial
converteronechannelbeforeitistobeoutputandaretransmittedeachframe
totheoutputuntilitis changedbytheCPU.
Anyswitchingconfigurationthatprovidesthreeormoretimeslotsbetween
inputandoutputchannels,willhaveathroughputdelayequaltothedifference
betweentheoutputandinputchannels;i.e.,thethroughputdelaywillbeless
thanoneframe. Table1showsthepossibledelaysfortheIDT72V8985device
in Variable Delay Mode. An example is shown in Figure 3.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT72V8985. Output channels are selected into
specific modes such as: Processor Mode or Connection mode, Variable or
Constantthroughputdelaymodes,OutputDrivers Enabledorinthree-state
condition. Thereis alsoonebittocontrolthestateoftheCCOoutputpin.
CONSTANTDELAYMODE
Inthismodeframeintegrityismaintainedinallswitchingconfigurationsby
Data
Memory
Data
Memory
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
TX
RX
TX
Connection
Memory
Connection
Memory
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Microprocessor
Figure 1. Connection Mode
Figure 2. Processor Mode
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IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
The Processor Enable bit (bit 6) places every output channel on every
outputstreaminProcessorMode;i.e.,thecontentsoftheConnectionMemory
LOW(CML,seeTable5)areoutputontheoutputstreamsonceeveryframe
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every
Connection Memory High (CMH, see Table 4) locations were set to HIGH,
regardlessoftheactualvalue. IfPEisLOW,thenbit2and0ofeachConnection
MemoryHighlocationoperatesnormally. Inthiscase,ifbit2oftheCMHisHIGH,
theassociatedTXoutputchannelisinProcessorMode. Ifbit2oftheCMHis
LOW,thenthecontentsoftheCMLdefinethesourceinformation(streamand
channel)ofthetimeslotthatistobeswitchedtoanoutput.
makinguseofamultipleDataMemorybuffertechniquewhereinputchannels
writteninanyofthebuffersduringframeNwillbereadoutduringframeN+2.
In the IDT72V8985, the minimum throughput delay achievable in Constant
Delaymodewillbe32timeslots;forexample,wheninputtimeslot32(channel
31)isswitchedtooutputtimeslot1(channel0). Likewise,themaximumdelay
isachievedwhenthefirsttimeslotinaframe(channel0)isswitchedtothelast
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
Tosummarize,anyinputtimeslotfrominputframeNwillbealwaysswitched
tothedestinationtimeslotonoutputframeN+2. InConstantDelaymodethe
devicethroughputdelayiscalculatedaccordingtothefollowingformula:
IftheODEinputpinisLOW,thenalltheserialoutputsarehigh-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
ordisables(ifLOW)forthatparticularchannel.
DELAY=[32+(32-IN)+(OUT-1)]
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Table4)isoutputonCCOpinonceeveryframe. TheCCOpinisa2.048Mb/
soutput,whichcarries256bits. IfCCObitissetHIGH,thecorrespondingbit
onCCOoutputistransmittedHIGH. IfCCOisLOW,thecorrespondingbiton
theCCOoutputistransmittedLOW. Thecontentsofthe256CCObitsoftheCMH
aretransmittedsequentiallyontotheCCOoutputpinandaresynchronousto
theTXstreams. Toallowfordelayinanyexternalcontrolcircuitrythecontents
oftheCCObitisoutputonechannelbeforethecorrespondingchannelonthe
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
toTX0,CH0),istransmittedsynchronouslywiththeTXchannel31,bit7.Bit1's
ofCMHforchannel1ofstreams0-7areoutputsynchronouslywithTXchannel
0 bits 7-0.
IN=thenumberoftheinputtimeslot(from1to32)
OUT=thenumberoftheoutputtimeslot(from1to32).
MICROPROCESSORPORT
TheIDT72V8985microprocessorportis anon-multiplexedbusarchitec-
ture. Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddress
inputlines(A0-A5)andfourcontrollines(CS,DS,R/WandDTA). Thisparallel
microportallowstheaccesstotheControlRegisters,ConnectionMemoryLow,
ConnectionMemoryHigh,andtheDataMemory. Alllocationsareread/written
except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
MemoryaremultiplexedwithaccessesfromtheinputandoutputTDMports.
ThiscancausevariableDataAcknowledgedelays(DTA). IntheIDT72V8985
device,theDTAoutputprovidesamaximumacknowledgmentdelayof800ns
forread/writeoperationsintheConnectionMemory. However,foroperations
intheDataMemory(ProcessorMode),themaximumacknowledgmentdelay
can be 1220ns.
INITIALIZATION
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedancestatecontroltotheConnectionMemoryHighbitsoutputs.
Theresetpinisdesignedtobeusedwithboardresetcircuitry.Duringreset
theTXserialstreamswillbeputintohigh-impedanceandthestateofinternal
registersandcounterswillbereset.Astheconnectionmemorycanbeinany
stateafterapowerup,theODEpinshouldbeusedtoholdtheTXstreamsin
high-impedanceuntiltheper-channeloutputenablecontrolintheconnection
memoryhighisappropriatelyprogrammed.ThemaindifferencebetweenODE
andresetis,resetaltersthestateoftheregistersandcounterswhereasODE
controlsonlythehigh-impedancestateoftheTXstreams.RESETinputisonly
providedonthe SSOPpackages.
SOFTWARECONTROL
IftheA5,A1,A0addresslineinputsareLOWthentheIDT72V8985Internal
ControlRegisteris addressed(seeTable2). IfA5inputlineis high,thenthe
remainingaddressinputlinesareusedtoselectthe32possiblechannelsper
inputoroutputstream. As explainedintheControlRegisterdescription,the
addressinputlinesandtheStreamAddressbits(STA)oftheControlregister
givetheuserthecapabilityofselectingallpositionsofIDT72V8985Dataand
Connectmemories. SeeFigure5foraccessinginternalmemories.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorEnablebits(Table3).InSplitMemory
mode(Bit7oftheControlregister)readsarefromtheDataMemoryandwrites
are to the Connection Memory LOW. The Memory Select bits allow the
ConnectionMemoryHighorLOWortheDataMemorytobechosen,andthe
StreamAddressbitsdefineinternalmemorysubsectionscorrespondingtoinput
oroutputstreams.
TABLE2ADDRESSMAPPING
A5
A4
A3
A2
A1
A0
LOCATION
0
1
1
1
1
1
1
1
1
X
0
0
•
X
0
0
•
X
0
0
•
0
0
0
•
0
0
1
•
Control Register
Channel 0
TABLE 1 VARIABLE DELAY MODE
Channel 1
•
Input Channel
Output Channel
m=n, n+1 or n+2
m>n+2
Throughput Delay
m-n+32time slot
m-ntimeslot
•
•
•
•
•
•
n
n
n
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
m<n
32-(n-m) time slot
1
1
1
1
1
Channel 31
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IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
Incoming Now
Outgoing Next
Outgoing Now
32 31........7
1
6
5
4
3 2
Time Slot 32 31 30 29 28............ 3
2
I
1
J
32 31.........7
6
5
I
4
3
2
1 Time Slot
G
H
A
B
C
D
E
F
G
H
J
J
J
J
32 Slots
32 Slots
32 Slots
For J: DELAY=3 Slots, 32 Slots, 33 Slots, and 34 Slots
For G, H, and I: DELAY= 3 slots
Figure 3. Variable Delay Mode
Incoming
Switching
Outgoing
Time Slot 32 31 30 29 28............ 3
2
I
1
J
32 31 30 29 28............. 3
2
1 Time Slot
A
A
B
C
D
E F G H
J
I
H
G
F
E
D
C
B
32 Slots
32 Slots
32 Slots
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For Slot 1 ("A"): IN=32, OUT=1, DELAY=(32-32)+32+(1-1)=32 time slots minimum delay
For Slot 32 ("J"): IN=1, OUT=32, DELAY=(32-1)+32+(32-1)=94 time slots maximum delay
Figure 4. Constant Delay Mode
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IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
Control Register
b
b
b
b
b
b
b
b
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CR 4 CR 3
b
b
0
1
0
1
1
1
Connection Memory High
Connection Memory Low
Data Memory
CR 2 CR 1 CR 0
Stream
b
b
b
0
1
2
3
4
5
6
7
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
100001
100010
111111
100000
External Address Bits A5-A0
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Figure 5. Addressing Internal Memories
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IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
TABLE 3 CONTROL REGISTER
7
6
5
4
3
2
1
0
SM
PE
X
MS1
MS0 STA2 STA1 STA0
Bit
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when
the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in high-
impedance. When 0, the Connection Memory bits for each channel determine what is output.
5
unused
4-3
MS1-MS0
0-0 - Not to be used.
(Memory Select Bits)
0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0
STA2-0
(Stream Address Bits)
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
x = don't care
TABLE 4 CONNECTION MEMORY HIGH
7
6
5
4
3
2
1
0
X
V/C
X
X
X
CS
CCO
OE
Bit
7,5,4,3
6
Name
Description
unused
V/C (Variable/Constant
Throughput Delay Mode)
This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.
2
CS
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
(Channel Source)
1
0
CCO (CCO Bit)
This bit drives a bit time on the CCO output pin.
OE (Output Enable)
This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to
bemadehigh-impedance,allowingswitchmatrices tobeconstructed.AHIGHenables thedriverandaLOWdisables it.
x = don't care
TABLE 5 CONNECTION MEMORY LOW
7
6
5
4
3
2
1
0
SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
7-5 SAB2-0(1)
(Source Stream Address Bits)
4-0(1) CAB2-0(1)
Name
Description
These three bits are used to select eight source streams for the Connection.
These five bits are used to select 32 different source channels for the Connection (the stream where the channel
(Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.
8
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min. Typ.(1) Max.
Unit
V
Vcc
Vi
SymbolVoltage
-0.3
5.0
V
V
Positive Supply
InputVoltage
3.0
0
3.3
25
3.6
5.25
+85
VoltageonDigitalInputs
VoltageonDigitalOutputs
CurrentatDigitalOutputs
StorageTemperature
GND - 0.3 VCC +0.5
GND - 0.3 VCC +0.3
20
VI
V
VO
V
TOP
OperatingTemperature
Commercial
-40
°C
IO
mA
° C
W
TS
-55
+125
1
NOTE:
PD
PackagePowerDissapation
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only a functional operation
of the device at these or any conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DCELECTRICALCHARACTERISTICS
Symbol
ICC
Parameter
Min.
2.0
2.4
10
Typ.(1)
3
Max.
5
Units
mA
V
Test Conditions
SupplyCurrent
OutputsUnloaded
VIH
VIL
InputHighVoltage
InputLowVoltage
InputLeakage(Inputs)
InputCapacitance
OutputHighVoltage
OutputHighCurrent
OutputLowVoltage
OutputLowCurrent
HighImpedanceLeakage
OutputPinCapacitance
0.8
15
V
IIL
µA
pF
VI between GND and VCC
CI
10
VOH
IOH
VOL
IOL
0.4
5
V
IOH = 10mA
Sourcing. VOH = 0.8V
IOL = 5mA
mA
V
5
mA
µA
pF
Sinking. VOL = 0.4V
VO between GND and VCC
IOZ
CO
10
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
RL
Output
Pin
S2
S1
CL
S2isswitchedtoVCCorGNDwhentesting
outputlevelsorhighimpedancestates.
GND
GND
5707 drw09
Figure 6. Output Load
9
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) ST-BUS® TIMING
Symbol
tF0iW
tF0iS
tF0iH
tDAA
tSTiS
tSTiH
tC4i
Parameter
Min.
5
Typ.(2)
244
20
Max.
Units
ns
Test Conditions
FramePulseWidth
FramePulseSetupTime
FramePulseHoldTime
TX delay Active to Active
RXSetupTime
190
190
60
ns
5
20
ns
ns
10
10
40
CL = 150pF
ns
RXHoldTime
ns
Clock Period
244
122
122
ns
tCL
CK Input Low
ns
tCH
CK Input High
ns
ns
tr,tf
ClockRise/FallTime
10
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tF0iW
F0i
tCH
tCL
tF0iS
tF0iH
tC4i
C4i
tDAA
tf
tr
Ch. 0, Bit 6
TX
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 5
Ch. 0,
Bit 5
tSTiS
tSTiH
Ch. 31, Bit 0
Ch. 0, Bit 7
Ch. 0, Bit 6
RX
5707 drw10
Figure 7. ST-BUS® Timing
10
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) GCI TIMING
Symbol
Parameter
Min.
5
Typ.(2)
244
122
244
20
Max.
Units
ns
Test Conditions
tC4i
Clock Period
tCL, tCH
tWFH
PulseWidth
ns
FrameWidthHigh
FrameSetup
ns
ns
tF0iS
190
190
60
tF0iH
FrameHold
5
20
ns
tDAA
Data Delay/Clock Active to Active
RXInputSetup
RXInputHold
10
10
40
ns
CL = 150pF
tSTiS
ns
tSTiH
ns
tr,tf
ClockRise/FallTime
10
ns
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tWFH
F0i
tF0iS
tF0iH
tr
tCL
t
f
tCH
tC4i
C4i
TX
RX
Ch. 31
Bit 7
Ch. 0
Bit 0
Ch. 0
Bit 1
tDAA
tSTiS
tSTiH
Ch. 31
Bit 7
Ch. 0
Bit 0
Ch. 0
Bit 1
5707 drw11
Figure 8. GCI Timing
11
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) SERIAL STREAM TIMING
Symbol
Characteristics
Min.
0
Typ.(2)
30
Max.
Unit
Test Conditions
RL = 1KΩ(3), CL = 150pF
CL = 150pF
tTAZ
TX0-7 Delay - Active to High Z
TX0-7 Delay - High Z to Active
OutputDriverEnableDelay
CCO Output Delay
ResettoHighZ
45
ns
tTZA
45
60
ns
tOED
tXCD
45
60
ns
RL = 1KΩ(3), CL = 150pF
40
60
ns
CL = 150pF
tRSZ
5
30
ns
tZRS
HighZtoReset
0
32
ns
tZDO
tRPW
HighZtoValidData
ResetPulseWidth
100
cycles
ns
C4i cycles
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
ODE
Bit Cell Boundary
tOED
tOED
(GCI)
TX0-7
C4i
(ST-BUS)
5707 drw13
tTAZ
Figure 10. Output Driver Enable
TX0-7
TX0-7
CCO
RS
t
TZA
tRPW
TX
tXCD
tZDO
5707 drw14
tRSZ
5707 drw12
tZRS
Figure 9. Serial Outputs and External Control
Figure 11. Reset
12
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ACELECTRICALCHARACTERISTICS(1) MICROPROCESSORTIMING
Symbol
Characteristics
Min.
Typ.(2)
Max.
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
tCSS
CS Setup from DS Rising
R/W Setup from DS Rising
AddSetupfromDSRising
CS Hold after DS Falling
R/W Hold after DS Falling
AddHoldafterDSFalling
Data SetupfromDTA LowonRead
DataHoldonRead
0
tRWS
tADS
5
5
tCSH
0
tRWH
tADH
5
5
tDDR
10
10
10
5
CL = 150pF
RL = 1KΩ(3), CL = 150pF
tDHR
50
tDSW
tSWD
tDHW
tAKD
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
122
AcknowledgmentDelay:
CL = 150pF
ReadingDataMemory
560
300/370
45
1220
730/800
70
ns
ns
ns
ns
Reading/WritingConnectionMemory
WritingtoControlRegister
ReadingtoControlRegister
45
70
tAKH
AcknowledgmentHoldTime
10
20
40
ns
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
CS
tCSH
tCSS
tRWH
tRWS
R/W
tADH
tADS
A0-A5
D0-D7
READ
VALID DATA
tSWD
tDHR
tDSW
D0-D7
WRITE
VALID DATA
t
DHW
t
DDR
tAKH
t
AKD
DTA
5707 drw15
Figure 12. Motorola Non-Multiplexed Bus Timing
13
ORDERINGINFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Plastic Leaded Chip Carrier (PLCC, J44-1)
Small Shrink Outline Package (SSOP, SO48-1)
Plastic Quad Flatpack (PQFP, DB44-1)
J
PV
DB
72V8985
256 x 256 3.3V Time Slot Interchange Digital Switch
5707 drw15
DATASHEETDOCUMENTHISTORY
05/24/2000
08/21/2000
01/24/2001
04/05/2001
03/10/2003
05/09/2003
08/20/2003
pgs. 1, 2, 13 and 14.
pgs. 1, 2 and 14.
pgs. 1 and 9.
pg. 11.
pg. 13.
pgs. 1, 2, and 14.
pg. 9.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
408-330-1753
email:TELECOMhelp@idt.com
www.idt.com
14
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