IDT74ALVC08PG8 [IDT]
AND Gate, ALVC/VCX/A Series, 4-Func, 2-Input, CMOS, PDSO14, TSSOP-14;
| 型号： | IDT74ALVC08PG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | AND Gate, ALVC/VCX/A Series, 4-Func, 2-Input, CMOS, PDSO14, TSSOP-14 栅 光电二极管 |
| 文件： | 总5页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74ALVC08
3.3V CMOS QUADRUPLE
2-INPUT POSITIVE-AND GATE
DESCRIPTION:
FEATURES:
This quadruple 2-inputpositive-ANDgate is builtusingadvanceddual
metalCMOStechnology.The ALVC08performs the BooleanfunctionY=
A • B or Y = A + B in positive logic.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
TheALVC08hasbeendesignedwitha±24mAoutputdriver. Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SOIC, SSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
PINCONFIGURATION
14
13
1
2
3
4
5
6
1A
1B
1Y
2A
VCC
4B
A
Y
12
11
10
9
4A
B
4Y
3B
3A
3Y
2B
2Y
8
7
GND
SOIC/ SSOP/ TSSOP
TOP VIEW
(1)
PINDESCRIPTION
Pin Names
FUNCTION TABLE (EACH GATE)
Inputs
Output
Description
xA, xB
xY
Data Inputs
xA
H
xB
H
X
L
xY
H
L
Data Outputs
L
X
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1
©2000 Integrated Device Technology, Inc.
DSC-4633/2
IDT74ALVC08
3.3VCMOSQUADRUPLE2-INPUTPOSITIVE-ANDGATE
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
COUT
CI/O
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
° C
mA
mA
NOTE:
Continuous Clamp Current,
VI < 0 or VI > VCC
1. As applicable to the device type.
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
VCC = 3.6V
VI = VCC
VI = GND
—
—
—
—
—
5
5
µA
µA
V
VCC = 3.6V
VIK
VH
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
Input Hysteresis
—
—
100
0.1
—
10
mV
µ A
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µ A
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2
IDT74ALVC08
3.3VCMOSQUADRUPLE2-INPUTPOSITIVE-ANDGATE
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
CPD
PowerDissipationCapacitanceperGate
CL = 0pF, f = 10Mhz
25
26
pF
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
PropagationDelay
xA or xB to xY
1
3.2
1.2
3.4
1.2
3.3
tPHL
NOTE:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
3
IDT74ALVC08
3.3VCMOSQUADRUPLE2-INPUTPOSITIVE-ANDGATE
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
tPHL
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
tPHL
tPLH
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Quad Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VOL + VLZ
VOL
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VOH - VHZ
SWITCH
OPEN
VT
0V
ALVC Quad Link
0V
Test Circuit for All Outputs
ALVC Quad Link
NOTE:
DEFINITIONS:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
DATA
INPUT
VT
0V
tSU
tH
SWITCHPOSITION
VIH
TIMING
INPUT
VT
Test
Switch
VLOAD
GND
Open
0V
tREM
Open Drain
Disable Low
Enable Low
VIH
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
Disable High
Enable High
SYNCHRONOUS
CONTROL
tSU
tH
All Other Tests
ALVC Quad Link
VIH
VT
INPUT
0V
Set-up, Hold, and Release Times
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
ALVC Quad Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Quad Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74ALVC08
3.3VCMOSQUADRUPLE2-INPUTPOSITIVE-ANDGATE
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
XXX
XX
ALVC
Device Type Package
Temp. Range
Small Outline IC
Shrink Small Outline Package
Thin Shrink Small Outline Package
DC
PY
PG
08
74
Quadruple 2-Input Positive-AND Gate, 24mA
– 40°C to +85°C
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
logichelp@idt.com
5
相关型号：
IDT74ALVC125DC8
Bus Driver, ALVC/VCX/A Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, SOIC-14
IDT
©2020 ICPDF网 联系我们和版权申明