IDT74ALVC126PG8 [IDT]
Bus Driver, ALVC/VCX/A Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, TSSOP-14;
| 型号： | IDT74ALVC126PG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, ALVC/VCX/A Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, TSSOP-14 光电二极管 |
| 文件： | 总6页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74ALVC126
3.3V CMOS QUADRUPLE
BUS BUFFER GATE
WITH 3-STATE OUTPUTS
DESCRIPTION:
FEATURES:
This quadruple bus buffer gate is built using advanced dual metal CMOS
technology. The ALVC126 features independent line drivers with 3-state
outputs.Eachoutputisdisabledwhentheassociatedoutput-enable(OE)input
islow.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
TheALVC126hasbeendesignedwitha±24mAoutputdriver. Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SOIC, SSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
1
10
1OE
3OE
3
8
9
2
3Y
1Y
1A
3A
4
13
12
2OE
4OE
4A
6
11
5
4Y
2Y
2A
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2000
1
©2000 Integrated Device Technology, Inc.
DSC-4636/1
IDT74ALVC126
3.3VCMOSQUADRUPLEBUSBUFFERGATEWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
(2)
VTERM
VTERM
TSTG
IOUT
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1
2
3
4
5
6
14
13
1OE
VCC
4OE
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1A
1Y
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
12
11
10
9
4A
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
4Y
2OE
2A
ICC
ISS
Continuous Current through each
VCC or GND
±100
3OE
3A
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2Y
3Y
8
7
GND
2. VCC terminals.
3. All terminals except VCC.
SOIC/ SSOP/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
CI/O
NOTE:
1. As applicable to the device type.
PINDESCRIPTION
Pin Names
Description
xOE
x A
Output Enable Inputs
Data Inputs
x Y
3-State Outputs
(1)
FUNCTION TABLE (EACH BUFFER)
Inputs
Output
xOE
H
xA
H
L
xY
H
L
H
L
X
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
2
IDT74ALVC126
3.3VCMOSQUADRUPLEBUSBUFFERGATEWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
10
mV
µA
ICCL
ICCH
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
ICCZ
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74ALVC126
3.3VCMOSQUADRUPLEBUSBUFFERGATEWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
CPD
PowerDissipationCapacitanceperGateOutputsenabled
CL = 0pF, f = 10Mhz
20
28
pF
CPD
PowerDissipationCapacitanceperGateOutputsdisabled
1
2
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPLH
PropagationDelay
1
3.5
1.1
3.1
1.1
3
ns
tPHL
tPZH
tPZL
tPHZ
tPLZ
xA to xY
OutputEnableTime
xOE to xY
1.5
1
5.6
5
1.5
1.7
5.3
4.4
1.5
1.7
4.5
4.2
ns
ns
OutputDisableTime
xOE to xY
NOTE:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
4
IDT74ALVC126
3.3VCMOSQUADRUPLEBUSBUFFERGATEWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
tPHL
tPLH
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Quad Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VOL + VLZ
VOL
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VOH - VHZ
SWITCH
OPEN
VT
0V
ALVC Quad Link
0V
Test Circuit for All Outputs
ALVC Quad Link
NOTE:
DEFINITIONS:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
DATA
INPUT
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VT
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
tREM
Open Drain
Disable Low
Enable Low
VIH
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
Disable High
Enable High
SYNCHRONOUS
CONTROL
tSU
tH
All Other Tests
Open
ALVC Quad Link
VIH
VT
Set-up, Hold, and Release Times
INPUT
0V
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
ALVC Quad Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Quad Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVC126
3.3VCMOSQUADRUPLEBUSBUFFERGATEWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
XXX
XX
ALVC
Device Type Package
Temp. Range
DC
PY
PG
Small Outline IC
Shrink Small Outline Package
Thin Shrink Small Outline Package
126
74
Quadruple Bus Buffer Gate with 3-State Outputs, ±24mA
– 40°C to +85°C
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www.idt.com
6
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