IDT74ALVC1G79DY8 [IDT]

D Flip-Flop, ALVC/VCX/A Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO5, 0.65 MM PITCH, PLASTIC, SOP-5;
IDT74ALVC1G79DY8
型号: IDT74ALVC1G79DY8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

D Flip-Flop, ALVC/VCX/A Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO5, 0.65 MM PITCH, PLASTIC, SOP-5

光电二极管 逻辑集成电路 触发器
文件: 总6页 (文件大小:108K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
3.3V CMOS SINGLE  
IDT74ALVC1G79  
POSITIVE-EDGE-  
TRIGGERED D-TYPE  
FLIP-FLOP  
FEATURES:  
DESCRIPTION:  
This single positive-edge-triggered D-type flip-flop is built using  
advanced dual metal CMOS technology. The ALVC1G79 is designed  
for 1.65V to 3.6V VCC operation. When data at the data (D) input meets  
the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a  
voltage level and is not directly related to the rise time of the clock pulse.  
Following the hold-time interval, data at the D input may be changed  
without affecting the levels at the outputs.  
0.5 MICRON CMOS Technology  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.65mm pitch PSOP package  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 1.65V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
The ALVC1G79 has been designed with a ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speed performance.  
Drive Features for ALVC1G79:  
High Output Drivers: ±24mA  
Suitable for heavy loads  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
FUNCTIONAL BLOCK DIAGRAM  
2
C
C
CLK  
C
4
TG  
C
Q
C
TG  
C
C
TG  
C
C
TG  
C
1
D
PIN DESCRIPTION  
PIN CONFIGURATION  
Pin Names  
Description  
CLK  
D
Clock Input  
Data Input  
Data Output  
5
4
1
D
VCC  
2
SO5-1  
CLK  
Q
3
GND  
Q
PSOP  
TOP VIEW  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
AUGUST1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4751/-  
IDT74ALVC1G79  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
3.3VCMOSSINGLEPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP  
FUNCTION TABLE (1)  
ABSOLUTE MAXIMUM RATING (1)  
Inputs  
Output  
Symbol  
Description  
Terminal Voltage  
Max.  
Unit  
(2)  
CLK  
D
H
L
Q
H
VTERM  
– 0.5 to + 4.6  
V
with Respect to GND  
Terminal Voltage  
(3)  
VTERM  
–0.5 to  
V
L
with Respect to GND  
Storage Temperature  
VCC + 0.5  
Q0  
L
X
TSTG  
IOUT  
IIK  
– 65 to + 150 °C  
NOTE:  
DC Output Current  
– 50 to + 50  
± 50  
mA  
mA  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Don't Care  
Continuous Clamp Current,  
>
VI < 0 or VI VCC  
- = LOW-to-HIGHTransition  
Qo = Level of Q before the indicated steady-state input conditions  
IOK  
Continuous Clamp Current, VO < 0  
– 50  
mA  
mA  
were established.  
ICC  
ISS  
Continuous Current through  
each VCC or GND  
±100  
ALVC 1G Link  
NOTES:  
o
1. Stresses greater than those listed under ABSOLUTE MAXIMUM  
RATINGS may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device at these or  
any other conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect reliability.  
2. VCC terminals.  
A
CAPACITANCE(T = +25 C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Conditions  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
VIN = 0V  
5
7
pF  
COUT  
Output  
Capacitance  
I/O Port  
VOUT = 0V  
7
9
pF  
3. All terminals except VCC.  
CI/O  
VIN = 0V  
7
9
pF  
Capacitance  
ALVC 1G Link  
NOTE:  
1. As applicable to the device type.  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Following Conditions Apply Unless Otherwise Specified:  
CC  
Operating Condition: TA = – 40°C to +85°C, V = 2.3V to 3.6V  
(1)  
Typ.  
Symbol  
Parameter  
Test Conditions  
VCC = 1.65V to 1.95V  
Min.  
Max.  
Unit  
VIH  
Input HIGH Voltage Level  
0.65 x VCC  
V
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
VCC = 1.65V to 1.95V  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
VCC = 3.6V  
1.7  
2
VIL  
Input LOW Voltage Level  
0.35 x VCC  
0.7  
V
0.8  
IIH  
Input HIGH Current  
VI = VCC  
± 5  
µA  
IIL  
Input LOW Current  
VCC = 3.6V  
VI = GND  
VO = VCC  
VO = GND  
± 5  
IOZH  
IOZL  
VIK  
VH  
High Impedance Output Current  
(3-State Output pins)  
Clamp Diode Voltage  
Input Hysteresis  
VCC = 3.6V  
± 10  
± 10  
– 1.2  
µA  
µA  
V
VCC = 2.3V, IIN = – 18mA  
VCC = 3.3V  
– 0.7  
100  
0.1  
mV  
µA  
ICCL  
ICCH  
ICCZ  
Quiescent Power Supply Current  
VCC = 3.6V  
VIN = GND or VCC  
10  
ICC  
Quiescent Power Supply  
Current Variation  
One input at VCC 0.6V,  
750  
µA  
other inputs at VCC or GND  
ALVC 1G Link  
NOTE:  
1. Typical values are at VCC = 3.3V, +25°C ambient.  
2
IDT74ALVC1G79  
3.3VCMOSSINGLEPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
OUTPUT DRIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Max.  
Unit  
VOH  
Output HIGH Voltage  
VCC = 1.65V to 3.6V  
IOH = – 0.1mA  
IOH = – 4mA  
IOH = – 6mA  
IOH = – 12mA  
VCC – 0.2  
V
VCC = 1.65V  
VCC = 2.3V  
1.2  
2
VCC = 2.3V  
1.7  
2.2  
2.4  
2
VCC = 2.7V  
VCC = 3.0V  
VCC = 3.0V  
IOH = – 24mA  
IOL = 0.1mA  
IOL = 4mA  
VOL  
Output LOW Voltage  
VCC = 1.65V to 3.6V  
VCC = 1.65V  
VCC = 2.3V  
0.2  
0.45  
0.4  
0.7  
0.4  
0.55  
V
IOL = 6mA  
IOL = 12mA  
IOL = 12mA  
IOL = 24mA  
VCC = 2.7V  
VCC = 3.0V  
ALVC 1G Link  
NOTE:  
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the  
appropriate VCC range. TA = – 40°C to + 85°C.  
o
OPERATING CHARACTERISTICS, T = 25 C  
A
VCC = 1.8V ± 0.15V  
VCC = 2.5 ± 0.2V  
VCC = 3.3V ± 0.3V  
Symbol  
Parameter  
Test Conditions  
Typ.  
Typ.  
Typ.  
Unit  
CPD  
Power Dissipation Capacitance  
CL = 0pF, f = 10MHz  
pF  
SWITCHING CHARACTERISTICS(1)  
VCC = 1.8V ± 0.15V  
VCC = 2.5V ± 0.2V  
VCC = 2.7V  
VCC = 3.3V ± 0.3V  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
fMAX  
MHz  
tPLH  
tPHL  
tW  
Propagation Delay  
CLK to Q  
12  
6
5
3.8  
ns  
Pulse Width, CLK HIGH or LOW  
5
5
5
2
3.3  
3
3.3  
3
3.3  
3
ns  
ns  
ns  
ns  
tSU  
tSU  
Setup Time, data before CLK, HIGH  
Setup Time, data before CLK, LOW  
Hold Time, data after CLK↑  
3
3
3
tH  
1
1
0
NOTE:  
1. See test circuits and waveforms. TA = – 40°C to + 85°C.  
3
IDT74ALVC1G79  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
3.3VCMOSSINGLEPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP  
TEST CIRCUITS AND WAVEFORMS:  
TEST CONDITIONS  
Symbol  
PROPAGATION DELAY  
(1)  
(1)  
(2)  
VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V  
Unit  
VIH  
VLOAD  
6
6
2 xVcc  
Vcc  
V
SAME PHASE  
INPUT TRANSITION  
T
V
VIH  
VT  
2.7  
1.5  
300  
300  
50  
2.7  
1.5  
300  
300  
50  
V
V
0V  
tPHL  
tPLH  
Vcc / 2  
150  
VOH  
OUTPUT  
VLZ  
VHZ  
CL  
mV  
mV  
T
V
VOL  
150  
PLH  
tPHL  
t
VIH  
VT  
0V  
30  
pF  
ALVC 1G Link  
OPPOSITE PHASE  
INPUT TRANSITION  
ALVC 1G Link  
ENABLE AND DISABLE TIMES  
TEST CIRCUITS FOR ALL OUTPUTS  
LOAD  
V
DISABLE  
ENABLE  
CC  
V
IH  
V
Open  
CONTROL  
INPUT  
VT  
0V  
500  
GND  
tPZL  
tPLZ  
VIN  
VOUT  
Pulse(1, 2)  
Generator  
VLOAD/2  
VT  
VLOAD/2  
OUTPUT  
NORMALLY  
LOW  
D.U.T.  
SWITCH  
CLOSED  
VLZ  
VOL  
tPHZ  
500Ω  
tPZH  
T
R
CL  
OUTPUT  
NORMALLY  
HIGH  
OH  
V
SWITCH  
OPEN  
VT  
0V  
VHZ  
DEFINITIONS:  
ALVC 1G Link  
0V  
CL= Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse  
Generator.  
ALVC 1G Link  
NOTE:  
NOTES:  
1. Diagram shown for input Control Enable-LOW and input Control  
Disable-HIGH.  
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.  
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.  
SWITCH POSITION  
SET-UP, HOLD, AND RELEASE TIMES  
Test  
Switch  
VIH  
VT  
0V  
DATA  
INPUT  
Open Drain  
Disable Low  
Enable Low  
Disable High  
Enable High  
All Other tests  
VLOAD  
tSU  
tH  
IH  
V
TIMING  
INPUT  
VT  
0V  
GND  
Open  
tREM  
VIH  
VT  
0V  
ASYNCHRONOUS  
CONTROL  
ALVC 1G Link  
VIH  
VT  
0V  
SYNCHRONOUS  
CONTROL  
tSU  
tH  
ALVC 1G Link  
PULSE WIDTH  
LOW-HIGH-LOW  
PULSE  
VT  
tW  
HIGH-LOW-HIGH  
PULSE  
VT  
ALVC 1G Link  
4
IDT74ALVC1G79  
3.3VCMOSSINGLEPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS:  
TEST CONDITIONS  
PROPAGATION DELAY  
(1)  
VCC = 1.8V ± 0.15V  
Symbol  
Unit  
VIH  
VT  
SAME PHASE  
INPUT TRANSITION  
VLOAD  
2 x VCC  
VCC  
V
0V  
tPHL  
tPHL  
tPLH  
VIH  
VT  
V
V
VOH  
VT  
OUTPUT  
VCC / 2  
150  
VOL  
VLZ  
VHZ  
CL  
mV  
mV  
t
PLH  
VIH  
VT  
150  
OPPOSITE PHASE  
INPUT TRANSITION  
30  
pF  
ALVC 1G Link  
0V  
ALVC 1G Link  
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES  
VLOAD  
DISABLE  
ENABLE  
VCC  
VIH  
VT  
Open  
GND  
CONTROL  
INPUT  
0V  
1000  
tPZL  
tPLZ  
VIN  
VOUT  
Pulse(1)  
Generator  
VLOAD/2  
VT  
VLOAD/2  
OUTPUT  
NORM ALLY  
LOW  
D.U.T.  
SW ITCH  
CLOSED  
VLZ  
VOL  
tPHZ  
tPZH  
1000Ω  
RT  
CL  
OUTPUT  
NORM ALLY  
HIGH  
VOH  
VHZ  
SW ITCH  
OPEN  
VT  
0V  
ALVC 1G Link  
DEFINITIONS:  
0V  
CL= Load capacitance: includes jig and probe capacitance.  
ALVC 1G Link  
RT = Termination resistance: should be equal to ZOUT of the Pulse  
NOTE:  
Generator.  
1. Diagram shown for input Control Enable-LOW and input Control  
Disable-HIGH.  
NOTE:  
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.  
SET-UP, HOLD, AND RELEASE TIMES  
SWITCH POSITION  
Test  
Switch  
VIH  
VT  
0V  
DATA  
Open Drain  
Disable Low  
Enable Low  
Disable High  
Enable High  
All Other tests  
VLOAD  
INPUT  
tSU  
tH  
VIH  
VT  
0V  
TIMING  
INPUT  
GND  
Open  
tREM  
VIH  
VT  
0V  
ASYNCHRONOUS  
CONTROL  
VIH  
VT  
0V  
ALVC 1G Link  
SYNCHRONOUS  
CONTROL  
tSU  
tH  
ALVC 1G Link  
PULSE WIDTH  
LOW -HIGH-LOW  
PULSE  
VT  
tW  
HIGH-LOW -HIGH  
PULSE  
VT  
ALVC 1G Link  
5
IDT74ALVC1G79  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
3.3VCMOSSINGLEPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOP  
ORDERINGINFORMATION  
IDT  
XX  
ALVC  
XXX  
XX  
Device Type Package  
Temp. Range  
DY  
Plastic Small Outline Package (SO5-1)  
Single Positive-Edge-Triggered D-Type Flip-Flop, ±24mA  
– 40°C to +85°C  
1G79  
74  
PICOGATE-LOGIC (DY) PACKAGES  
Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDTs 5-pin PSOP (DY) packaged devices  
utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol  
denotes a wafer fab/assembly site code for internal tracking.  
EXAMPLES:  
1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A.  
2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04.  
PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES  
TECHNOLOGY  
ALVC  
CODE  
G
J
FUNCTION  
00  
CODE  
A
B
ALVCH  
02  
LVC  
L
04  
U04  
06  
C
D
T
(1)  
LVCH  
07  
V
08  
E
14  
F
32  
G
79  
R
86  
H
125  
126  
132  
M
N
Y
NOTE:  
1. Code to be determined.  
CORPORATE HEADQUARTERS  
2975 Stender Way  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com*  
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
6

相关型号:

IDT74ALVC1G86

3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
IDT

IDT74ALVC1G86DY

3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE
IDT

IDT74ALVC1G86DY8

XOR Gate, ALVC/VCX/A Series, 1-Func, 2-Input, CMOS, PDSO5, 0.65 MM PITCH, PLASTIC, SOP-5
IDT

IDT74ALVC244

3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
IDT

IDT74ALVC244PG

3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
IDT

IDT74ALVC244PG8

Bus Driver, ALVC/VCX/A Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.65 MM PITCH, TSSOP-20
IDT

IDT74ALVC244PY

3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
IDT

IDT74ALVC244PY8

Bus Driver, ALVC/VCX/A Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.65 MM PITCH, SSOP-20
IDT

IDT74ALVC244PYG

Bus Driver, ALVC/VCX/A Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.65 MM PITCH, SSOP-20
IDT

IDT74ALVC244Q

3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
IDT

IDT74ALVC244QG

Bus Driver, ALVC/VCX/A Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.635 MM PITCH, QSOP-20
IDT

IDT74ALVC244SO

3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
IDT