IDT74ALVCH162374PF8
更新时间：2024-09-18 14:17:05
品牌：IDT
描述：Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48
概述
规格参数
数据手册IDT74ALVCH162374PF8 概述
Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48 总线驱动器/收发器
IDT74ALVCH162374PF8 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | TSSOP, |
| 针数： | 48 | Reach Compliance Code： | compliant |
| 风险等级： | 5.89 | 系列： | ALVC/VCX/A |
| JESD-30 代码： | R-PDSO-G48 | 长度： | 9.7 mm |
| 逻辑集成电路类型： | BUS DRIVER | 位数： | 8 |
| 功能数量： | 2 | 端口数量： | 2 |
| 端子数量： | 48 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 输出特性： | 3-STATE WITH SERIES RESISTOR |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | TSSOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 传播延迟（tpd）： | 5.4 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 1.2 mm | 最大供电电压 (Vsup)： | 3.6 V |
| 最小供电电压 (Vsup)： | 2.7 V | 标称供电电压 (Vsup)： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子形式： | GULL WING |
| 端子节距： | 0.4 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 4.4 mm |
| Base Number Matches： | 1 |
IDT74ALVCH162374PF8 数据手册
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PDF下载3.3V CMOS 16-BIT EDGE-
TRIGGERED D-TYPE FLIP-
IDT74ALVCH162374
FLOP WITH 3-STATE OUT-
PUTS AND BUS-HOLD
DESCRIPTION:
FEATURES:
–
–
–
0.5 MICRON CMOS Technology
TypicaltSK(0) (Output Skew) < 250ps
This 16-bit edge-triggered D-type flip-flop is built using advanced dual
metal CMOS technology. The ALVCH162374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-
flop. On the positive transition of the clock (CLK) input, the Q outputs of
the flip-flop take on the logic levels set up at the data (D) inputs. OE can
be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The
high-impedance state and the increased drive provide the capability to
drive bus lines without need for interface or pullup components. OE does
not affect internal operations of the flip-flop. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
–
–
–
–
–
–
–
Drive Features for ALVCH162374:
–
–
Balanced Output Drivers: ±12mA
Low switching noise
The ALVCH162374 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
The ALVCH162374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistor.
Functional Block Diagram
1
24
2OE
1OE
48
25
2CLK
1CLK
C1
C1
2
13
1Q1
2Q1
47
36
1D1
1D
1D
2D1
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
MARCH1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4565/-
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATING (1)
Symbol
Description
Terminal Voltage
Max.
Unit
(2)
VTERM
– 0.5 to + 4.6
V
1CLK
1
2
3
4
48
47
46
45
44
43
42
41
40
39
1OE
1Q1
1Q2
with Respect to GND
Terminal Voltage
(3)
VTERM
– 0.5 to
VCC + 0.5
V
1D1
1D2
GND
1D3
1D4
with Respect to GND
Storage Temperature
TSTG
IOUT
IIK
– 65 to + 150
°C
DC Output Current
– 50 to + 50
± 50
mA
mA
GND
1Q3
1Q4
Continuous Clamp Current,
VI < 0 or VI > VCC
Continuous Clamp Current, VO < 0
5
6
IOK
– 50
mA
mA
ICC
ISS
Continuous Current through
each VCC or GND
±100
VCC
1Q5
1Q6
7
V
CC
1D5
1D6
GND
1D7
8
NEW16link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
9
GND
1Q7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38
37
36
35
SO48-1
SO48-2
SO48-3
1D8
2D1
2D2
1Q8
2Q1
2Q2
3. All terminals except VCC.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
34
33
GND
2Q3
2Q4
VCC
2Q5
GND
2D3
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
2D4
32
31
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
7
7
9
9
pF
pF
VCC
2D5
2D6
30
29
28
27
26
Capacitance
NEW16link
2Q6
GND
2Q7
NOTE:
1. As applicable to the device type.
GND
2D7
2D8
2Q8
FUNCTION TABLE (each flip-flop)(1)
2CLK
2OE
25
Inputs
Outputs
xOE
L
xCLK
xDx
H
xQx
H
SSOP/
TSSOP/TVSOP
TOP VIEW
↑
↑
L
L
L
L
Hor L
X
X
QO
Z
H
X
PIN DESCRIPTION
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Pin Names
Description
Data Inputs(1)
xDx
Z = High-Impedance
xCLK
xQx
Clock Inputs
↑ = LOW-to-HIGHTransition
3-State Outputs
QO = Level of Q before the indicated steady-state input conditions were
established
xOE
3-State Output Enable Inputs (Active LOW)
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
2
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
0.7
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
—
V
—
0.8
IIH
Input HIGH Current
VI = VCC
—
± 5
± 5
± 10
± 10
– 1.2
—
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
VO = VCC
VO = GND
—
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
VCC = 3.6V
—
µA
µA
V
—
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
– 0.7
100
0.1
mV
µA
ICCL
ICCH
ICCZ
∆ICC
VCC = 3.6V
VIN = GND or VCC
40
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
VI = 2.0V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
– 75
—
—
µA
IBHL
75
– 45
45
—
—
—
—
—
—
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
µA
—
IBHHO
IBHLO
—
± 500
µA
NEW16link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
1.9
1.7
2.2
2
—
—
VCC = 2.7V
VCC = 3.0V
—
—
2.4
2
—
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3.0V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Unit
Symbol
Parameter
Power Dissipation Capacitance
Outputs enabled
Test Conditions
Typical
Typical
CPD
CL = 0pF, f = 10Mhz
28
31
pF
pF
CPD
Power Dissipation Capacitance
Outputs disabled
10
11
(1)
SWITCHING CHARACTERISTICS
VCC = 2.5V ± 0.2V
VCC = 2.7V
Min. Max.
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fMAX
150
—
150
—
—
150
—
MHz
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
xCLK to xQx
1
1
1
5.4
6.5
5.6
5.4
1
4.6
5.2
4.5
ns
Output Enable Time
xOE to xQx
—
—
6.4
5
1
ns
ns
Output Disable Time
xOE to xQx
1.2
Setup Time, data before CLK↑
2.1
0.6
3.3
—
—
—
—
—
2.2
0.5
3.3
—
—
—
—
—
1.9
0.5
3.3
—
—
—
ns
ns
ns
ps
tH
Hold Time, data after CLK↑
tW
Pulse Duration, CLK HIGH or LOW
—
(2)
tSK(o)
NOTES:
Output Skew
500
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
PROPAGATION DELAY
TEST CONDITIONS
Symbol
(1)
(1)
(2)
VCC = 3.3V±0.3V VCC = 2.7V VCC = 2.5V±0.2V
Unit
V
IH
VLOAD
6
6
2 x Vcc
Vcc
V
SAME PHASE
INPUT TRANSITION
VT
0V
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
tPHL
tPLH
VOH
VT
Vcc / 2
150
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
tPHL
tPLH
150
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
30
pF
NEW16link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
VLOAD
DISABLE
VCC
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VLZ
VOL
500Ω
tPHZ
t
PZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
DEFINITIONS:
0V
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
VIH
DATA
INPUT
SWITCH POSITION
VT
0V
tSU
tH
Test
Switch
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
GND
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
NEW16link
ALVC Link
OUTPUT SKEW - TSK (x)
VIH
VT
0V
INPUT
PULSE WIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
VT
OUTPUT 1
tSK (x)
VOL
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
VOL
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERINGINFORMATION
XX
Device Type Package
IDT
XX
ALVC
X
XX
XXX
Bus-Hold
Family
Temp. Range
PV
PA
PF
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
374
16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs
162
Double-Density with Resistors, ±12mA
H
Bus-Hold
– 40°C to +85°C
74
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
IDT74ALVCH162374PF8 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| IDT74ALVCH162374PFG | IDT | Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48 | 获取价格 |
|
| IDT74ALVCH162374PV | ETC | 16-Bit D-Type Flip-Flop | 获取价格 |
|
| IDT74ALVCH162374PV8 | IDT | Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.635 MM PITCH, SSOP-48 | 获取价格 |
|
| IDT74ALVCH162374PVG | IDT | Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.635 MM PITCH, SSOP-48 | 获取价格 |
|
| IDT74ALVCH16240PA | ETC | Quad 4-Bit Buffer/Driver | 获取价格 |
|
| IDT74ALVCH16240PA8 | IDT | Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, Inverted Output, CMOS, PDSO48, 0.50 MM PITCH, TSSOP-48 | 获取价格 |
|
| IDT74ALVCH16240PF | ETC | Quad 4-Bit Buffer/Driver | 获取价格 |
|
| IDT74ALVCH16240PV | ETC | Quad 4-Bit Buffer/Driver | 获取价格 |
|
| IDT74ALVCH16240PV8 | IDT | Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, Inverted Output, CMOS, PDSO48, 0.635 MM PITCH, SSOP-48 | 获取价格 |
|
| IDT74ALVCH16244 | IDT | 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD | 获取价格 |
|
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