IDT74ALVCH162836PA8 [IDT]

Bus Driver, ALVC/VCX/A Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56;
IDT74ALVCH162836PA8
型号: IDT74ALVCH162836PA8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Bus Driver, ALVC/VCX/A Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

光电二极管
文件: 总7页 (文件大小:70K)
中文:  中文翻译
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3.3V CMOS 20-BIT  
IDT74ALVCH162836  
UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
This 20-bit universal bus driver is built using advanced dual metal CMOS  
technology.DataflowfromAtoYiscontrolledbytheoutput-enable(OE)input.  
Thedeviceoperatesinthetransparentmodewhenthelatch-enable(LE)input  
islow.WhenLEishigh,theAdataislatchediftheclock(CLK)inputisheldat  
ahighorlowlogiclevel.IfLEishigh,theAdataisstoredinthelatch/flip-flopon  
thelow-to-hightransitionofCLK.WhenOEishigh,theoutputsareinthehigh-  
impedancestate.  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
Available in SSOP, TSSOP, and TVSOP packages  
TheALVCH162836hasseriesresistorsinthedeviceoutputstructurewhich  
willsignificantlyreducelinenoisewhenusedwithlightloads.Thisdriverhas  
beendesignedtodrive±12mAatthedesignatedthresholdlevels.  
The ALVCH162836 has bus-hold” which retains the inputs’ last state  
whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs  
andeliminatestheneedforpull-up/downresistors.  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
Low switching noise  
APPLICATIONS:  
• SDRAM Modules  
• PC Motherboards  
Workstations  
FUNCTIONALBLOCKDIAGRAM  
1
OE  
56  
CLK  
29  
LE  
55  
A1  
1D  
2
Y1  
C1  
CLK  
TO 19 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
APRIL 1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-4568/1  
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
PINCONFIGURATION  
Symbol  
Description  
Max  
Unit  
V
(2)  
VTERM  
Terminal Voltage with Respect to GND  
–0.5 to +4.6  
1
OE  
Y1  
56  
CLK  
A1  
(3)  
VTERM  
Terminal Voltage with Respect to GND –0.5 to VCC+0.5  
V
2
55  
54  
53  
52  
TSTG  
IOUT  
IIK  
Storage Temperature  
DC Output Current  
–65 to +150  
–50 to +50  
±50  
° C  
mA  
mA  
3
Y2  
A2  
4
GND  
GND  
A3  
Continuous Clamp Current,  
VI < 0 or VI > VCC  
5
Y3  
Y4  
IOK  
Continuous Clamp Current, VO < 0  
–50  
mA  
mA  
6
51  
50  
49  
A4  
ICC  
ISS  
Continuous Current through each  
VCC or GND  
±100  
VCC  
7
VCC  
A5  
8
Y5  
Y6  
Y7  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
9
48  
A6  
10  
A7  
47  
46  
45  
44  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
GND  
Y8  
GND  
A8  
2. VCC terminals.  
3. All terminals except VCC.  
Y9  
A9  
Y10  
Y11  
Y12  
43  
42  
A10  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
VCC  
A17  
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
41  
40  
39  
38  
Symbol  
Parameter(1)  
Conditions  
VIN = 0V  
VOUT = 0V  
VIN = 0V  
Typ.  
Max. Unit  
Y13  
GND  
Y14  
CIN  
Input Capacitance  
Output Capacitance  
I/O Port Capacitance  
5
7
7
7
9
9
pF  
pF  
pF  
COUT  
COUT  
Y15  
37  
36  
35  
NOTE:  
1. As applicable to the device type.  
Y16  
VCC  
Y17  
34  
33  
32  
FUNCTIONTABLE(1)  
24  
25  
26  
Y18  
A18  
Inputs  
Output  
GND  
GND  
OE  
H
L
LE  
X
L
CLK  
X
X
X
Ax  
X
L
Yx  
Z
Y19  
Y20  
NC  
31  
30  
29  
A19  
A20  
LE  
27  
28  
L
L
L
H
L
H
L
L
H
H
H
H
SSOP/ TSSOP/ TVSOP  
TOP VIEW  
L
H
X
X
H
2
L
H
L
Y
2
L
Y
PINDESCRIPTION  
NOTES:  
Pin Names  
Description  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Don’t Care  
= LOW-to-HIGH Transition  
Z = High-Impedance  
2. Output level before the indicated steady-state input conditions were established.  
OE  
CLK  
LE  
3-State Output Enable Inputs (Active LOW)  
Register Input Clock  
Latch Enable (Active LOW)  
Data Inputs(1)  
Ax  
Yx  
3-State Outputs  
N C  
No Internal Connection  
NOTE:  
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.  
2
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
OperatingCondition:TA = –40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
Min.  
1.7  
2
Typ.(1)  
Max.  
Unit  
VIH  
Input HIGH Voltage Level  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
V
VIL  
Input LOW Voltage Level  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
0.7  
0.8  
V
IIH  
IIL  
Input HIGH Current  
VCC = 3.6V  
VCC = 3.6V  
VCC = 3.6V  
VI = VCC  
±5  
±5  
µA  
µA  
µ A  
Input LOW Current  
VI = GND  
VO = VCC  
VO = GND  
IOZH  
IOZL  
VIK  
VH  
High Impedance Output Current  
(3-State Output pins)  
±10  
±10  
–1.2  
Clamp Diode Voltage  
VCC = 2.3V, IIN = –18mA  
VCC = 3.3V  
–0.7  
V
Input Hysteresis  
100  
0.1  
40  
mV  
µ A  
ICCL  
ICCH  
ICCZ  
Quiescent Power Supply Current  
VCC = 3.6V  
VIN = GND or VCC  
ICC  
Quiescent Power Supply Current  
Variation  
One input at VCC - 0.6V, other inputs at VCC or GND  
750  
µ A  
NOTE:  
1. Typical values are at VCC = 3.3V, +25°C ambient.  
BUS-HOLDCHARACTERISTICS  
Symbol  
IBHH  
Parameter(1)  
Test Conditions  
VI = 2V  
Min.  
75  
75  
Typ.(2)  
Max.  
Unit  
Bus-HoldInputSustainCurrent  
VCC = 3V  
µ A  
IBHL  
VI = 0.8V  
IBHH  
Bus-HoldInputSustainCurrent  
Bus-HoldInputOverdrive Current  
VCC = 2.3V  
VCC = 3.6V  
VI = 1.7V  
45  
45  
µ A  
µ A  
IBHL  
VI = 0.7V  
IBHHO  
VI = 0 to 3.6V  
±500  
IBHLO  
NOTES:  
1. Pins with Bus-Hold are identified in the pin description.  
2. Typical values are at VCC = 3.3V, +25°C ambient.  
3
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
OUTPUTDRIVECHARACTERISTICS  
Symbol  
Parameter  
TestConditions(1)  
Min.  
VCC – 0.2  
1.9  
1.7  
2.2  
2
Max.  
Unit  
VOH  
OutputHIGHVoltage  
VCC = 2.3V to 3.6V  
IOH = – 0.1mA  
IOH = – 4mA  
IOH = – 6mA  
IOH = – 4mA  
IOH = – 8mA  
IOH = – 6mA  
IOH = – 12mA  
IOL = 0.1mA  
IOL = 4mA  
V
VCC = 2.3V  
VCC = 2.7V  
VCC = 3V  
2.4  
2
VOL  
OutputLOWVoltage  
VCC = 2.3V to 3.6V  
VCC = 2.3V  
0.2  
0.4  
0.55  
0.4  
0.6  
0.55  
0.8  
V
IOL = 6mA  
VCC = 2.7V  
VCC = 3V  
IOL = 4mA  
IOL = 8mA  
IOL = 6mA  
IOL = 12mA  
NOTE:  
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.  
TA = – 40°C to + 85°C.  
OPERATING CHARACTERISTICS, TA = 25°C  
VCC = 2.5V ± 0.2V  
VCC = 3.3V ± 0.3V  
Symbol  
CPD  
Parameter  
Test Conditions  
Typical  
31.5  
8
Typical  
36  
Unit  
PowerDissipationCapacitanceOutputsenabled  
PowerDissipationCapacitanceOutputsdisabled  
CL = 0pF, f = 10Mhz  
pF  
CPD  
10.5  
4
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
SWITCHINGCHARACTERISTICS(1)  
VCC = 2.5V ± 0.2V  
VCC = 2.7V  
VCC = 3.3V ± 0.3V  
Symbol  
fMAX  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
tSU  
Parameter  
Min.  
150  
1
Max.  
Min.  
150  
Max.  
Min.  
150  
1.2  
Max.  
4
Unit  
ns  
PropagationDelay  
4.4  
4.6  
ns  
Ax to Yx  
PropagationDelay  
1.1  
1
5.8  
5.2  
6.4  
4.7  
6.1  
5.5  
6.5  
5.2  
1.4  
1.1  
1.2  
1.7  
5.1  
5
ns  
ns  
ns  
ns  
LE to Yx  
PropagationDelay  
CLK to Yx  
OutputEnableTime  
1.1  
1
5.5  
5.1  
OE to Yx  
OutputDisableTime  
OE to Yx  
Set-upTime,databeforeCLK↑  
Set-up Time, data before LE, CLK HIGH  
Set-upTime, data before LE,CLKLOW  
HoldTime,dataafterCLK↑  
Hold Time, data after LE, CLK HIGH or LOW  
Pulse Duration,LE LOW  
Pulse Duration, CLK HIGH or LOW  
1.4  
1.2  
1.4  
0.9  
1.1  
3.3  
3.3  
1.7  
1.6  
1.5  
0.9  
1.1  
3.3  
3.3  
1.5  
1.3  
1.2  
0.9  
1.1  
3.3  
3.3  
500  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
tSU  
tSU  
tH  
tH  
tW  
tW  
(2)  
tSK(O)  
OutputSkew  
NOTES:  
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.  
2
Skew between any two outputs of the same package and switching in the same direction.  
5
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDWAVEFORMS  
VIH  
VT  
SAME PHASE  
INPUT TRANSITION  
TESTCONDITIONS  
0V  
tPHL  
tPLH  
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit  
VOH  
VT  
OUTPUT  
VLOAD  
VIH  
6
6
2 x Vcc  
Vcc  
V
V
VOL  
2.7  
1.5  
300  
300  
50  
2.7  
1.5  
300  
300  
50  
tPHL  
tPLH  
VIH  
VT  
0V  
VT  
Vcc / 2  
150  
V
OPPOSITE PHASE  
INPUT TRANSITION  
VLZ  
VHZ  
CL  
mV  
mV  
pF  
150  
ALVC Link  
30  
Propagation Delay  
VLOAD  
Open  
GND  
DISABLE  
VCC  
ENABLE  
VIH  
VT  
CONTROL  
INPUT  
500  
0V  
tPZL  
tPLZ  
VIN  
VOUT  
Pulse(1, 2)  
Generator  
VLOAD/2  
D.U.T.  
VLOAD/2  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
CLOSED  
VT  
VLZ  
VOL  
500Ω  
tPHZ  
tPZH  
RT  
CL  
OUTPUT  
NORMALLY  
HIGH  
VOH  
VHZ  
SWITCH  
OPEN  
VT  
0V  
ALVC Link  
0V  
Test Circuit for All Outputs  
ALVC Link  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
Enable and Disable Times  
NOTE:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
NOTES:  
VIH  
VT  
0V  
1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.  
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.  
DATA  
INPUT  
tSU  
tH  
VIH  
VT  
0V  
TIMING  
INPUT  
SWITCHPOSITION  
Test  
Switch  
VLOAD  
GND  
Open  
tREM  
VIH  
VT  
0V  
ASYNCHRONOUS  
CONTROL  
Open Drain  
Disable Low  
Enable Low  
VIH  
VT  
0V  
SYNCHRONOUS  
CONTROL  
Disable High  
Enable High  
tSU  
tH  
ALVC Link  
All Other Tests  
VIH  
Set-up, Hold, and Release Times  
VT  
0V  
INPUT  
tPLH1  
tPHL1  
VOH  
VT  
LOW-HIGH-LOW  
VT  
PULSE  
OUTPUT 1  
OUTPUT 2  
VOL  
tSK (x)  
tSK (x)  
tW  
VOH  
VT  
HIGH-LOW-HIGH  
PULSE  
VT  
VOL  
ALVC Link  
tPLH2  
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1  
tPHL2  
Pulse Width  
ALVC Link  
Output Skew - tSK(X)  
NOTES:  
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.  
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.  
6
IDT74ALVCH162836  
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
IDT  
XXX  
XX  
ALVC  
X
XXX  
XX  
Device Type Package  
Bus-Hold  
Family  
Temp. Range  
Shrink Small Outline Package  
Thin Shrink Small Outline Package  
Thin Very Small Outline Package  
PV  
PA  
PF  
20-Bit Universal Bus Driver with 3-State Outputs  
Double-Density with Resistors, ±12mA  
836  
162  
H
Bus-Hold  
74  
–40°C to +85°C  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
for Tech Support:  
logichelp@idt.com  
(408) 654-6459  
www.idt.com  
7

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