IDT74ALVCH16540PF8 [IDT]
Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, Inverted Output, CMOS, PDSO48, TVSOP-48;型号: | IDT74ALVCH16540PF8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, Inverted Output, CMOS, PDSO48, TVSOP-48 光电二极管 电视 |
文件: | 总6页 (文件大小:77K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING
BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This 16-bit inverting buffer/line driver is built using advanced dual metal
CMOStechnology.TheALVCH16540offersbus/backplaneinterfacecapabil-
itywithimprovedpackingdensityandaflow-throughorganizationforsimplifying
boardlayout.Itisdesignedspecificallytoimprovetheperformanceanddensity
of3-statememoryaddressdrivers,clockdrivers,andbus-orientedreceivers
andtransmitters.Thethree-statecontrolsoperatethisdeviceinaquad-nibble,
dual-byte,orsingle16-bitwordmode.The3-stateoutputsarecontrolledbythe
output enable (OE) pins. A high on OE causes the outputs to force a high
impedanceoff-state.Allinputsaredesignedwithhysteresisforimprovednoise
margin.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
The ALVCH16540 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
The ALVCH16540 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs
andeliminatestheneedforpull-up/downresistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
2
47
6
35
13
14
1
2A1
2Y0
2Y1
1A0
46
5
1Y1
1Y2
3
1Y4
1A1
44
43
41
33
32
16
17
19
2A2
2A3
2A4
2Y2
2Y3
1A2
1A3
30
2Y4
1A4
9
20
29
27
26
2Y5
2Y6
2Y7
1Y5
1Y6
1Y7
1A5
1A6
1A7
2A5
2A6
2A7
11
12
22
23
38
37
24
25
2OE1
2OE2
1OE1
1OE2
48
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4545/1
IDT74ALVCH16540
3.3VCMOS16-BITINVERTINGBUFFER/LINEDRIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
1
1OE1
1Y0
48
47
46
45
1OE2
1A0
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1Y1
3
1A1
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
1Y2
4
GND
1A2
5
44
43
42
41
40
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
1Y3
6
1A3
VCC
1Y4
7
VCC
1A4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
1Y5
9
1A5
GND
1Y6
10
11
12
13
14
39
38
37
36
35
34
33
GND
1A6
2. VCC terminals.
3. All terminals except VCC.
1Y7
1A7
2Y0
2A0
2Y1
GND
2Y2
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2A1
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
15
16
17
GND
2A2
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
CI/O
2Y3
2A3
32
31
VCC
2Y4
18
19
20
21
VCC
2A4
NOTE:
1. As applicable to the device type.
30
29
28
27
26
25
2Y5
2A5
GND
2Y6
GND
2A6
22
23
24
PINDESCRIPTION
2Y7
Pin Names
xOEx
xAx
Description
2A7
3-State Output Enable Inputs (Active LOW)
Data Inputs(1)
2OE1
2OE2
xYx
3-State Outputs(1)
SSOP/ TSSOP/ TVSOP
TOP VIEW
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTIONTABLE(1)
Inputs
Output
xOE1
xOE2
xAx
L
xYx
H
L
L
L
L
H
L
X
H
H
X
X
Z
X
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2
IDT74ALVCH16540
3.3VCMOS16-BITINVERTINGBUFFER/LINEDRIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16540
3.3VCMOS16-BITINVERTINGBUFFER/LINEDRIVER
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
—
Typical
—
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
—
—
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xAx to xYx
—
—
—
3.6
4.7
4.5
—
1
3
ns
ns
ns
ps
tPHL
tPZH
OutputEnableTime
xOEx to xYx
—
—
—
—
—
—
—
—
—
1
1
3.8
4.1
500
tPZL
tPHZ
OutputDisableTime
tPLZ
xOEx to xYx
OutputSkew(2)
tSK(o)
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16540
3.3VCMOS16-BITINVERTINGBUFFER/LINEDRIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
DATA
INPUT
VT
0V
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
tREM
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
Open
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH16540
3.3VCMOS16-BITINVERTINGBUFFER/LINEDRIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
ALVC
X
XXX
XX
XX
XXX
Device Type Package
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
540
16-Bit Inverting Buffer/Line Driver with 3-State Outputs
16
Double-Density with Resistors, ±24mA
Bus-Hold
H
74
–40°C to +85°C
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www.idt.com
6
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