IDT74ALVCH16841PV8 [IDT]
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;
| 型号： | IDT74ALVCH16841PV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 20-BIT
IDT74ALVCH16841
BUS-INTERFACE D-TYPE
LATCH WITH 3-STATE OUT-
PUTS AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This20-bitinterfaceD-typelatchisbuiltusingadvanceddualmetalCMOS
technology. The ALVCH16841 features 3-state outputs designed specifi-
cally for driving highly capacitive relatively low-impedance loads. This
device is particularly suitable for implementing buffer registers, unidirec-
tional bus drivers, and working registers.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
The ALVCH16841 can be used as two 10-bit latches or one 20-bit latch.
The20latchesaretransparentD-typelatches.Thedevicehasnoninverting
data(D)inputsandprovidestruedataatitsoutputs. Whilethelatch-enable
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch
follow the D inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the
outputsofthecorresponding10-bitlatchineitheranormallogicstate(high
orlowlogiclevels)orahigh-impedancestate. Inthehigh-impedancestate,
the outputs neither load nor drive the bus lines significantly. OE does not
affecttheinternaloperationofthelatches. Olddatacanberetainedornew
data can be entered while the outputs are in the high-impedance state.
The ALVCH16841 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
The ALVCH16841 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONALBLOCKDIAGRAM
28
1
2OE
1OE
56
29
42
1LE
2LE
2D1
55
1D1
1D
C1
1D
C1
15
2
2Q1
1Q1
Q
Q
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
©1999 Integrated Device Technology, Inc.
DSC-4699/2
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
1
56
55
1OE
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1LE
1D1
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1Q1
1Q2
2
3
4
5
6
7
8
9
1D2
GND
1D3
1D4
54
53
52
51
50
49
48
47
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
1Q3
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
VCC
1D5
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2. VCC terminals.
3. All terminals except VCC.
46
45
44
43
42
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
41
40
39
38
37
36
35
34
33
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
2Q3
COUT
COUT
GND
2Q4
NOTE:
1. As applicable to the device type.
2Q5
2Q6
VCC
2Q7
2Q8
PINDESCRIPTION
Pin Names
VCC
2D7
2D8
Description
xDx
xLE
Data Inputs(1)
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
3-State Outputs
xOE
xQx
GND
2Q9
25
26
27
28
32
31
30
29
GND
2D9
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2Q10
2OE
2D10
2LE
(1)
FUNCTION TABLE (EACH 10-BIT LATCH)
Inputs
Output
SSOP/ TSSOP/ TVSOP
TOP VIEW
xDx
H
xLE
H
xOE
xQx
H
L
L
L
H
L
X
L
L
Q2
X
X
H
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
12
1
20
3
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
—
Max.
Min.
Max.
Unit
PropagationDelay
xDx to xQx
1
5
4.7
1.2
3.9
ns
ns
ns
ns
tPHL
tPLH
PropagationDelay
xLE to xQx
1
1
5.6
6.2
5.3
—
—
—
5.1
6
1
1
4.3
4.9
4.1
tPHL
tPZH
tPZL
OutputEnableTime
xOE to xQx
tPHZ
tPLZ
OutputDisableTime
xOE to xQx
1.1
4.3
1.3
tSU
Set-upTime,databeforeLE↓
HoldTime,dataafterLE↓
Pulse Duration, xLE HIGH
OutputSkew(2)
0.9
1.2
3.3
—
—
—
—
—
0.7
1.5
3.3
—
—
—
—
—
1.1
1.1
3.3
—
—
—
ns
ns
ns
ps
tH
tW
—
tSK(O)
NOTES:
500
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
tPHL
tPLH
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
VT
DATA
INPUT
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
tREM
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
All Other Tests
Open
ALVC Link
VIH
Set-up, Hold, and Release Times
VT
0V
INPUT
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XXX
IDT
ALVC
XXX
XX
XX
Device Type Package
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
20-Bit Bus-Interface D-Type Latch with 3-State Outputs
841
16
Double-Density, ±24mA
Bus-Hold
H
74
–40°C to +85°C
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www.idt.com
6
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