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IDT74AUC16373BVI8 [IDT]

Bus Driver, AUC Series, 2-Func, 8-Bit, True Output, CMOS, PBGA56, VFBGA-56;
IDT74AUC16373BVI8
型号： IDT74AUC16373BVI8
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

Bus Driver, AUC Series, 2-Func, 8-Bit, True Output, CMOS, PBGA56, VFBGA-56
文件： 总7页 (文件大小：91K)
中文：  中文翻译
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1.8V CMOS 16-BIT TRANSPARENT  
D-TYPE LATCH WITH  
3-STATE OUTPUTS  
IDT74AUC16373  
DESCRIPTION:  
FEATURES:  
This16-bittransparentD-typelatchisbuiltusingadvancedCMOStechnol-  
ogy. Thedevicecanbeusedasasingle16-bitlatchorastwo8-bitlatches. When  
thelatchenable(LE)inputishigh,theQoutputsfollowthedata(D)inputs. When  
LEis takenlow, the Qoutputs are latchedatthe levels setupatthe Dinputs.  
Abufferedoutputenable(OE)inputcanbeusedtoplacetheeightoutputs  
ineitheranormallogicstate(highorlowlogiclevels)orahigh-impedancestate.  
In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. TheOEinputdoesnotaffecttheinternaloperationofthelatch.  
Thisdeviceisfullyspecifiedforpartialpower-downapplicationsusingIOFF.  
TheIOFFcircuitrydisablestheoutputs,preventingdamagingcurrentbackflow  
through the device when it is powered down.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• 1.8VOptimized  
• 0.8V to 2.7V Operating Range  
• Inputs/outputs tolerant up to 3.6V  
• Output drivers: ±9mA @ 2.3V  
• Supports hot insertion  
• Available in TSSOP, TVSOP, and VFBGA packages  
APPLICATIONS:  
To ensure the high-impedance state during power up or power down, OE  
shouldbetiedtoVDD throughapull-upresistor;theminimumvalueoftheresistor  
isdeterminedbythecurrent-sinkingcapabilityofthedriver.  
• high performance, low voltage communications systems  
• high performance, low voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
1OE  
1LE  
2OE  
2LE  
C1  
C1  
1Q1  
2Q1  
1D1  
2D1  
1D  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
FEBRUARY 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-6169/10  
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
PINOUTCONFIGURATION  
1LE  
NC  
1D2  
1D1  
1D4  
1D3  
1D6  
1D5  
1D8  
1D7  
2D1  
2D2  
2D3  
2D4  
2D5  
2D6  
2D7  
2D8  
2LE  
NC  
6
5
NC  
NC  
GND  
GND  
VDD  
VDD  
GND  
GND  
GND  
GND  
VDD  
VDD  
GND  
GND  
NC  
NC  
4
3
NC  
1Q1  
1Q3  
1Q5  
1Q7  
2Q2  
2Q4  
2Q6  
2Q8  
NC  
2
1
1OE  
A
2OE  
K
1Q2  
B
1Q4  
C
1Q6  
D
1Q8  
E
2Q1  
F
2Q3  
G
2Q5  
H
2Q7  
J
VFBGA  
NOTE:  
NC = No Internal Connection  
56 BALL VFBGA PACKAGE LAYOUT  
A
B
C
D
E
F
G
H
J
K
6
5
4
3
2
1
TOP VIEW  
2
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTE MAXIMUM RATINGS(1)  
PINCONFIGURATION  
Symbol  
Description  
Max  
Unit  
VTERM  
Terminal Voltage with Respect to GND  
(all input and VDD terminals)  
Terminal Voltage with Respect to GND  
(any I/O or Output terminals in high-  
impedance or power-off state)  
Storage Temperature  
–0.5 to +3.6  
V
1OE  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
VDD  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
VDD  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
VTERM  
–0.5 to +3.6  
V
2
1Q1  
1Q2  
GND  
1Q3  
1Q4  
VDD  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
VDD  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
3
TSTG  
IOUT  
IIK  
–65 to +150  
±20  
° C  
4
Continuous DC Output Current  
Continuous Clamp Current,  
VI < 0, or VI > VDD  
mA  
mA  
±50  
5
6
IOK  
IDD  
ISS  
Continuous Clamp Current, VO < 0  
Continuous Current through  
each VDD or GND  
–50  
mA  
mA  
7
±100  
8
NOTE:  
9
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
10  
11  
12  
13  
14  
38  
37  
36  
35  
34  
33  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CAPACITANCE (TA = +25°C, f = 1.0MHz, VDD = 2.5V)  
Symbol  
Parameter  
Conditions  
Typ.  
Max. Unit  
(1)  
CIN  
Input Capacitance  
Output Capacitance  
VIN = 0V  
3
4
6.5  
4
pF  
pF  
pF  
32  
31  
30  
29  
28  
27  
26  
25  
(2)  
COUT  
(3)  
VOUT = 0V  
5.5  
3
CI  
Input Port Capacitance VIN = 0V  
NOTES:  
1. Applies to Control Inputs.  
2. Applies to Data Outputs.  
3. Applies to Data Inputs.  
2OE  
(1)  
FUNCTION TABLE (EACH 8-BIT LATCH)  
Inputs  
xLE  
H
Output  
xQx  
H
TSSOP/ TVSOP  
TOP VIEW  
xOE  
L
xDx  
H
L
H
L
L
PINDESCRIPTION  
(2)  
L
L
X
Q
Pin Names  
xDx  
Description  
H
X
X
Z
DataInputs  
NOTES:  
xLE  
LatchEnableInputs  
3-StateOutputs  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Don't Care  
xQx  
xOE  
3-StateOutputEnableInputs(ActiveLOW)  
Z = High-Impedance  
2. Level of Q before the indicated steady-state conditions were established.  
3
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
RECOMMENDEDOPERATINGCHARACTERISTICS(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Unit  
VDD  
SupplyVoltage  
0.8  
2.7  
V
VDD = 0.8V  
VDD  
—
VDD = 1.1V to 1.3V  
VDD = 1.4V to 1.6V  
VDD = 1.65V to 1.95V  
VDD = 2.3V to 2.7V  
VDD = 0.8V  
0.65 x VDD  
—
VIH  
VIL  
Input HIGH Voltage Level  
InputLOWVoltageLevel  
0.65 x VDD  
—
V
V
0.65 x VDD  
1.7  
—
—
—
—
—
0
—
—
0
VDD = 1.1V to 1.3V  
VDD = 1.4V to 1.6V  
VDD = 1.65V to 1.95V  
VDD = 2.3V to 2.7V  
0.35 x VDD  
0.35 x VDD  
0.35 x VDD  
0.7  
2.7  
VDD  
2.7  
–0.7  
–3  
VI  
InputVoltage  
V
V
VO  
OutputVoltage  
ActiveState  
3-State  
0
0
VDD = 0.8V  
VDD = 1.1V  
VDD = 1.4V  
VDD = 1.65V  
VDD = 2.3V  
VDD = 0.8V  
VDD = 1.1V  
VDD = 1.4V  
VDD = 1.65V  
VDD = 2.3V  
—
—
—
—
—
—
—
—
—
—
—
–40  
IOH  
IOL  
HIGH Level Output Current  
LOWLevelOutputCurrent  
–5  
mA  
mA  
–8  
–9  
0.7  
3
5
8
9
Δt/Δv  
InputTransitionRiseorFallTime  
OperatingFree-AirTemperature  
20  
ns/V  
° C  
TA  
+85  
NOTE:  
1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(1)  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
OperatingConditions:TA =–40°Cto+85°C  
Symbol  
IIH  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Input HIGH or LOW Current  
AllInputs  
VDD = 2.7V, VI = VDD or GND  
—
—
±5  
µ A  
IIL  
IOFF  
IOZH  
IOZL  
IDDL  
IDDH  
IDDZ  
Input/OutputPowerOffLeakage  
HighImpedanceOutputCurrent  
(3-StateOutputPins)  
VDD = 0V, VIN or VO ≤ 2.7V  
—
—
—
—
—
—
—
—
±10  
±10  
±10  
20  
µ A  
µA  
VDD = 2.7V  
VO = VDD  
VO = GND  
QuiescentPowerSupplyCurrent  
VDD = 0.8V to 2.7V  
VIN = GND or VDD  
µ A  
NOTE:  
1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.  
4
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
OUTPUTDRIVECHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
VDD - 0.1  
—
Typ.  
—
Max.  
—
Unit  
VOH  
OutputHIGHVoltage  
VDD = 0.8V - 2.7V  
VDD = 0.8V  
IOH = –100μA  
IOH = –0.7mA  
IOH = –3mA  
IOH = –5mA  
IOH = –8mA  
IOH = –9mA  
IOH = 100μA  
IOL = 0.7mA  
IOL = 3mA  
0.55  
—
—
(2)  
VDD = 1.1V  
0.8  
—
V
(3)  
VDD = 1.4V  
1
—
—
(4)  
VDD = 1.65V  
1.2  
—
—
(5)  
VDD = 2.3V  
1.8  
—
—
VOL  
Output LOWVoltage  
VDD = 0.8V - 2.7V  
VDD = 0.8V  
—
—
0.2  
—
—
0.25  
—
(2)  
VDD = 1.1V  
—
0.3  
0.4  
0.45  
0.6  
V
(3)  
VDD = 1.4V  
IOL = 5mA  
—
—
(4)  
VDD = 1.65V  
IOL = 8mA  
—
—
(5)  
VDD = 2.3V  
IOH = 9mA  
—
—
NOTES:  
1. VIL and VIH must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS table for the appropriate VDD range. TA = -40°C to +85°C.  
2. Demonstrates operation for nominal VDD = 1.2V.  
3. Demonstrates operation for nominal VDD = 1.5V.  
4. Demonstrates operation for nominal VDD = 1.8V.  
5. Demonstrates operation for nominal VDD = 2.5V.  
OPERATING CHARACTERISTICS, TA = 25°C  
Symbol Parameter  
Test Conditions  
CL = 0pF  
VDD = 0.8V VDD = 1.2V  
VDD = 1.5V  
VDD = 1.8V  
VDD = 2.5V Unit  
CPD  
PowerDissipationCapacitance  
21  
22  
23  
25  
29  
pF  
OutputsEnabled  
f = 10MHz  
CPD  
PowerDissipationCapacitance  
OutputsDisabled  
5
5
6
7
10  
pF  
SWITCHINGCHARACTERISTICS(1)  
VDD = 0.8V VDD = 1.2V±0.1V VDD = 1.5V±0.1V  
VDD = 1.8V±0.15V  
VDD = 2.5V±0.2V  
Symbol  
tPLH  
Parameter  
PropagationDelay xDx to xQx  
xLE to xQx  
Typ.  
8
Min.  
1.1  
Max.  
3.8  
Min.  
0.6  
Max.  
2.4  
Min.  
Typ.  
1.5  
Max.  
Min.  
0.6  
Max.  
1.9  
Unit  
0.7  
0.7  
0.8  
2.4  
2.8  
2.9  
ns  
tPHL  
10.6  
9
1.4  
4.9  
0.7  
3.2  
1.6  
0.6  
2.1  
tPZH  
tPZL  
OutputEnableTime  
xOE to xQx  
OutputDisableTime  
xOE to xQx  
1.3  
4.5  
0.6  
2.9  
1.7  
0.7  
2.2  
ns  
ns  
tPHZ  
tPLZ  
13  
2.4  
7
2.4  
4.8  
1.1  
2.7  
4.6  
0.4  
2.5  
tSU  
tH  
Set-upTime,DatabeforeLE↓  
HoldTime,DataafterLE↓  
Pulse Duration, LE HIGH  
1.7  
—
4.2  
0.7  
1.2  
2.9  
—
—
—
0.5  
0.8  
2.3  
—
—
—
0.4  
0.7  
2.1  
—
—
—
—
—
—
0.4  
0.6  
1.7  
—
—
—
ns  
ns  
ns  
tW  
NOTE:  
1. See TEST CIRCUITS AND WAVEFORMS. TA = -40°C to +85°C.  
5
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDWAVEFORMS  
TESTCONDITIONS(1)  
Symbol  
VLOAD  
VT  
VDD = 0.8V  
2xVDD  
VDD/2  
100  
VDD = 1.2V±0.1V  
VDD = 1.5V±0.1V  
VDD = 1.8V±0.15V  
VDD = 2.5V±0.2V  
Unit  
V
2xVDD  
VDD/2  
100  
100  
2
2xVDD  
VDD/2  
100  
100  
2
2xVDD  
VDD/2  
150  
150  
1
2xVDD  
VDD/2  
150  
V
VLZ  
mV  
mV  
KΩ  
pF  
VHZ  
100  
150  
RL  
2
0.5  
CL  
15  
15  
15  
30  
30  
VDD  
VT  
0V  
VLOAD  
Open  
GND  
VDD  
SAME PHASE  
INPUT TRANSITION  
tPHL  
tPHL  
tPLH  
tPLH  
VOH  
VT  
VOL  
RL  
OUTPUT  
VIN  
VOUT  
Pulse(1)  
D.U.T.  
RT  
Generator  
VDD  
VT  
0V  
OPPOSITE PHASE  
INPUT TRANSITION  
RL  
CL  
Propagation Delay  
Test Circuits for All Outputs  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
NOTE:  
DISABLE  
ENABLE  
VDD  
VT  
CONTROL  
INPUT  
0V  
tPZL  
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; Slew Rate ≥ 1V/ns.  
tPLZ  
VLOAD/2  
VT  
VLOAD/2  
OUTPUT  
NORMALLY  
LOW  
SWITCHPOSITION  
SWITCH  
CLOSED  
VOL + VLZ  
VOL  
Test  
Switch  
VLOAD  
GND  
tPHZ  
tPZH  
Open Drain  
Disable Low  
Enable Low  
OUTPUT  
NORMALLY  
HIGH  
VOH  
VOH - VHZ  
SWITCH  
OPEN  
VT  
0V  
0V  
Disable High  
Enable High  
NOTE:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
All Other Tests  
Open  
Enable and Disable Times  
VDD  
LOW-HIGH-LOW  
PULSE  
VT  
0V  
TIMING  
VT  
INPUT  
0V  
tW  
tSU  
VT  
tH  
VDD  
VT  
VDD  
0V  
HIGH-LOW-HIGH  
PULSE  
DATA  
INPUT  
VT  
Setup and Hold Times  
Pulse Width  
6
IDT74AUC16373  
1.8VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
IDT  
XX  
XX  
AUC  
X
XX  
XXX  
X
Package  
Family  
Device Type  
Temp.  
Temp. Range  
Bus- Hold  
I
Industrial Temperature Range  
Very Fine Pitch Ball Grid Array  
Thin Shrink Small Outline Package  
Thin Very Small Outline Package  
BV  
PA  
PF  
373  
16-Bit Transparent D-Type Latch  
with 3-State Outputs  
16  
Double-Density  
Blank  
74  
No bus-hold  
– 40°C to +85°C  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
logichelp@idt.com  
www.idt.com  
7

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