IDT74FCT161TP [IDT]
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS; FAST CMOS可预置同步二进制计数器
| 型号： | IDT74FCT161TP |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS |
| 文件： | 总7页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT161T/AT/CT
IDT54/74FCT163T/AT/CT
FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS
Integrated Device Technology, Inc.
DESCRIPTION:
FEATURES:
TheIDT54/74FCT161T/163T,IDT54/74FCT161AT/163AT
and IDT54/74FCT161CT/163CT are high-speed synchro-
nous modulo-16 binary counters built using an advanced dual
metal CMOS technology. They are synchronously preset-
table for application in programmable dividers and have two
types of count enable inputs plus a terminal count output for
versatility in forming synchronous multi-stage counters. The
IDT54/74FCT161T/AT/CT have asynchronous Master Reset
inputsthatoverrideallotherinputsandforcetheoutputsLOW.
The IDT54/74FCT163T/AT/CT have Synchronous Reset in-
puts that override counting and parallel loading and allow the
outputs to be simultaneously reset on the rising edge of the
clock.
• Std., A and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
FUNCTIONAL BLOCK DIAGRAMS
P
0
P1
P2
P3
PE
'161
'163
CEP
CET
163
ONLY
TC
161
ONLY
CP
CP
CP
D CP D
C
D
Q
Q
Q
0
Q
0
DETAIL
DETAIL
DETAIL
A
A
A
DETAIL A
MR ('161)
SR ('163)
Q
0
Q
1
Q
2
Q
3
2611 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1994
1995 Integrated Device Technology, Inc.
6.7
DSC-4219/4
1
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
IDT54/74FCT861 10-BIT TRANSCEIVERS
3
2
20 19
18
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
*R
CP
Vcc
TC
4
5
6
7
8
Q
Q
0
1
P
P
NC
0
1
1
P16-1,
D16-1,
S016-1,
S016-7
&
17
16
15
14
Q
0
P
0
1
L20-2
NC
Q2
P
Q
1
P
P
2
3
P
P
2
3
Q2
Q3
Q
3
10 11 12 13
9
E16-1
CEP
GND
CET
PE
2611 drw 03
2611 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
*MR for '161
*SR for ‘163
PIN DESCRIPTION
FUNCTION TABLE(2)
Pin Names
Description
Action on the Rising
Clock Edge(s)
(1)
CET CEP
SR
L
PE
X
CEP
CET
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
X
X
H
L
X
X
H
X
L
Reset (Clear)
H
L
Load (Pn→Qn)
CP
H
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
MR (‘161)
SR (‘163)
P0-3
H
H
X
NOTES:
1. 163 only.
2611 tbl 02
PE
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Q0-3
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care.
TC
Terminal Count Output
2611 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2611 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2611 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.7
2
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
COM'L(5)
MIL
2.0V
2.7V
—
—
—
—
V
V
VIL
IIH
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
0.8
±1
V
µA
µA
µA
V
Input HIGH Current(4)
Input LOW Current(4)
Input HIGH Current(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VI = 2.7V
IIL
VCC = Max.
VI = 0.5V
—
—
±1
II
VCC = Max., VI = VCC (Max.)
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
—
±1
VIK
IOS
VOH
—
–0.7
–120
3.3
–1.2
–225
—
–60
2.4
mA
V
VCC = Min.
IOH = –6mA MIL.
VIN = VIH or VIL
IOH = –8mA COM’L.
IOH = –12mA MIL.
IOH = –15mA COM’L.
2.0
—
3.0
0.3
—
V
V
VOL
Output LOW Voltage
Input Hysteresis
VCC = Min.
VIN = VIH or VIL
IOL= 32mA MIL.
0.5
IOL= 48mA COM’L.
VH
—
—
—
200
—
1
mV
mA
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
0.01
NOTES:
2611 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = -55°C.
5. Clock pin requires a minimum VIH of 2.5V.
6.7
3
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
—
0.5
2.0
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
VCC = Max., Outputs Open
Load Mode
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
CEP = CET = PE = GND
MR or SR = VCC
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
Load Mode
fCP = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = VCC
One Bit Toggling
at fi = 5MHz
VIN = VCC
VIN = GND
—
—
1.5
2.0
3.5
5.5
mA
VIN = 3.4V
VIN = GND
50% Duty Cycle
VCC = Max., Outputs Open
Load Mode
fCP = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = VCC
Four Bits Toggling
at fi = 5MHz
VIN = VCC
VIN = GND
—
—
3.8
5.0
7.3(5)
VIN = 3.4V
VIN = GND
12.3(5)
50% Duty Cycle
2611 tbl 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.7
4
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161T
IDT54/74FCT161AT
IDT54/74FCT161CT
IDT54/74FCT163CT
IDT54/74FCT163T
IDT54/74FCT163AT
Com'l.
Mil.
Com'l.
Mil.
Com'l
Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Symbol
Parameter
Condition(1) Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
7.5 2.0
Max. Min. Max. Unit
tPLH
tPHL
Propagation Delay
CP to Qn
(PE Input HIGH)
CL = 50pF
RL = 500Ω
2.0 11.0 2.0 11.5 2.0
7.2
6.2
2.0
2.0
5.8
5.8
2.0
6.3
ns
ns
tPLH
tPHL
Propagation Delay
CP to Qn
2.0
9.5
2.0 10.0 2.0
6.5
2.0
2.0
6.3
(PE Input LOW)
tPLH
tPHL
Propagation Delay
CP to TC
2.0 15.0 2.0 16.5 2.0
1.5 8.5 1.5 9.0 1.5
9.8
5.5
8.5
7.5
—
2.0 10.8 2.0
7.4
5.2
6.0
7.0
—
2.0
1.5
2.0
2.0
4.5
8.3
5.6
6.6
7.7
—
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
CET to TC
1.5
2.0
2.0
4.5
5.9
9.1
8.2
—
1.5
2.0
2.0
4.0
tPHL
tPHL
tSU
Propagation Delay
MR to Qn ('161)
2.0 13.0 2.0 14.0 2.0
2.0 11.5 2.0 12.5 2.0
Propagation Delay
MR to TC ('161)
Set-up Time,
5.0
1.5
—
—
5.5
2.0
—
—
4.0
1.5
HIGH or LOW
Pn to CP
tH
Hold Time,
HIGH or LOW
Pn to CP
—
2.0
—
1.5
—
2.0
—
ns
tSU
tH
Set-up Time,
HIGH or LOW
PE or SR to CP
11.5
1.5
11.5
0
—
—
—
—
13.5
1.5
13.0
0
—
—
—
—
9.5
1.5
9.5
0
—
—
—
—
11.5
1.5
11.0
0
—
—
—
—
9.5
1.5
9.5
0
—
—
—
—
11.5
1.5
11.0
0
—
—
—
—
ns
ns
ns
ns
Hold Time,
HIGH or LOW
PE or SR to CP
tSU
tH
Set-up Time,
HIGH or LOW
CEP or CET to CP
Hold Time,
HIGH or LOW
CEP or CET to CP
tW
tW
Clock Pulse
Width (Load)
HIGH or LOW
5.0
7.0
—
—
5.0
8.0
—
—
4.0(3)
6.0
—
—
4.0(3)
7.0
—
—
4.0(3)
6.0
—
—
4.0(3)
7.0
—
—
ns
ns
Clock Pulse
Width (Count)
HIGH or LOW
tW
MR Pulse Width,
LOW ('161)
5.0
6.0
—
—
5.0
6.0
—
—
4.0(3)
5.0
—
—
4.0(3)
5.0
—
—
4.0(3)
5.0
—
—
4.0(3)
5.0
—
—
ns
ns
tREM
Recovery Time
MR to CP ('161)
NOTES:
2611 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
6.7
5
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500
500
Ω
Ω
Enable Low
VOUT
VIN
Open
Pulse
Generator
All Other Tests
D.U.T.
2611 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
T
R
C
L
Generator.
2611 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
t
H
t
t
SU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
t
W
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
2611 drw 06
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
SU
t
H
2611 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2611 drw 07
0V
2611 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.7
6
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
FCT
X
XXXX
X
X
X
Temperature
Range
Family Device
Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
L
Leadless Chip Carrier
Small Outline IC
CERPACK
SO
E
Q
Quarter-size Small Outline Package
161T
Synchronous Binary Counter
with Asynchronous Master Reset
163T
161AT
163AT
Blank High Drive
54
74
-55°C to +125°C
0° to +70°C
2611 drw 09
6.7
7
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