IDT74FCT162260ATEG [IDT]
Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56;
| 型号： | IDT74FCT162260ATEG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56 CD 逻辑集成电路 |
| 文件： | 总8页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT54/74FCT162260AT/CT/ET
12-BIT TRI-PORT
BUS EXCHANGER
FEATURES:
DESCRIPTION:
−
−
−
−
−
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
The FCT162260AT/CT/ET Tri-Port Bus Exchangers are high-speed
12-bitlatchedbusmultiplexers/transceiversforuseinhigh-speedmicropro-
cessorapplications. TheseBus Exchangers supportmemoryinterleaving
withlatchedoutputs onthe Bports andaddress multiplexingwithlatched
inputs onthe Bports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be
transferred between the A port and either/both of the B ports. The latch
enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
Whena latch-enable inputis high,the latchis transparent. Whena latch-
enableinputislow,thedataattheinputislatchedandremainslatcheduntil
thelatchenableinputisreturnedhigh. Independentoutputenables(OE1B
and OE2B) allow reading from one port while writing to the other port.
−
25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and
25 mil pitch CERPACK packages
Extended commercial range of -40°C to +85°C
VCC = 5V ±10%
−
−
−
Balanced Output Drivers:
•
•
±24mA (commercial)
±16mA (military)
−
−
Reduced system switching noise
Typical V (Output Ground Bounce) < 0.6V at V = 5V, T =
25°C
The FCT162260AT/CT/ET have balanced output drive with current
limitingresistors. Thisofferslowgroundbounce,minimalundershoot,and
controlledoutputfalltimes-reducingtheneedforexternalseriesterminating
OLP
CC
A
resistors.
FUNCTIONALBLOCKDIAGRAM
29
OE1B
30
LEA1B
A-1B
LATCH
1B1:12
12
2
LE1B
1B-A
12
LATCH
12
12
28
SEL
1
OEA
1
M
A1:12
U
12
X
0
12
12
2B-A
27
LATCH
12
LE2B
A-2B
LATCH
55
2B1:12
12
LEA2B
56
OE2B
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-5430/-
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE2B
LEA2B
2B4
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
V
2
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
3
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
5v16-link
4
GND
2B5
5
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
6
2B6
7
VCC
8
2B7
A2
9
2B8
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
A3
10
11
12
13
2B9
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
O
CAPACITANCE
Symbol
(TA = +25 C, f = 1.0MHz)
Parameter(1)
Conditions
Typ.
Max. Unit
A5
CIN
Input Capacitance
VIN = 0V
3.5
6
8
pF
COUT
Output Capacitance
VOUT = 0V
3.5
pF
5v16-link
A6
14 SO56-1
SO56-2
15
NOTE:
A7
SO56-3
E56-1
1. This parameter is measured at characterization but not tested.
A8
16
A9
17
18
19
20
21
22
23
24
25
26
GND
A10
A11
A12
VCC
1B1
1B2
1B8
1B7
VCC
1B6
1B5
GND
1B3
GND
1B4
27
28
LE2B
SEL
LEA1B
OE1B
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
2
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
PINDESCRIPTION
Signal
A(1:12)
I/O
I/O
I/O
I/O
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
BidirectionalData Port1B. Connectedtothe evenpathorevenbankofmemory.
BidirectionalDataPort2B. Connectedtotheoddpathoroddbankofmemory.
1B(1:12)
2B(1:12)
LEA1B
Latch Enable Input for A-1BLatch. The Latchis openwhen LEA1B is HIGH. Data from the A-port is latched on the HIGHto LOW transition
of LEA1B.
LEA2B
LE1B
LE2B
SEL
I
I
I
I
LatchEnable InputforA-2BLatch. The Latchis openwhenLEA2Bis HIGH. Data fromthe A-Portis latchedonthe HIGHto LOWtransition
of LEA2B.
LatchEnableInputforthe1B-ALatch. TheLatchisopenwhenLE1BisHIGH. Datafromthe1BportislatchedontheHIGHtoLOWtransition
of LE1B.
LatchEnableInputforthe2B-ALatch. TheLatchisopenwhenLE2BisHIGH. Datafromthe2BportislatchedontheHIGHtoLOWtransition
of LE2B.
1Bor2BPathSelection. WhenHIGH,SELenablesdatatransferfrom1BPorttoAPort. WhenLOW,SELenablesdatatransferfrom2BPort
to A Port.
OEA
OE1B
OE2B
I
I
I
Output Enable for A Port (Active LOW).
Output Enable for 1B Port (Active LOW).
Output Enable for 2B Port (Active LOW).
FUNCTION TABLES(1)
Inputs
Output
A
1B
H
L
2B
X
X
X
H
L
SEL
H
LE1B LE2B
OEA
L
H
H
L
X
X
X
H
H
L
H
L
H
L
(1)
X
X
X
X
X
H
L
A
L
X
X
X
X
L
H
L
L
L
(1)
X
X
L
L
A
X
X
H
Z
Inputs
Outputs
A
H
L
LEA1B LEA2B OE1B OE2B
1B
2B
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
(1)
H
L
B
(1)
L
B
(1)
H
L
H
H
L
B
H
(1)
L
B
L
(1)
(1)
X
X
X
X
L
B
B
X
X
X
X
X
X
X
X
Z
Z
Active
Z
Z
Active
Active
X
Active
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
3
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 5.0V ±10%; Military: TA = -55°C to +125°C, VCC = 5.0V ±10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
Typ.(2) Max.
Unit
VIH
2
—
—
—
0.8
±1
V
VIL
IIH
Input LOW Level
Input HIGH Current (Input pins)(5)
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
—
V
VI = VCC
—
µA
(5)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)(5)
—
±1
IIL
VI = GND
—
±1
(5)
Input LOW Current (I/O pins)
—
±1
IOZH
IOZL
VIK
IOS
High Impedance Output Current
(3-State Output pins)(5)
Clamp Diode Voltage
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
VCC = Min., IIN = –18mA
–0.7
–140
100
5
–1.2
–250
—
V
(3)
Short Circuit Current
VCC = Max., VO = GND
mA
mV
µA
VH
Input Hysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
5v16-link
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2) Max.
Unit
(3)
IODL
Output LOW Current
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
60
115
–115
3.3
200
–200
—
mA
(3)
IODH
VOH
Output HIGH Current
Output HIGH Voltage
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
–60
2.4
mA
V
VCC = Min.
IOH = –16mA MIL.
VIN = VIH or VIL
VCC = Min.
IOH = –24mA COM’L.
IOL = 16mA MIL.
VOL
Output LOW Voltage
—
0.3
0.55
V
VIN = VIH or VIL
IOL = 24mA COM’L
5v16-link
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = -55°C.
4
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
VCC = Max.
—
0.5
1.5
mA
(3)
VIN = 3.4V
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
Outputs Open
VIN = VCC
—
60
100
µA/
VIN = GND
MHz
One Output Port Enabled
LExx = VCC
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN = VCC
—
0.6
0.9
1.5
2.3
mA
Outputs Open
fi = 10MHz
VIN = GND
50% Duty Cycle
One Output Port Enabled
LExx = VCC
VIN = 3.4V
VIN = GND
—
One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
—
—
1.8
4.8
3.5(5)
VIN = GND
50% Duty Cycle
One Output Port Enabled
LExx = VCC
VIN = 3.4V
VIN = GND
12.5(5)
Twelve Input Bits Toggling
Twelve Output Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162260AT
FCT162260CT
FCT162260ET
Com'l. Mil.
Com'l. Mil.
Com'l. Mil.
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Propagation Delay
Condition(1) Min (2) Max Min (2) Max Min (2) Max Min (2) Max Min (2) Max Min (2) Max Unit
.
.
.
.
.
.
.
.
.
.
.
.
CL = 50pF
RL = 500
1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5 3.6
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Ax to 1Bx or Ax to 2Bx
Propagation Delay
1Bx to Ax or 2Bx to Ax
Propagation Delay
LExB to Ax
Ω
1.5 5.6 1.5 5.9 1.5 1.5 5.4 1.5 3.6
5
—
—
—
—
—
—
1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5
1.5 4.7 1.5 5.2 1.5 4.4 1.5 4.8 1.5
1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5
4
4
4
Propagation Delay
LEA1B to 1Bx or LEA2B to 2Bx
Propagation Delay
SEL to Ax
Output Enable Time
1.5 5.7 1.5 6.1 1.5 5.1 1.5 5.4 1.5 4.4
to Ax,
to 1BX, or
to 2Bx
to 2Bx
OEA
Output Disable Time
to Ax, to 1BX, or
OE1B
OE2B
1.5 4.4 1.5 4.8 1.5
4
1.5 4.4 1.5
4
OEA
OE1B
OE2B
tSU
Set-Up Time, HIGH or LOW Data to Latch
Hold Time, Latch to Data
1.5
1
—
—
—
0.5
1.5
1.5
3
—
—
—
0.5
1
1
—
—
—
0.5
1
1.5
3
—
—
—
0.5
1
1
—
—
—
0.5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
tH
(4)
tW
Pulse Width, Latch HIGH
3
3
3
(3)
tSK(o)
Output Skew
—
—
—
—
—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
6
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
Test
Switch
Closed
Open
V CC
7.0V
Open Drain
Disable Low
Enable Low
All Other Tests
500Ω
500Ω
VOUT
VIN
Pulse
Generator
D.U.T.
5v16-link
DEFINITIONS:
50pF
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
T
R
L
C
SET-UP, HOLD, AND RELEASE TIMES
PULSEWIDTH
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
tSU
tH
ENABLEANDDISABLETIMES
PROPAGATIONDELAY
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
7
IDT54/74FCT162260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
MILITARYANDCOMMERCIALTEMPERATURERANGES
ORDERINGINFORMATION
IDT
X
FCT
XXX
XXXX
X
X
Temperature
Range
Family Device
Type
Package
Process
Blank
Commercial
B
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
PV
PA
PF
E
260AT
260CT
260ET
12-Bit Tri-Port Bus Exchanger
162
Double-Density, 5 Volt, Balanced Drive
54
74
– 55°C to +125°C
– 40°C to +85°C
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
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