IDT74FCT16260CTPA8 [IDT]
Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74FCT16260CTPA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT74FCT16260AT/CT/ET
12-BIT TRI-PORT
BUS EXCHANGER
DESCRIPTION:
FEATURES:
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit latched
busmultiplexers/transceiversforuseinhigh-speedmicroprocessorapplica-
tions. TheseBusExchangerssupportmemoryinterleavingwithlatchedoutputs
ontheBportsandaddressmultiplexingwithlatchedinputsontheBports.
TheTri-PortBusExchangerhasthree12-bitports. Datamaybetransferred
betweentheAportandeither/bothoftheBports. Thelatchenable(LE1B,LE2B,
LEA1BandLEA2B)inputscontroldatastorage. Whenalatch-enableinputis
high,thelatchistransparent. Whenalatch-enableinputislow,thedataatthe
inputislatchedandremainslatcheduntilthelatchenableinputisreturnedhigh.
Independent output enables (OE1B and OE2B) allow reading from one port
whilewritingtotheotherport.
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 5V ±10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
TheFCT16260Tisideallysuitedfordrivinghighcapacitanceloadsandlow
impedancebackplanes. Theoutputbuffersaredesignedwithpoweroffdisable
capabilitytoallow"liveinsertion"ofboardswhenusedasbackplanedrivers.
• Power off disable outputs permit “live insertion”
• Available in SSOP and TSSOP packages
FUNCTIONALBLOCKDIAGRAM
29
OE1B
30
LEA1B
A-1B
LATCH
1B1:12
12
2
LE1B
1B-A
12
LATCH
12
12
28
SEL
1
OEA
1
M
A1:12
U
12
X
0
12
12
2B-A
27
LATCH
12
LE2B
A-2B
LATCH
55
56
2B1:12
12
LEA2B
OE2B
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5431/3
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE2B
LEA2B
2B4
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
3
4
GND
2B5
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
5
6
2B6
7
VCC
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
8
2B7
A2
9
2B8
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2B9
CAPACITANCE (TA = +25°C, F = 1.0MHz)
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
COUT
VOUT = 0V
3.5
A5
NOTE:
A6
1. This parameter is measured at characterization but not tested.
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
1B8
1B7
VCC
1B6
1B5
GND
1B3
GND
1B4
27
28
LE2B
SEL
LEA1B
OE1B
SSOP/ TSSOP
TOP VIEW
2
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Signal
I/O
I/O
I/O
I/O
I
Description
A(1:12)
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
BidirectionalDataPort2B. Connectedtotheoddpathoroddbankofmemory.
1B(1:12)
2B(1:12)
LEA1B
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to
LOWtransitionofLEA1B.
LEA2B
LE1B
LE2B
SEL
I
I
I
I
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to
LOWtransitionofLEA2B.
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH
to LOW transition of LE1B.
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH
to LOW transition of LE2B.
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data
transfer from 2B Port to A Port.
OEA
OE1B
OE2B
I
I
I
Output Enable for A Port (Active LOW)
Output Enable for 1B Port (Active LOW)
Output Enable for 2B Port (Active LOW)
FUNCTIONTABLES(1)
Inputs
Output
1B
H
L
2B
X
X
X
H
L
SEL
H
LE1B
LE2B
OEA
A
H
H
H
L
X
X
X
H
H
L
L
L
L
L
L
L
H
H
L
A(1)
X
X
X
X
X
H
L
X
X
X
X
H
L
L
A(1)
X
X
L
X
X
Z
Inputs
Outputs
A
H
L
LEA1B LEA2B OE1B OE2B
1B
H
2B
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
B(1)
B(1)
H
L
L
H
L
H
H
L
B(1)
B(1)
B(1)
Z
L
L
B(1)
X
X
X
X
X
L
X
X
X
X
X
X
X
X
Z
Active
Z
Z
Active
Active
Active
NOTES:
1. Output level before the indicated steady-state input conditions were established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
3
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
0.8
±1
V
IIH
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VI = VCC
—
—
µA
—
—
±1
IIL
VI = GND
—
—
±1
—
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
—
±1
µA
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
–1.2
–250
V
IOS
Short Circuit Current
–80
mA
VH
Input Hysteresis
—
—
—
100
5
—
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
OutputDriveCurrent
Output HIGH Voltage
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min.
Typ.(2)
Max.
Unit
IO
–50
2.5
2.4
2
—
3.5
3.5
3
–180
—
mA
VOH
VCC = Min.
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VIN = VIH or VIL
—
V
V
—
VOL
OutputLOWVoltage
VCC = Min.
—
0.2
0.55
VIN = VIH or VIL
IOFF
Input/OutputPowerOffLeakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
—
—
±1
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = –55°C.
4
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
One Output Port Enabled
LExx = VCC
One Input Bit Togging
One Output Bit Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
LExx = VCC
VIN = VCC
VIN = GND
—
—
0.6
0.9
1.5
2.3
mA
VIN = 3.4V
VIN = GND
One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
1.8
4.8
3.5(5)
50% Duty Cycle
One Output Port Enabled
LExx = VCC
VIN = 3.4V
VIN = GND
12.5(5)
Twelve Input Bits Toggling
Twelve Output Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V).
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT16260AT
FCT16260CT
FCT16260ET
Symbol
tPLH
Parameter
PropagationDelay
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
1.5
1.5
1.5
1.5
1.5
1.5
5.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.6
ns
tPHL
Ax to 1Bx or Ax to 2Bx
PropagationDelay
tPLH
5.6
5.2
4.7
5.2
5.7
4.4
5
3.6
4
ns
ns
ns
ns
ns
ns
tPHL
1Bx to Ax or 2Bx to Ax
PropagationDelay
tPLH
4.7
4.4
4.7
5.1
4
tPHL
LExB to Ax
tPLH
PropagationDelay
4
tPHL
LEA1B to 1Bx or LEA2B to 2Bx
PropagationDelay
tPLH
4
tPHL
SEL to Ax
tPZH
tPZL
OutputEnableTime
4.4
4
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
OutputDisableTime
tPHZ
tPLZ
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
Set-up Time HIGH or LOW Data to Latch
HoldTime,LatchtoData
Pulse Width, Latch HIGH (4)
OutputSkew(3)
tSU
tH
1.5
1
—
—
1
1
—
—
1
1
—
—
ns
ns
ns
ns
tW
3
—
3
—
3
—
tSK(o)
—
0.5
—
0.5
—
0.5
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
6
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
Test
Switch
Closed
Open
Open Drain
Disable Low
Enable Low
V CC
7.0V
All Other Tests
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
V OUT
VIN
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Pulse
Generator
D.U.T.
50pF
CL
500Ω
RT
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
Pulse Width
tSU
tH
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
7
IDT74FCT16260AT/CT/ET
FASTCMOS12-BITTRI-PORTBUSEXCHANGER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XXX
XX
Temp. Range
Family
Package
Device Type
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
260AT 12-Bit Tri-Port Bus Exchanger
260CT
260ET
16
74
Double-Density, 5 Volt, Balanced Drive
– 40°C to +85°C
DATASHEETDOCUMENTHISTORY
1/21/2002 RemovedMilitarytempgrade
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8
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