IDT74FCT162H501ATPFB [IDT]
FAST CMOS 18-BIT REGISTERED TRANSCEIVER; FAST CMOS 18位寄存收发器
| 型号： | IDT74FCT162H501ATPFB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 18-BIT REGISTERED TRANSCEIVER |
| 文件： | 总9页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT16501AT/CT/ET
IDT54/74FCT162501AT/CT/ET
IDT54/74FCT162H501AT/CT/ET
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
Integrated Device Technology, Inc.
CMOS technology. These high-speed, low-power 18-bit reg-
istered bus transceivers combine D-type latches and D-type
flip-flopstoallowdataflowintransparent, latchedandclocked
modes. Data flow in each direction is controlled by output-
enable (OEAB and OEBA), latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,
thedeviceoperatesintransparentmodewhenLEABisHIGH.
When LEAB is LOW, the A data is latched if CLKAB is held at
a HIGH or LOW logic level. If LEAB is LOW, the A bus data
isstoredinthelatch/flip-flopontheLOW-to-HIGHtransitionof
CLKAB. OEAB is the output enable for the B port. Data flow
fromtheBporttotheAportissimilarbutrequiresusing OEBA,
LEBA and CLKBA. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤ 1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
• Features for FCT16501AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
The FCT16501AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
• Features for FCT162501AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
The FCT162501AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimalundershoot,andcontrolledoutputfalltimes–reducing
the need for external series terminating resistors. The
FCT162501AT/CT/ET are plug-in replacements for the
FCT16501AT/CT/ET and ABT16501 for on-board bus inter-
face applications.
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
• Features for FCT162H501AT/CT/ET:
– Bus Hold retains last active bus state during 3-state
– Eliminates the need for external pull up resistors
The FCT162H501AT/CT/ET have "Bus Hold" which re-
tains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
DESCRIPTION:
The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18-
bitregisteredtransceiversarebuiltusingadvanceddualmetal
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
C
B1
A1
D
D
C
D
C
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2547 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.10
DSC-2547/8
1
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
OEAB
LEAB
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
LEAB
A1
2
CLKAB
B1
2
CLKAB
A1
3
B
1
3
GND
4
GND
GND
A2
4
GND
B2
A
2
3
5
B
B
V
B
B
B
2
5
A
6
3
A3
6
B3
VCC
7
CC
4
VCC
A4
7
VCC
B4
A4
A5
A6
8
8
9
5
A5
9
B5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
6
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B6
GND
GND
GND
A7
GND
B7
A7
A8
A9
B
B
B
B
B
B
7
8
A8
B8
9
SO56-1
SO56-2
SO56-3
A9
B9
E56-1
A10
A11
A12
10
11
12
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
GND
GND
A13
A14
A15
B
B
B
V
B
B
13
14
15
CC
16
17
VCC
A16
A17
GND
GND
A18
B18
CLKBA
GND
OEBA
LEBA
OEBA
LEBA
2547 drw 03
2547 drw 02
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.10
2
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1,4)
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Description
A-to-B Output Enable Input
Inputs
Outputs
Bx
OEAB
LEAB
CLKAB
Ax
X
L
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
L
X
H
H
L
X
X
X
↑
Z
L
H
H
H
H
H
H
B-to-A Latch Enable Input
H
L
H
A-to-B Clock Input
L
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
L
↑
H
X
X
H
L
L
B(2)
B(3)
Bx
L
H
NOTE:
2547 tbl 01
1. On FCT16xH501T these pins have “Bus Hold”. All other pins are standard
inputs, outputs or I/Os.
NOTES:
2547 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
ABSOLUTE MAXIMUM RATINGS(1)
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
Symbol
Description
Max.
Unit
(2) Terminal Voltage with Respect to
VTERM
–0.5 to +7.0
V
GND
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
(3) Terminal Voltage with Respect to
GND
VTERM
–0.5 to
VCC +0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
–60 to +120 mA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
2547 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Symbol
Parameter(1)
Input
Conditions
Typ. Max. Unit
CIN
VIN = 0V
3.5
6.0
pF
Capacitance
I/O
CI/O
VOUT = 0V
3.5
8.0
pF
Capacitance
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
2547 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
5.10
3
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
–80
—
—
—
—
—
0.8
±1
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VCC = Max.
VI = VCC
—
µA
—
±1
II L
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
100
5
–1.2
–225
—
V
IOS
VH
Short Circuit Current
mA
mV
µA
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
2547 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16501T
Symbol
Parameter
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min. Typ.(2) Max.
Unit
IO
Output Drive Current
–50
2.5
2.4
—
3.5
3.5
–180
—
mA
VOH
Output HIGH Voltage
VCC = Min.
IOH = –3mA
V
V
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(4)
IOL = 48mA MIL.
—
2.0
—
3.0
0.2
—
—
0.55
±1
V
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 64mA COM'L.
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2547 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162501T
Symbol
Parameter
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
Min. Typ.(2) Max.
Unit
IODL
Output LOW Current
60
–60
2.4
115
200
mA
VOUT = 1.5V(3)
IODH
VOH
Output HIGH Current
Output HIGH Voltage
VCC = 5V, VIN = VIH or VIL,
–115 –200
mA
V
VCC = Min.
IOH = –16mA MIL.
IOH = –24mA COM'L.
IOL = 16mA MIL.
3.3
0.3
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
—
0.55
V
VIN = VIH or VIL
IOL = 24mA COM'L.
2547 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.10
4
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Input LOW Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
VIL
Guaranteed Logic LOW Level
0.8
V
I
I
I H
Input
Standard Input(5)
V
CC = Max.
V
I
I
= VCC
—
±
1
1
µA
HIGH
Current(4)
Standard I/O(5)
Bus-Hold Input
Bus-Hold I/O
—
±
—
±
100
100
—
±
I L
Input
LOW
Standard Input(5)
Standard I/O(5)
V
= GND
—
±
1
1
—
±
Current(4) Bus-Hold Input
—
±
100
100
—
Bus-Hold I/O
—
±
I
I
BHH
BHL
Bus Hold
Bus-Hold Input
VCC = Min.
V
I
I
= 2.0V
= 0.8V
–50
+50
µ
A
A
Sustain
Current(4)
V
—
I
I
OZH
OZL
High Impedance Output Current
(3-State Output pins)(5,6)
Clamp Diode Voltage
VCC = Max.
V
O
O
= 2.7V
= 0.5V
—
—
—
—
±
1
1
µ
V
±
VIK
V
CC = Min., IIN = –18mA
—
–0.7
–1.2
V
I
OS
Short Circuit Current
V
CC = Max., V
O
= GND(3)
–80
—
–
140
100
5
–
225
mA
mV
V
H
Input Hysteresis
—
—
I
I
I
CCL
CCH
CCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
500
µA
2547 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus Hold I/O pins.
5.10
5
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
—
0.5
1.5
mA
VIN = 3.4V(3)
ICCD
IC
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
VCC = Max., Outputs Open
OEAB = OEBA = VCC or GND VIN = GND
One Input Toggling
VIN = VCC
—
75
120
µA/
MHz
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
VIN = VCC
VIN = GND
—
—
0.8
1.3
1.7
3.2
mA
VIN = 3.4V
VIN = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
VIN = VCC
VIN = GND
—
—
3.8
8.5
6.5(5)
VIN = 3.4V
VIN = GND
20.8(5)
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
2547 tbl 09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.10
6
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16501AT/162501AT
Com'l. Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
FCT16501CT/162501CT
FCT16501ET/162501ET
Com'l. Mil.
Com'l. Mil.
Symbol
Parameter
fMAX CLKAB or CLKBA frequency(4) CL = 50pF
—
150
—
150
—
150
—
150
—
150
—
—
—
—
MHz
ns
tPLH Propagation Delay
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time
tPZL OEBA to Ax, OEAB to Bx
tPHZ Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
RL = 500Ω 1.5 5.1 1.5 5.6 1.5 4.6 1.5 4.6 1.5 3.8
1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.6 1.5 4.2
1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.4 1.5 4.2
1.5 6.0 1.5 6.4 1.5 5.6 1.5 6.0 1.5 4.8
1.5 5.6 1.5 6.0 1.5 5.2 1.5 5.6 1.5 5.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
3.0
0
—
—
—
—
—
—
—
0.5
3.0
0
—
—
—
—
—
—
—
0.5
3.0
0
—
—
—
—
—
—
—
0.5
3.0
0
—
—
—
—
—
—
—
0.5
2.4
0
—
—
—
—
—
—
—
0.5
tH
tSU
Set-up Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock
LOW
Clock
HIGH
3.0
1.5
1.5
3.0
3.0
—
3.0
1.5
1.5
3.0
3.0
—
3.0
1.5
1.5
3.0
3.0
—
3.0
1.5
1.5
3.0
3.0
—
2.0
1.5
0.5
3.0
3.0
—
tH
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width
tW
tW
(4)
HIGH
CLKAB or CLKBA Pulse Width
HIGH or LOW(4)
tSK(o) Output Skew(3)
NOTES:
2547 tbl 10
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5.10
7
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500
Ω
Ω
Enable Low
VOUT
VIN
Open
Pulse
Generator
All Other Tests
D.U.T.
2547 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
500
T
R
C
L
Generator.
2547 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
t
H
t
t
SU
1.5V
3V
1.5V
0V
TIMING
INPUT
t
W
ASYNCHRONOUS CONTROL
t
REM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
1.5V
ETC.
2547 drw 06
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
SU
t
H
2547 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
V
OL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
V
OH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2547 drw 07
0V
2547 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.10
8
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
X
IDT
FCT
X
X
XXXX
X
X
Temperature
Range
Drive Bus Hold Device Type Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
501AT
501CT
501ET
Non-Inverting 18-Bit Registered Transceiver
Blank
H
Standard
Bus Hold
16
162
16-Bit High Drive
16-Bit Balanced Drive
54
74
–55°C to +125°C
–40°C to +85°C
2547 drw 09
5.10
9
相关型号：
IDT74FCT162H501ATPFG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56
IDT
IDT74FCT162H501ATPV8
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56
IDT
IDT74FCT162H501ATPVG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56
IDT
IDT74FCT162H501CTEG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56
IDT
IDT74FCT162H501CTPA8
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
©2020 ICPDF网 联系我们和版权申明