IDT74FCT162H952ETPV8 [IDT]
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56;
| 型号： | IDT74FCT162H952ETPV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
16-BIT REGISTERED
TRANSCEIVER
IDT74FCT162H952AT/CT/ET
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT162H952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separateinputandoutputcontrolforindependentcontrolofdataflowineither
direction.Forexample,theA-to-BEnable(xCEAB) mustbelowtoenterdata
fromtheAport.xCLKABcontrolstheclockingfunction.WhenxCLKABtoggles
fromlow-to-high,thedatapresentontheAportwillbeclockedintotheregister.
xOEABperformsthe outputenablefunctionontheBport.Dataflowfromthe
BporttoAportissimilarbutrequiresusingxCEBA,xCLKBA,andxOEBAinputs.
Full16-bitoperationis achievedbytyingthe controlpins ofthe independent
transceiverstogether.
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤ 1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
• Available in SSOP and TSSOP packages
The FCT162H952T has "Bus Hold" which retains the input's last state
whenevertheinputgoestohighimpedance. Thisprevents"floating"inputsand
eliminatestheneedforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
54
31
2CEBA
1CEBA
30
55
2CLKBA
1CLKBA
28
1
2OEAB
1OEAB
26
3
2CEAB
1CEAB
2
27
2CLKAB
1CLKAB
29
56
2OEBA
1OEBA
C
CE
D
C
5
15
CE
2A1
1A1
42
52
D
1B1
2B1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5441/3
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1OEBA
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
2
1CLKAB
1CLKBA
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
3
1CEAB
GND
1CEBA
GND
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
4
5
1A1
1B1
NOTES:
6
1A2
1B2
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VCC
7
VCC
8
1A3
1A4
1B3
1B4
9
2. All device terminals except FCT162XXX Output and I/O terminals.VCC terminals.
3. Outputs and I/O terminals for FCT162XXX.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1A5
1B5
GND
GND
1A6
1A7
1A8
2A1
2A2
1B6
1B7
1B8
2B1
2B2
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
2A3
2B3
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
GND
GND
COUT
VOUT = 0V
3.5
2A4
2A5
2B4
2B5
NOTE:
1. This parameter is measured at characterization but not tested.
2A6
2B6
VCC
VCC
2A7
2B7
2A8
2B8
GND
GND
2CEBA
2CEAB
FUNCTIONTABLE(1, 3)
2CLKAB
2CLKBA
Inputs
Outputs
2OEAB
2OEBA
xCEAB
xCLKAB
xOEAB
xAx
X
xBx
(2)
SSOP/ TSSOP
TOP VIEW
H
X
L
X
L
↑
↑
X
L
L
L
L
H
B
(2)
X
B
L
L
H
Z
PINDESCRIPTION
L
H
X
X
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
Description
NOTES:
A-to-BOutputEnableInput(ActiveLOW)
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
B-to-AOutputEnableInput(ActiveLOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
and xOEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs(1)
B-to-ADataInputsorA-to-B3-StateOutputs(1)
xBx
NOTE:
1. These pins have “Bus Hold”. All other pins are standard inputs, outputs or I/Os.
2
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
InputLOWLevel
Input
Test Conditions(1)
GuaranteedLogicHIGHLevel
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
GuaranteedLogicLOWLevel
—
—
—
—
—
—
—
—
—
–50
50
—
0.8
V
(5)
IIH
StandardInput
VCC = Max.
VI = VCC
—
±1
µA
(5)
HIGH
Current(4)
StandardI/O
—
±1
Bus-holdInput
Bus-hold I/O
—
±100
±100
±1
—
(5)
IIL
Input
StandardInput
VI = GND
—
(5)
LOW
Current(4)
StandardI/O
—
±1
Bus-holdInput
Bus-hold I/O
Bus-holdInput
—
±100
±100
—
—
IBHH
IBHL
IOZH
IOZL
VIK
Bus-holdSustain
VCC = Min.
VI = 2V
—
µ A
µ A
(4)
Current
VI = 0.8V
VO = 2.7V
VO = 0.5V
—
—
HighImpedanceOutputCurrent
VCC = Max.
—
—
—
–80
—
—
—
±1
(5,6)
(3-StateOutputpins)
—
±1
ClampDiodeVoltage
ShortCircuitCurrent
VCC = Min., IIN = –18mA
–0.7
–140
100
5
–1.2
–250
—
V
(3)
IOS
VCC = Max., VO = GND
—
mA
mV
µ A
VH
InputHysteresis
ICCL
ICCH
ICCZ
QuiescentPowerSupplyCurrent
VCC = Max
500
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
OutputLOWCurrent
Output HIGH Current
OutputHIGHVoltage
Test Conditions(1)
Min.
60
Typ.(2) Max.
Unit
mA
mA
V
(3)
IODL
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
115
–115
3.3
200
–200
—
(3)
IODH
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
–60
2.4
VOH
VCC = Min.
IOH = –24mA
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 24mA
—
0.3
0.55
V
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus-hold are identified in the pin description.
5. The test limit for this parameter is ±5µA at TA = –55°C.
6. Does not include Bus-hold I/O pins.
3
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply
CurrentTTLInputs HIGH
DynamicPowerSupplyCurrent(4)
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
VCC = Max.
—
0.5
1.5
mA
(3)
VIN = 3.4V
ICCD
IC
VCC = Max.
OutputsOpen
xOEAB or xOEBA = GND
OneInputToggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
75
120
1.7
3.2
µA/
MHz
TotalPowerSupplyCurrent(6)
VCC = Max.
VIN = VCC
—
0.8
mA
OutputsOpen
fCP = 10MHz (xCLKAB)
50% Duty Cycle
VIN = GND
xOEAB = xCEAB = GND
xOEBA = VCC
OneBitToggling
fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
1.3
3.8
50% Duty Cycle
(5)
VCC = Max.
VIN = VCC
6.5
OutputsOpen
VIN = GND
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
(5)
xOEBA = VCC
SixteenBitsToggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
—
8.3
20
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT162H952AT
FCT162H952CT FCT162H952ET
Symbol
tPLH
Parameter
PropagationDelay
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
2
10
2
6.3
1.5
3.7
ns
tPHL
xCLKAB, xCLKBA to xBx, xAx
OutputEnableTime
tPZH
tPZL
1.5
1.5
2.5
2
10.5
10
1.5
1.5
2.5
1.5
3
7
1.5
1.5
1.5
0
4.4
3.6
—
—
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
ns
xOEBA, xOEAB to xAx, xBx
OutputDisableTime
tPHZ
tPLZ
6.5
—
—
—
—
—
0.5
xOEBA, xOEAB to xAx, xBx
Set-up Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
Hold Time HIGH or LOW
tSU
—
—
—
—
—
0.5
tH
tSU
tH
xAx, xBx to xCLKAB, xCLKBA
Set-up Time, HIGH or LOW
xCEAB, xCEBA to xCLKAB, xCLKBA
Hold Time HIGH or LOW
3
2
2
2
0
xCEAB, xCEBA to xCLKAB, xCLKBA
Pulse Width HIGH or LOW
tW
3
3
3
(3)
xCLKAB or xCLKBA
(4)
tSK(o)
OutputSkew
—
—
—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Guaranteed but not tested.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VCC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
Pulse Width
tSU
tH
CLOCK ENABLE
ETC.
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT162H952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXX
XXXX
X
X
Device Type
Temp. Range
Family
Bus Hold
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
952AT
952CT
952ET
16-Bit Registered Transceiver
H
Bus Hold
162
Double-Density, 5 Volt, Balanced Drive
- 40°C to +85°C
74
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www.idt.com
7
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