IDT74FCT163244APVG8 [IDT]

Bus Driver, FCT Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, GREEN, SSOP-48;
IDT74FCT163244APVG8
型号: IDT74FCT163244APVG8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Bus Driver, FCT Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, GREEN, SSOP-48

驱动 光电二极管 逻辑集成电路
文件: 总6页 (文件大小:72K)
中文:  中文翻译
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3.3V CMOS 16-BIT  
BUFFER/LINE DRIVER  
IDT74FCT163244A/C  
DESCRIPTION:  
FEATURES:  
The FCT16324416-bitbuffer/line drivers are builtusingadvanceddual  
metalCMOStechnology. Thesehigh-speed,low-powerdevicesofferbus/  
backplane interface capability with improved packing density. These  
deviceshaveaflow-throughorganizationforsimplifyingboardlayout. The  
three-statecontrols operatethesedevices inaQuad-Nibble,Dual-Byteor  
single 16-bit word mode. All inputs are designed with hysteresis for  
improvednoise margin.  
The inputs of the FCT163244 can be driven from either 3.3V or 5V  
devices. This feature allows the use of these devices as translators in a  
mixed 3.3V/5V supply system. Thus, the FCT163244 can be used as  
buffers toconnect5Vcomponents toa 3.3Vbus.  
• 0.5 MICRON CMOS Technology  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended  
Range  
• CMOS power levels (0.4μ W typ. static)  
• Rail-to-rail output swing for increased noise margin  
Low Ground Bounce (0.3V typ.)  
Inputs (except I/O) can be driven by 3.3V or 5V components  
Available in SSOP, TSSOP, and TVSOP packages  
FUNCTIONALBLOCKDIAGRAM  
25  
1
1OE  
3OE  
13  
14  
2
3
36  
35  
47  
46  
1
1
1
1
Y1  
Y2  
Y3  
Y4  
1
A
1
2
3
3
Y
Y
1
2
3A1  
3
A
A
A
2
1A  
16  
17  
5
6
33  
32  
44  
43  
3
3
4
3
3
Y
Y
3
4
1A  
3
4
1A  
3
24  
48  
2OE  
4OE  
19  
20  
8
9
30  
29  
41  
40  
2
Y
1
4
4
4
Y
Y
Y
1
2
3
2
A
A
A
1
2
3
4
A
A
A
1
2
3
2
2
2
2
2
Y2  
Y3  
Y4  
4
4
22  
23  
11  
12  
27  
26  
38  
37  
2
A4  
4
A4  
4
Y
4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
SEPTEMBER 2009  
1
© 2009 Integrated Device Technology, Inc.  
DSC-2532/12  
IDT74FCT163244A/C  
3.3VCMOS16-BITBUFFER/LINEDRIVER  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Max  
Unit  
V
(2)  
VTERM  
Terminal Voltage with Respect to GND  
Terminal Voltage with Respect to GND  
–0.5 to +4.6  
–0.5 to 7  
(3)  
VTERM  
V
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
OE  
2
OE  
(4)  
VTERM  
Terminal Voltage with Respect to GND –0.5 to VCC+0.5  
V
2
1
Y
1
2
1A  
1
2
TSTG  
IOUT  
Storage Temperature  
DC Output Current  
–65 to +150  
–60 to +60  
° C  
mA  
3
1
Y
1A  
NOTES:  
GND  
4
GND  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Vcc terminals.  
5
1
Y
3
4
1A  
3
6
1
Y
1A  
4
V
CC  
7
V
CC  
3. Input terminals.  
4. Outputs and I/O terminals.  
8
2
2
Y
1
2
2A  
1
9
2A  
2
Y
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
GND  
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
2A  
2A  
3A  
3A  
3
4
1
2
2
2
3
3
Y3  
Y4  
Y1  
Y2  
Symbol  
CIN  
Parameter(1)  
Input Capacitance  
Output Capacitance  
Conditions  
VIN = 0V  
Typ.  
3.5  
Max. Unit  
6
8
pF  
pF  
COUT  
VOUT = 0V  
3.5  
NOTE:  
1. This parameter is measured at characterization but not tested.  
GND  
GND  
3A  
3
3
3
Y
3
4
Y
3A  
4
PINDESCRIPTION  
V
CC  
V
CC  
Pin Names  
xOE  
Description  
3-State Output Enable Inputs (Active LOW)  
Data Inputs  
4A  
1
4
4
Y
1
2
xAx  
4A  
2
Y
xYx  
3-State Outputs  
GND  
GND  
4A  
3
4
4
4
Y
3
4
FUNCTIONTABLE(1)  
4A  
Y
Inputs  
Outputs  
4OE  
3OE  
xOE  
L
xAx  
L
xYx  
L
L
H
H
SSOP/ TSSOP/ TVSOP  
TOP VIEW  
H
X
Z
NOTE:  
1. H = HIGH Voltage Level  
X = Don’t Care  
L = LOW Voltage Level  
Z = High-Impedance  
2
IDT74FCT163244A/C  
3.3VCMOS16-BITBUFFER/LINEDRIVER  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
2
Typ.(2)  
Max.  
Unit  
VIH  
Input HIGH Level (Input pins)  
Input HIGH Level (I/O pins)  
Guaranteed Logic HIGH Level  
5.5  
V
2
VCC+0.5  
VIL  
IIH  
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level  
–0.5  
–36  
0.8  
1
V
Input HIGH Current (Input pins)  
Input HIGH Current (I/O pins)  
Input LOW Current (Input pins)  
Input LOW Current (I/O pins)  
High Impedance Output Current  
(3-State Output pins)  
VCC = Max.  
VI = 5.5V  
VI = VCC  
1
µA  
IIL  
VI = GND  
VI = GND  
VO = VCC  
VO = GND  
1
1
IOZH  
IOZL  
VIK  
VCC = Max.  
1
µA  
1
Clamp Diode Voltage  
VCC = Min., IIN = –18mA  
–0.7  
–60  
–1.2  
–110  
V
(3)  
IODH  
Output HIGH Current  
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V  
mA  
mA  
(3)  
IODL  
VOH  
Output LOW Current  
Output HIGH Voltage  
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V  
50  
VCC-0.2  
2.4  
90  
3
200  
VCC = Min.  
IOH = –0.1mA  
VIN = VIH or VIL  
VCC = 3V  
IOH = –3mA  
IOH = –8mA  
V
2.4(5)  
3
VIN = VIH or VIL  
VCC = Min.  
VOL  
OutputLOWVoltage  
IOL = 0.1mA  
IOL = 16mA  
IOL = 24mA  
IOL = 24mA  
0.2  
0.3  
0.3  
0.2  
0.4  
VIN = VIH or VIL  
0.55  
0.5  
V
VCC = 3V  
VIN = VIH or VIL  
(3)  
IOS  
VH  
Short Circuit Current(4)  
VCC = Max., VO = GND  
–60  
–135  
–240  
mA  
Input Hysteresis  
150  
0.1  
10  
mV  
µ A  
ICCL  
ICCH  
ICCZ  
Quiescent Power Supply Current  
VCC = Max.  
VIN = GND or VCC  
NOTES:  
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at VCC = 3.3V, +25°C ambient.  
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.  
4. This parameter is guaranteed but not tested.  
5. VOH = VCC–0.6V at rated current.  
3
IDT74FCT163244A/C  
3.3VCMOS16-BITBUFFER/LINEDRIVER  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Typ.(2)  
Max.  
Unit  
ΔICC  
Quiescent Power Supply Current  
TTL Inputs HIGH  
VCC = Max.  
VIN = VCC - 0.6V  
2
30  
µ A  
(3)  
ICCD  
IC  
Dynamic Power Supply  
Current(4)  
VCC = Max.  
Outputs Open  
xOE = GND  
One Input Togging  
50% Duty Cycle  
VIN = VCC  
VIN = GND  
50  
75  
µA/  
MHz  
Total Power Supply Current(6)  
VCC = Max.  
Outputs Open  
fi = 10MHz  
VIN = VCC  
VIN = GND  
0.5  
0.5  
2
0.8  
0.8  
mA  
50% Duty Cycle  
xOE = GND  
One Bit Toggling  
VIN = VCC - 0.6V  
VIN = GND  
(5)  
VCC = Max.  
VIN = VCC  
3
Outputs Open  
fi = 2.5MHz  
VIN = GND  
50% Duty Cycle  
xOE = GND  
Sixteen BitsTogging  
VIN = VCC - 0.6V  
VIN = GND  
2
3.3(5)  
NOTES:  
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at VCC = 3.3V, +25°C ambient.  
3. Per TTL driven input. All other inputs at VCC or GND.  
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.  
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.  
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC  
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)  
ICC = Quiescent Current (ICCL, ICCH and ICCZ)  
ΔICC = Power Supply Current for a TTL High Input  
DH = Duty Cycle for TTL Inputs High  
NT = Number of TTL Inputs at DH  
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)  
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)  
NCP = Number of Clock Inputs at fCP  
fi = Input Frequency  
Ni = Number of Inputs at fi  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)  
FCT163244A  
FCT163224C  
Symbol Parameter  
Condition(2)  
CL = 50pF  
RL = 500Ω  
Min.(3)  
Max.  
Min.(3)  
Max.  
Unit  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
tSK(o)  
PropagationDelay  
1.5  
4.8  
1.5  
1.5  
1.5  
4.1  
ns  
ns  
ns  
ns  
xAx to xYx  
OutputEnableTime  
1.5  
1.5  
6.2  
5.6  
0.5  
5.8  
5.2  
0.5  
OutputDisableTime  
(4)  
OutputSkew  
NOTES:  
1. Propagation Delays and Enable/Disable times are with VCC = 3.3V±0.3V (normal range). For VCC = 2.7 to 3.6V (extended range), all Propagation Delays and Enable/Disable  
times should be degraded by 20%.  
2. See test circuit and waveforms.  
3. Minimum limits are guaranteed but not tested on Propagation Delays.  
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.  
4
IDT74FCT163244A/C  
3.3VCMOS16-BITBUFFER/LINEDRIVER  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDWAVEFORMS  
SWITCHPOSITION  
Test  
Switch  
6V  
6v  
Open Drain  
Disable Low  
Enable Low  
V
CC  
Open  
GND  
500  
Ω
Disable High  
Enable High  
GND  
Open  
V
OUT  
V
IN  
Pulse  
Generator  
All Other Tests  
D.U.T  
.
50pF  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
500  
Ω
T
R
L
C
Test Circuits for All Outputs  
3V  
DATA  
1.5V  
0V  
INPUT  
LOW-HIGH-LOW  
PULSE  
tH  
tSU  
1.5V  
1.5V  
3V  
1.5V  
0V  
TIMING  
INPUT  
t
W
ASYNCHRONOUS CONTROL  
tREM  
PRESET  
3V  
1.5V  
0V  
CLEAR  
ETC.  
HIGH-LOW-HIGH  
PULSE  
SYNCHRONOUS CONTROL  
3V  
1.5V  
0V  
PRESET  
CLEAR  
CLOCK ENABLE  
ETC.  
tSU  
tH  
Pulse Width  
Set-up, Hold, and Release Times  
ENABLE  
DISABLE  
3V  
1.5V  
0V  
3V  
SAME PHASE  
CONTROL  
INPUT  
1.5V  
0V  
INPUT TRANSITION  
t
PLH  
t
PHL  
PHL  
t
PZL  
tPLZ  
VOH  
OUTPUT  
3V  
1.5V  
3V  
1.5V  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
6V  
VOL  
tPLH  
t
0.3V  
0.3V  
VOL  
3V  
1.5V  
0V  
tPZH  
tPHZ  
OPPOSITE PHASE  
INPUT TRANSITION  
VOH  
OUTPUT  
NORMALLY  
HIGH  
SWITCH  
GND  
1.5V  
0V  
Propagation Delay  
0V  
Enable and Disable Times  
NOTES:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.  
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.  
5
IDT74FCT163244A/C  
3.3VCMOS16-BITBUFFER/LINEDRIVER  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XX  
FCT  
XXX  
XXXX  
X
Device Type  
Temp. Range  
Family  
Package  
PVG  
PAG  
PFG  
Shrink Small Outline Package - Green  
Thin Shrink Small Outline Package - Green  
Thin Very Small Outline Package - Green  
244A  
244C  
Non-Inverting 16-Bit Buffer/Line Driver  
Double-Density 3.3Volt  
163  
74  
40°C to +85°C  
DatasheetDocumentHistory  
09/10/09 Pg.6  
Updatedthe orderinginformationbyremovingthe "IDT"notationandnonRoHSpart.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
logichelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
6

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