IDT74FCT163501APV8 [IDT]
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56;
| 型号： | IDT74FCT163501APV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56 光电二极管 |
| 文件： | 总7页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT
REGISTERED TRANSCEIVER
IDT74FCT163501A/C
DESCRIPTION:
FEATURES:
TheFCT16350118-bitregisteredtransceiversarebuiltusingadvanced
dual metal CMOS technology. These high-speed, low-power 18-bit
registeredbustransceiverscombineD-typelatchesandD-typeflip-flopsto
allowdataflowintransparent,latchedandclockedmodes. Dataflowineach
directionis controlledbyoutput-enable (OEABandOEBA), latchenable
(LEABandLEBA)andclock(CLKABandCLKBA)inputs. ForA-to-Bdata
flow,the device operates intransparentmode whenLEABis high. When
LEABislow,theAdataislatchedifCLKABisheldatahighorlowlogiclevel.
IfLEABislow,theAbusdataisstoredinthelatch/flip-floponthelow-to-high
transitionofCLKAB. OEABperformstheoutputenablefunctionontheBport.
Data flowfromBporttoAportis similiarbutrequires using OEBA,LEBA
andCLKBA. Flow-throughorganizationofsignalpinssimplifieslayout. All
inputs are designedwithhysteresis forimprovednoise margin.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4μ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP, TSSOP, and TVSOP packages
The FCT163501 has series current limiting resistors. These offer low
ground bounce, minimal undershoot, and controlled output fall times-
reducingthe needforexternalseries terminatingresistors.
FUNCTIONALBLOCKDIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
55
CLKAB
2
LEAB
C
C
54
B1
3
D
A1
D
C
D
C
D
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
APRIL 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-2776/7
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
OEAB
LEAB
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to 7
2
(3)
VTERM
V
(4)
3
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +60
° C
mA
GND
A2
4
GND
B2
5
NOTES:
A3
6
B3
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
VCC
A4
7
VCC
B4
8
A5
9
B5
3. Input terminals.
4. Outputs and I/O terminals.
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B6
GND
A7
GND
B7
A8
B8
CAPACITANCE (TA = +25°C, F = 1.0MHz)
A9
B9
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
CIN
VIN = 0V
3.5
6
8
pF
pF
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTIONTABLE(1,4)
Inputs
Outputs
Bx
OEAB
L
LEAB
X
CLKAB
Ax
X
L
X
X
X
↑
Z
L
H
H
H
H
H
L
H
L
OEBA
LEBA
H
L
H
L
↑
H
X
X
H
(2)
H
L
L
B
SSOP/ TSSOP/ TVSOP
TOP VIEW
(3)
H
L
H
B
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and
PINDESCRIPTION
CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Pin Names
Description
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
A-to-BOutputEnableInput
B-to-AOutputEnableInput(ActiveLOW)
A-to-BLatchEnableInput
Z = High-Impedance
↑ = LOW-to-HIGH Transition
B-to-ALatchEnableInput
A-to-B Clock Input
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
Bx
2
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
2
Typ.(2)
—
Max.
Unit
VIH
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Guaranteed Logic HIGH Level
5.5
V
2
—
VCC+0.5
VIL
IIH
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
–0.5
—
—
—
—
—
—
—
–36
—
0.8
1
V
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VI = 5.5V
VI = VCC
—
—
1
µA
IIL
VI = GND
VI = GND
VO = VCC
VO = GND
—
1
—
1
IOZH
IOZL
VIK
VCC = Max.
—
1
µA
—
1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
–0.7
–60
–1.2
–110
V
(3)
IODH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
mA
mA
(3)
IODL
VOH
Output LOW Current
Output HIGH Voltage
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
50
VCC-0.2
2.4
90
—
3
200
—
—
—
VCC = Min.
IOH = –0.1mA
VIN = VIH or VIL
VCC = 3V
IOH = –3mA
IOH = –8mA
V
2.4(5)
3
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
VIN = VIH or VIL
0.55
0.5
V
VCC = 3V
VIN = VIH or VIL
(3)
IOS
VH
Short Circuit Current(4)
VCC = Max., VO = GND
–60
–135
–240
mA
Input Hysteresis
—
—
—
150
0.1
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
3
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = VCC - 0.6V
—
2
30
µA
(3)
ICCD
IC
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OEAB = OEBA = VCC or GND
One Input Togging
50% Duty Cycle
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
Total Power Supply Current(6)
VCC = Max.,Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
VIN = VCC
VIN = GND
—
0.6
1
mA
OEAB = OEBA = VCC
LEAB = GND
fI = 5MHz
VIN = VCC - 0.6V
VIN = GND
—
—
0.6
3
1
50% Duty Cycle
One Bit Toggling
VCC = Max.,Outputs Open
(5)
VIN = VCC
5
fCP = 10MHz (xCLKAB)
50% Duty Cycle
VIN = GND
OEAB = OEBA = VCC
LEAB = GND
(5)
fI = 2.5MHz
VIN = VCC - 0.6V
VIN = GND
—
3
5.3
50% Duty Cycle
Eighteen Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)
FCT163501A
FCT163501C
Min.(3)
Symbol Parameter
Condition(2)
CL = 50pF
RL = 500Ω
Min.(3)
Max.
150
5.1
Max.
150
4.6
Unit
ns
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
CLKAB or CLKBA frequency
—
—
PropagationDelay
1.5
1.5
ns
Ax to Bx or Bx to Ax
PropagationDelay
1.5
1.5
1.5
1.5
3
5.6
5.6
6
1.5
1.5
1.5
1.5
3
5.3
5.3
5.6
5.2
—
—
ns
ns
ns
ns
ns
ns
ns
ns
LEBA to Ax, LEAB to Bx
PropagationDelay
CLKBA to Ax, CLKAB to Bx
OutputEnableTime
OEBA to Ax, OEAB to Bx
OutputDisableTime
5.6
—
—
OEBA to Ax, OEAB to Bx
Set-up Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
tH
0
0
tSU
tH
Clock LOW
Clock HIGH
3
—
—
—
3
—
—
—
1.5
1.5
1.5
1.5
(4)
tW
LEAB or LEBA Pulse Width HIGH
3
3
—
—
0.5
3
3
—
—
0.5
ns
ns
ns
(4)
tW
CLKAB or CLKBA Pulse Width HIGH or LOW
(5)
tSK(o)
OutputSkew
—
—
NOTES:
1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable
times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
6v
Test
Switch
6V
VCC
Open
Open Drain
Disable Low
Enable Low
GND
500Ω
VOUT
VIN
Disable High
Enable High
GND
Open
Pulse
Generator
D.U.T.
All Other Tests
50pF
500Ω
T
R
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tSU
tH
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Set-up, Hold, and Release Times
ENABLE
tPZL
DISABLE
tPLZ
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
0.3V
0.3V
VOL
VOH
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
Propagation Delay
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
6
IDT74FCT163501A/C
3.3VCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXX
XXXX
X
Device Type
Temp. Range
Family
Package
PV
PA
PF
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
501A
501C
Non-Inverting 18-Bit Registered Transceiver
Double-Density 3.3Volt
163
74
− 40°C to +85°C
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
logichelp@idt.com
www.idt.com
7
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