IDT74FCT163543APF8 [IDT]

Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TVSOP-56;


型号：	IDT74FCT163543APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TVSOP-56 光电二极管输出元件逻辑集成电路电视
文件：	总7页 (文件大小：123K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 16-BIT

LATCHED TRANSCEIVER

IDT74FCT163543/A/C

FEATURES:

DESCRIPTION:

−

0.5 MICRON CMOS Technology

Typical tSK(o) (Output Skew) < 250ps

The FCT163543/A/C 16-bit latched transceivers are built using ad-

vanced dual metal CMOS technology. These high-speed, low-power

devices are organizedas twoindependent8-bitD-type latchedtransceiv-

ers withseparateinputandoutputcontroltopermitindependentcontrolof

dataflowineitherdirection.Forexample,theA-to-BEnable(xCEAB)must

be low in order to enter data from the A port or to output data from the B

port. xLEABcontrols the latchfunction. WhenxLEABis low,the latches

aretransparent.Asubsequentlow-to-hightransitionofxLEABsignalputs

theAlatchesinthestoragemode.xOEABperformsoutputenablefunction

onthe Bport.Data flowfromthe Bporttothe Aportis similarbutrequires

usingxCEBA, xLEBA, andxOEBAinputs. Flow-throughorganizationof

signal pins simplifies layout. All inputs are designed with hysteresis for

improvednoise margin.

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

V^CC= 3.3V ±0.3V, Normal Range or V^CC= 2.7V to 3.6V, Extended

Range

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Low Ground Bounce (0.3V typ.)

−

Inputs (except I/O) can be driven by 3.3V or 5V components

Available in SSOP, TSSOP and TVSOP Packages

The FCT163543/A/C have series current limiting resistors. These

offerlowgroundbounce,minimalundershoot,andcontrolledoutputfall

times–reducingthe needforexternalseries terminatingresistors.

FUNCTIONALBLOCKDIAGRAM

2OEBA

1OEBA

2CEBA

1CEBA

2LEBA

2OEAB

1LEBA

1OEAB

2CEAB

2LEAB

1CEAB

1LEAB

2A1

1A1

2B1

1B1

TO SEVEN OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

JUNE 2000

1999 Integrated Device Technology, Inc.

DSC-3250/3

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

1OEAB

1LEAB

1OEBA

LEBA

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +7

CEAB

GND

1CEBA

GND

(4)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

TSTG

IOUT

Storage Temperature

DC Output Current

–65 to +150

–60 to +60

°C

1A1

1A2

V^CC

1A3

1B1

1B2

V^CC

3v16-link

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V^CCterminals.

1A4

1A5

1B4

1B5

GND

1A6

GND

1B6

3. Input terminals.

4. Outputs and I/O terminals.

1A7

1A8

1B7

1B8

SO56-1

SO56-2

SO56-3

CAPACITANCE (T = +25^OC, f = 1.0MHz)

Symbol

2A1

2A2

2A3

Parameter⁽¹⁾

Conditions

Typ.

Max. Unit

2B1

2B2

2B3

CIN

Input Capacitance

VIN = 0V

3.5

COUT

Output Capacitance

VOUT = 0V

3.5

3v16-link

NOTE:

GND

1. This parameter is measured at characterization but not tested.

2A4

2A5

2A6

V^CC

2A7

2A8

2B4

2B5

2B6

V^CC

2B7

2B8

FUNCTIONTABLE^(1,3)

FOR A-TO-B(SYMMETRIC WITH B-TO-A)

GND

Latch

Status

Output

Buffers

Inputs

2CEBA

2LEBA

2CEAB

2LEAB

2OEAB

xCEAB

xLEAB xOEAB

xAx to xBx

Storing

xBx

HighZ

2OEBA

Storing

SSOP/ TSSOP/ TVSOP

TOP VIEW

Transparent

Current A Inputs

Previous⁽²⁾A Inputs

Storing

Transparent

Storing

HighZ

PINDESCRIPTION

HighZ

Pin Names

Description

NOTES:

xOEAB

xOEBA

xCEAB

xCEBA

xLEAB

xLEBA

xAx

A-to-BOutputEnableInput(ActiveLOW)

B-to-AOutputEnableInput(ActiveLOW)

A-to-BEnable Input(Active LOW)

1. A-to-B data flow shown; B-to-A flow control is the same, except using

xCEBA, xLEBA and xOEBA.

2. Before xLEAB LOW-to-HIGH Transition

3. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

B-to-AEnable Input(Active LOW)

A-to-BLatchEnableInput(ActiveLOW)

B-to-ALatchEnableInput(ActiveLOW)

A-to-BDataInputsorB-to-A3-StateOutputs

B-to-ADataInputsorA-to-B3-StateOutputs

xBx

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Industrial: T^A= -40°C to +85°C, V^CC= 2.7V to 3.6V

Symbol

Parameter

Test Conditions⁽¹⁾

Guaranteed Logic HIGH Level

Min.

Typ.⁽²⁾Max.

Unit

VIH

Input HIGH Level (Input pins)

—

5.5

Vcc+0.5

0.8

Input HIGH Level (I/O pins)

Input LOW Level

VIL

II H

II L

Guaranteed Logic LOW Level

VCC = Max.

–0.5

(Input and I/O pins)

Input HIGH Current (Input pins)

Input HIGH Current (I/O pins)

Input LOW Current (Input pins)

Input LOW Current (I/O pins)

High Impedance Output Current

(3-State Output pins)

VI = 5.5V

VI = VCC

—

–0.7

–60

—

±1

µA

VI = GND

VO = VCC

VO = GND

—

±1

—

±1

IOZH

IOZL

VIK

VCC = Max.

—

±1

µA

—

±1

Clamp Diode Voltage

VCC = Min., IIN = –18mA

—

–1.2

–110

200

—

(3)

IODH

IODL

VOH

Output HIGH Current

VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V

–36

(3)

Output LOW Current

VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V

Output HIGH Voltage

VCC = Min.

IOH = –0.1mA

VCC–0.2

VIN = VIH or VIL

VCC = 3V

IOH = –3mA

IOH = –8mA

2.4

2.4⁽⁵⁾

—

VIN = VIH or VIL

VCC = Min.

VOL

Output LOW Voltage

IOL = 0.1mA

IOL = 16mA

IOL = 24mA

—

0.2

0.3

0.2

0.4

VIN = VIH or VIL

0.55

0.5

VCC = 3V

VIN = VIH or VIL

(3)

IOS

Short Circuit Current⁽⁴⁾

Input Hysteresis

VCC = Max., VO = GND

–60

—

–135

150

0.1

–240

—

µA

—

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = Max.

VIN = GND or VCC

—

3v16-link

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V^CC= 3.3V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. VOH = Vcc -0.6V at rated current.

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

POWERSUPPLYCHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

Min.

Typ.⁽²⁾

Max.

Unit

∆ICC

Quiescent Power Supply

CurrentTTLInputs HIGH

VCC = Max.

VIN = VCC –0.6V

—

µ A

(3)

ICCD

Dynamic Power Supply Current⁽⁴⁾

VCC = Max., Outputs Open

xCEAB and xOEAB = GND

xCEBA = VCC

VIN = VCC

VIN = GND

—

100

µA/

MHz

OneInputToggling

50% Duty Cycle

TotalPowerSupplyCurrent⁽⁶⁾

VCC = Max., Outputs Open

fi = 10MHz

50% Duty Cycle

xLEAB, xCEAB and

xOEAB= GND

VIN = VCC

VIN = GND

—

0.6

2.4

VIN = VCC –0.6V

VIN = GND

xCEBA = VCC

OneBitToggling

(5)

VCC = Max., Outputs Open

fi = 2.5MHz

50% Duty Cycle

xLEAB, xCEAB and

xOEAB= GND

VIN = VCC

VIN = GND

(5)

VIN = VCC –0.6V

VIN = GND

4.3

xCEBA = VCC

Sixteen BitsToggling

NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 3.3V, +25°C ambient.

3. Per TTL driven input; all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

NCP = Number of Clock Inputs at fCP

fi = Input Frequency

Ni = Number of Inputs at fi

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE ⁽⁴⁾

FCT163543

FCT163543A

FCT163543C

Symbol

tPLH Propagation Delay

tPHL Transparent Mode

xAx to xBx or xBx to xAx

Parameter

Condition⁽¹⁾

CL = 50pF

RL = 500Ω

Min ⁽²⁾

Max.

Min ⁽²⁾

Max.

Min ⁽²⁾

Max.

Unit

1.5

8.5

1.5

6.5

1.5

5.3

tPLH Propagation Delay

tPHL xLEBA to xAx, xLEAB to xBx

tPZH Output Enable Time

1.5

12.5

1.5

tPZL xOEBA or xOEAB to xAx or xBx

xCEBA or xCEAB to xAx or xBx

tPHZ Output Disable Time

1.5

7.5

1.5

6.5

tPLZ xOEBA or xOEAB to xAx or xBx

xCEBA or xCEAB to xAx or xBx

tSU Set-up Time HIGH or LOW

xAx or xBx to xLEAB or xLEBA

—

Hold Time HIGH or LOW

xAx or xBx to xLEAB or xLEBA

xLEBA or xLEAB Pulse Width LOW

—

(3)

tSK(o) Output Skew

—

0.5

—

0.5

—

0.5

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays

and Enable/Disable times should be degraded by 20%.

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

V CC

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other Tests

Open

GND

500Ω

V OUT

VIN

GND

Open

Pulse

Generator

D.U.T.

50pF

3v16-link

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

Generator.

PULSEWIDTH

SET-UP, HOLD, AND RELEASE TIMES

1.5V

DATA

INPUT

LOW-HIGH-LOW

PULSE

tSU

1.5V

TIMING

INPUT

ASYNCHRONOUS CONTROL

tREM

PRESET

CLEAR

ETC.

1.5V

HIGH-LOW-HIGH

PULSE

1.5V

SYNCHRONOUS CONTROL

1.5V

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

PROPAGATIONDELAY

ENABLEANDDISABLETIMES

ENABLE

DISABLE

SAME PHASE

INPUT TRANSITION

1.5V

CONTROL

INPUT

1.5V

tPLH

tPHL

tPZL

tPLZ

VOH

1.5V

VOL

OUTPUT

NORMALLY

LOW

SWITCH

1.5V

tPLH

0.3V

VOL

VOH

tPZH

tPHZ

OPPOSITE PHASE

INPUT TRANSITION

1.5V

OUTPUT

NORMALLY

HIGH

SWITCH

GND

1.5V

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t ≤ 2.5ns; t ≤ 2.5ns.

3. If Vcc is below 3V, input voltage swings should be adjusted not to

exceed Vcc.

IDT74FCT163543/A/C

3.3VCMOS16-BITLATCHEDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

FCT

XXX

XXXX

Device Type

Temp. Range

Family

Package

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

543

16-Bit Latched Transceiver

543A

543C

Double-Density 3.3Volt

163

− 40°C to +85°C

CORPORATE HEADQUARTERS

for SALES:

2975StenderWay

Santa Clara, CA 95054

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74FCT163543APF8 [IDT]

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