IDT74FCT163601APV8 [IDT]
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56;
| 型号： | IDT74FCT163601APV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT
IDT74FCT163601A
UNIVERSAL BUS
TRANSCEIVER WITH
3-STATE OUTPUTS
DESCRIPTION:
FEATURES:
TheFCT163601/A18-bitregisteredtransceiverisbuiltusingadvanced
dual metal CMOS technology. These 18-bit universal bus transceivers
combineD-typelatchesandD-typeflip-flopstoallowdataflowintranspar-
ent, latched and clocked modes.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-
busdataisstoredinthelatch/flip-floponthelow-to-hightransitionofCLKAB.
OutputenableOEABisactivelow. WhenOEABislow,theoutputsareactive.
When OEAB is high, the outputs are in the high-impedance state.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,CLKBA
and CLKENBA.
• VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
The FCT163601 has series current limiting resistors. These offer low
ground bounce, minimal undershoot, and controlled output fall times-
reducing the need for external series terminating resistors.
FUNCTIONALBLOCKDIAGRAM
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
1D
C1
3
54
A1
B1
CLK
CE
1D
C1
CLK
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2002
1
©
2002 Integrated Device Technology, Inc.
DSC-3251/5
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
OEAB
LEAB
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENAB
CLKAB
B1
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to 7
(3)
2
VTERM
V
(4)
3
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +60
°C
mA
GND
A2
4
GND
B2
5
NOTES:
A3
6
B3
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
VCC
A4
7
VCC
B4
8
A5
9
B5
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B6
3. Input terminals.
4. Outputs and I/O terminals.
GND
A7
GND
B7
A8
B8
A9
B9
CAPACITANCE (TA = +25°C, F = 1.0MHz)
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
B10
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
B11
CIN
VIN = 0V
3.5
6
8
pF
pF
B12
COUT
VOUT = 0V
3.5
GND
B13
NOTE:
1. This parameter is measured at characterization but not tested.
B14
B15
VCC
B16
FUNCTIONTABLE(1,4)
B17
Inputs
Outputs
GND
B18
CLKENAB
OEAB
LEAB
CLKAB
A
X
L
B
Z
L
X
X
X
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
X
X
X
↑
↑
L
CLKBA
CLKENBA
OEBA
LEBA
H
X
L
H
(2)
B0
L
L
SSOP/ TSSOP
TOP VIEW
L
L
H
X
X
H
(2)
L
L
B0
(3)
L
L
H
B0
NOTES:
PINDESCRIPTION
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA
and CLKENBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
Pin Names
Description
OEAB
OEBA
LEAB
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-BLatchEnableInput
LEBA
B-to-ALatchEnableInput
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
CLKAB
CLKBA
Ax
A-to-B Clock Input
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
A to B Clock Enable Input (Active LOW)
Bx
CLKENAB
CLKENBA
B to A Clock Enable Input (Active LOW)
2
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
2
Typ.(2)
—
Max.
5.5
Unit
VIH
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Guaranteed Logic HIGH Level
V
2
—
VCC+0.5
0.8
VIL
IIH
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
–0.5
—
—
V
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VI = 5.5V
VI = VCC
—
±1
—
—
±1
µA
IIL
VI = GND
VI = GND
VO = VCC
VO = GND
—
—
±1
—
—
±1
IOZH
IOZL
VIK
VCC = Max.
—
—
±1
µA
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–60
–1.2
–110
V
IODH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
mA
mA
IODL
VOH
Output LOW Current
Output HIGH Voltage
50
VCC-0.2
2.4
90
—
3
200
—
VCC = Min.
IOH = –0.1mA
VIN = VIH or VIL
VCC = 3V
IOH = –3mA
IOH = –8mA
—
V
2.4(5)
3
—
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
VIN = VIH or VIL
0.55
0.5
V
VCC = 3V
VIN = VIH or VIL
IOS
VH
Short Circuit Current(4)
VCC = Max., VO = GND(3)
–60
–135
–240
mA
Input Hysteresis
—
—
—
150
0.1
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
3
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
—
2
30
µA
VIN = VCC –0.6V(3)
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
OutputsOpen
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
OEAB = VCC, OEBA = GND
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max., Outputs Open
fCP = 10MHz (CLKBA)
50% Duty Cycle
OEAB = VCC, OEBA = GND
LEBA = GND
VIN = VCC
VIN = GND
—
—
0.6
0.6
1
1
mA
VIN = VCC –0.6V
VIN = GND
CLKENBA = GND
fi = 5MHz
OneBitToggling
VCC = Max., Outputs Open
fCP = 10MHz (CLKBA)
50% Duty Cycle
OEAB = VCC, OEBA = GND
LEBA = GND
VIN = VCC
VIN = GND
—
—
3
3
5(5)
VIN = VCC –0.6V
VIN = GND
5.3(5)
CLKENBA = GND
fi = 2.5MHz
EighteenBitsToggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
CLKAB or CLKBA frequency(3)
PropagationDelay
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
—
Max.
150
5.5
Unit
ns
1.5
ns
Ax to Bx or Bx to Ax
PropagationDelay
1.5
1.5
1.5
1.5
3
6.2
6.3
6.5
5.2
—
ns
ns
ns
ns
ns
ns
ns
LEBA to Ax, LEAB to Bx
PropagationDelay
CLKBA to Ax, CLKAB to Bx
OutputEnableTime
OEBA to Ax, OEAB to Bx
OutputDisableTime
OEBA to Ax, OEAB to Bx
Set-up Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time HIGH or LOW
Ax to LEAB, Bx to LEBA
Set-up Time, CLKEN to CLK
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time, CLKEN to CLK
LEAB or LEBA Pulse Width HIGH
tH
0
—
tSU
Clock LOW
Clock HIGH
2.5
2
—
—
—
—
tSU
tH
2.5
1
ns
ns
tH
0
2.5
3
—
—
ns
ns
ns
ns
tW
tW
CLKAB or CLKBA Pulse Width HIGH or LOW
OutputSkew(4)
—
tSK(o)
—
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
6v
Test
Switch
6V
VCC
Open
Open Drain
Disable Low
Enable Low
GND
500Ω
VOUT
VIN
Disable High
Enable High
GND
Open
Pulse
Generator
D.U.T.
50pF
All Other Tests
500Ω
T
R
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
0.3V
0.3V
VOL
VOH
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
6
IDT74FCT163601A
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXX
XXXX
X
Device Type
Temp. Range
Family
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
601A
Non-Inverting 18-Bit Registered Transceiver
Double-Density 3.3Volt
163
74
− 40°C to +85°C
DATASHEETDOCUMENTHISTORY
4/22/2002 Removed blank speed grade
5/21/2002 Removed TVSOP package
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
相关型号：
IDT74FCT163646AE
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56
IDT
IDT74FCT163646APA8
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
IDT74FCT163646APAG
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
IDT74FCT163646APFG
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TVSOP-56
IDT
©2020 ICPDF网 联系我们和版权申明