IDT74FCT16373AT_17 [IDT]
FAST CMOS 16-BIT TRANSPARENT LATCH;
| 型号： | IDT74FCT16373AT_17 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 16-BIT TRANSPARENT LATCH |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS 16-BIT
TRANSPARENT LATCH
IDT74FCT16373AT/CT
FEATURES:
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• VCC = 5V 10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
DESCRIPTION:
TheFCT16373T16-bit transparentD-typelatchis builtusingadvanceddual
metalCMOStechnology. Thesehigh-speed, low-powerlatchesareidealfor
temporarystorageofdata.Theycanbeusedforimplementingmemoryaddress
latches,I/Oports,andbusdrivers.TheOutputEnableandLatchEnablecontrols
areorganizedtooperateeachdeviceastwo8-bitlatches,orone16-bitlatch.
Flow-throughorganizationofsignalpinssimplifieslayout.Allinputsaredesigned
withhysteresisforimprovednoisemargin.
TheFCT16373Tisideallysuitedfordrivinghigh-capacitanceloadsandlow-
impedancebackplanes.Theoutputbuffersaredesignedwithpoweroffdisable
capabilitytoallow"liveinsertion"ofboardswhenusedasbackplanedrivers.
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
2OE
1OE
2LE
1LE
D
D
C
1D1
2D1
1O1
2O1
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JULY 2017
1
©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5454/7
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
(2)
Description
Max
Unit
V
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
1
1
LE
1OE
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
1
O
1
2
D
D
1
2
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
3
1
O
GND
4
GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
5
1
1
O
3
4
1
D
D
3
6
O
1
4
VCC
7
V
CC
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
8
1
1
O
5
1D
5
6
9
O6
1D
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
1
1
2
2
O7
O8
O1
O2
1D
1D
2D
2D
7
8
1
2
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
GND
GND
2
2
O
3
4
2
D
D
3
O
2
4
PIN DESCRIPTION
Pin Names
VCC
V
CC
Description
xDx
DataInputs
2
2
O
5
2D
5
6
xLE
Latch Enable Input (Active HIGH)
OutputEnableInput(ActiveLOW)
3-StateOutputs
O6
2D
xOE
GND
GND
xOx
2
2
O
7
8
2
2
2
D
7
8
O
D
LE
2OE
FUNCTION TABLE(1)
Inputs
Outputs
TOP VIEW
xDx
H
xLE
H
xOE
L
xOx
H
PackageType
TSSOP
PackageCode
PAG56
Order Code
PAG
L
H
L
L
X
X
H
Z
SSOP
PVG56
PVG
NOTE:
1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-impedance
2
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V 10%
Symbol
VIH
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
0.8
1
Unit
V
Input HIGH Level
VIL
InputLOWLevel
GuaranteedLogicLOWLevel
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
—
—
V
IIH
InputHIGHCurrent(Inputpins)(5)
Input HIGH Current (I/O pins)(5)
InputLOWCurrent(Inputpins)(5)
InputLOWCurrent(I/Opins)(5)
HighImpedanceOutputCurrent
(3-StateOutputpins)(5)
VI = VCC
—
µA
—
1
IIL
VI = GND
—
1
—
1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
1
µA
—
1
ClampDiodeVoltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
–140
100
5
–1.2
–250
—
500
V
IOS
ShortCircuitCurrent
mA
mV
µA
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max
VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS
Symbol
IO
Parameter
OutputDriveCurrent
Output HIGH Voltage
Test Conditions(1)
Min.
–50
2.5
2.4
2
Typ.(2) Max.
Unit
mA
V
VCC = Max., VO = 2.5V(3)
—
3.5
3.5
3
180
—
VOH
VCC = Min.
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VIN = VIH or VIL
—
V
—
V
VOL
OutputLOWVoltage
VCC = Min.
—
0.2
0.55
V
VIN = VIH or VIL
IOFF
Input/OutputPowerOffLeakage(5)
VCC = 0V, VIN = or VO ≤ 4.5V
—
—
1
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is 5µA at TA = –55°C.
3
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
OutputsOpen
xOE = GND
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max.
OutputsOpen
fi = 10MHz
VIN = VCC
VIN = GND
—
—
0.6
0.9
1.5
2.3
mA
50% Duty Cycle
xOE = GND
xLE = VCC
VIN = 3.4V
VIN = GND
OneBitToggling
VCC = Max.
OutputsOpen
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
2.4
6.4
4.5(5)
50% Duty Cycle
xOE = GND
xLE = VCC
VIN = 3.4V
VIN = GND
16.5(5)
SixteenBitsToggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16373AT
FCT16373CT
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
PropagationDelay
xDx to xOx
Condition(2)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
5.2
1.5
3.6
ns
PropagationDelay
xLE to xOx
2
8.5
6.5
5.5
2
3.7
4.4
3.9
ns
ns
ns
OutputEnableTime
1.5
1.5
1.5
1.5
OutputDisableTime
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx to xLE
xLE Pulse Width HIGH
2
1.5
5
—
—
2
1.5
5
—
—
ns
ns
ns
ns
tH
tW
—
—
tSK(o)
OutputSkew(3)
—
0.5
—
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
SWITCH POSITION
7.0V
Test
Switch
Closed
Open
500Ω
500Ω
Open Drain
Disable Low
Enable Low
V
OUT
V
IN
Pulse
Generator
D.U.T.
50pF
All Other Tests
R
T
C
L
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
INPUT
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
H
t
SU
1.5V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
REM
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
PRESET
CLEAR
CLOCK ENABLE
ETC.
Pulse Width
tSU
tH
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
t
PLH
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
t
0.3V
0.3V
VOL
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16373AT/CT
FASTCMOS16-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
ORDERING INFORMATION
XX
FCT
XXX
XXXX
Device Type
X
X
X
Package
Temp. Range
Family
Tube
Tape and Reel
Blank
8
G
Green
PV
PA
Shrink Small Outline Package (PVG48)
Thin Shrink Small Outline Package (PAG48)
373AT
373CT
16-Bit Transparent Latch
Double-Density, 5Volt, High Drive
16
74
− 40°C to +85°C
Orderable Part Information
Speed
(ns)
Pkg.
Code
Pkg.
Type
Temp.
Grade
Orderable Part ID
A
74FCT16373ATPAG
74FCT16373ATPAG8
74FCT16373ATPVG
74FCT16373ATPVG8
74FCT16373CTPAG
74FCT16373CTPAG8
74FCT16373CTPVG
74FCT16373CTPVG8
PAG48
PAG48
PVG48
PVG48
PAG48
PAG48
PVG48
PVG48
TSSOP
TSSOP
SSOP
I
I
I
I
I
I
I
I
SSOP
C
TSSOP
TSSOP
SSOP
SSOP
Datasheet Document History
09/10/2009 Pg. 7
07/31/2017 Pg. 2, 7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
Addedtableunderpinconfigurationdiagramwithdetailedpackageinformation.Updatedtheorderinginformation
diagram by adding Tube, Tape and Reel. Added orderable part information table.
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www.idt.com
7
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IDT
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