IDT74FCT163951CPF [IDT]
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER; 3.3V CMOS 16位寄存收发器
| 型号： | IDT74FCT163951CPF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER |
| 文件： | 总7页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74FCT163952A/B/C
3.3V CMOS
16-BIT REGISTERED
TRANSCEIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT163952A/B/C 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed,low-powerdevicesareorganizedastwoindepen-
dent 8-bit D-type registered transceivers with separate input
andoutputcontrolforindependentcontrolofdataflowineither
direction. For example, the A-to-B Enable (xCEAB) must be
LOW to enter data from the A port. xCLKAB controls the
clockingfunction. WhenxCLKABtogglesfromLOW-to-HIGH,
the data present on the A port will be clocked into the register.
xOEAB performs the output enable function on the B port.
Data flow from the B port to A port is similar but requires using
xCEBA, xCLKBA, and xOEBA inputs. Full 16-bit operation is
achieved by tying the control pins of the independent trans-
ceivers together.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
The FCT163952A/B/C have series current limiting resis-
tors. Theseofferlowgroundbounce, minimalundershoot, and
controlled output fall times–reducing the need for external
series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1CEBA
1CLKBA
1OEAB
1CEAB
2CEBA
2CLKBA
2OEAB
2CEAB
1CLKAB
2CLKAB
1OEBA
2OEBA
C
CE
D
C
CE
D
1A1
2A1
1B1
2B1
C
CE
C
CE
D
D
3096 drw 01
3096 drw 02
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1996 Integrated Device Technology, Inc.
AUGUST 1996
8.10
DSC-3096/4
1
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
Description
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
1
OEAB
1
56
55
54
53
52
51
50
49
48
47
46
45
44
1
1
OEBA
1
CLKAB
2
CLKBA
3
1
CEAB
1
CEBA
GND
4
GND
B-to-A Clock Input
1
1
A
1
2
5
1
1
B
B
1
2
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
A
6
xBx
V
1
CC
7
V
CC
3096 tbl 01
A3
A4
A5
8
1
B
3
4
5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
1
9
1
1
B
Description
Terminal Voltage with
Respect to GND
Max.
Unit
1
10
11
12
13
B
(2)
VTERM
–0.5 to +4.6
V
GND
GND
(3)
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
V
1
1
1
2
2
2
A6
A7
A8
A1
A2
A3
1
1
1
2
2
2
B
B
B
B
B
B
6
7
8
1
2
3
(4)
VTERM
Terminal Voltage with
Respect to GND
–0.5 to
VCC + 0.5
–65 to +150
14 SO56-1 43
SO56-2
15 SO56-3 42
TSTG
IOUT
Storage Temperature
°C
mA
DC Output Current
–60 to +60
16
17
18
19
20
21
22
23
24
25
26
27
28
41
40
39
38
37
36
35
34
33
32
31
30
29
3096 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
GND
GND
2
2
A4
A5
A6
2
2
2
B
B
B
4
5
2
6
V
2
CC
V
CC
A
7
8
2
B
7
8
2
A
2B
FUNCTION TABLE(1,3)
GND
GND
Inputs
Outputs
2
2
CEBA
2
CEAB
x
xCLKAB
x
xAx
X
xBx
B(2)
B(2)
L
CEAB
OEAB
2
CLKAB
OEAB
CLKBA
H
X
L
X
L
↑
L
L
L
L
H
2
2
OEBA
X
L
SSOP/
3096 drw 03
TSSOP/TVSOP
TOP VIEW
L
↑
H
H
X
X
X
Z
NOTES:
3096 tbl 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
1. A-to-B data flow is shown: B-to-A data flow is similar but uses, xCEBA,
xCLKBA, and xOEBA.
2. Level of B before the indicated steady-state input conditions were
established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
CIN
Input
Capacitance
I/O
VIN = 0V
3.5
3.5
6.0
pF
CI/O
VOUT = 0V
8.0
pF
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
Capacitance
3096 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
8.10
2
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
V
IH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2.0
—
5.5
CC+0.5
0.8
V
Input HIGH Level (I/O pins)
Input LOW Level
2.0
—
—
V
VIL
Guaranteed Logic LOW Level
–0.5
V
(Input and I/O pins)
I
I
I H
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
V
CC = Max.
V
V
V
V
V
V
I
I
I
I
= 5.5V
= VCC
—
—
—
—
—
—
—
—
±1
±1
±1
±1
±1
±1
µ
A
I L
= GND
= GND
—
—
I
I
OZH
OZL
VCC = Max.
O
O
= VCC
—
µA
= GND
—
V
IK
Clamp Diode Voltage
V
V
V
V
V
CC = Min., IIN = –18mA
—
–
0.7
–
1.2
V
I
I
ODH
ODL
Output HIGH Current
CC = 3.3V, VIN = VIH or VIL,
CC = 3.3V, VIN = VIH or VIL,
V
V
O
O
= 1.5V(3)
= 1.5V(3)
–36
50
–60
90
–110
200
—
mA
mA
V
Output LOW Current
V
OH
OL
Output HIGH Voltage
CC = Min.
I
I
I
OH = –0.1mA
OH = –3mA
OH = –8mA
V
CC–
0.2
—
IN = VIH or VIL
2.4
3.0
3.0
—
V
V
V
CC = 3.0V
IN = VIH or VIL
CC = Min.
2.4(5)
—
V
Output LOW Voltage
I
I
I
I
OL = 0.1mA
OL = 16mA
OL = 24mA
OL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
V
VIN = VIH or VIL
0.55
0.50
V
V
V
CC = 3.0V
IN = VIH or VIL
I
OS
Short Circuit Current(4)
Input Hysteresis
CC = Max., V
O
= GND(3)
—
–60
—
–
135
150
0.1
–240
—
mA
mV
VH
I
I
I
CCL
CCH
CCZ
Quiescent Power Supply Current
V
V
CC = Max.,
IN = GND or VCC
—
10
µA
3096 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
8.10
3
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VCC = Max.
VIN = VCC –0.6V(3)
Min.
Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply
—
2.0
100
µA
ICCD
IC
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
VCC = Max., Outputs Open VIN = VCC
—
60
100
µA/
MHz
xOEAB or xOEBA = GND
One Input Toggling
50% Duty Cycle
VIN = GND
VCC = Max., Outputs Open VIN = VCC
—
—
0.6
0.6
1.0
1.1
mA
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
One Bit Toggling
fi = 5MHz
VIN = GND
VIN = VCC –0.6V
VIN = GND
50% Duty Cycle
VCC = Max., Outputs Open VIN = VCC
—
—
3.0
3.0
5.0(5)
5.9(5)
fCP= 10MHz (xCLKAB)
50% Duty Cycle
VIN = GND
xOEAB = xCEAB = GND
xOEBA = VCC
Sixteen Bits Toggling
fi = 2.5MHz
VIN = VCC –0.6V
VIN = GND
50% Duty Cycle
3096 tbl 07
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
8.10
4
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
FCT163952B FCT163952C
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(5)
FCT163952A
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH Propagation Delay
tPHL xCLKAB, xCLKBA to xBx, xAx RL = 500Ω
tPZH Output Enable Time
tPZL xOEBA, xOEAB to xAx, xBx
tPHZ Output Disable Time
tPLZ xOEBA, xOEAB to xAx, xBx
CL = 50pF
2.0
1.5
1.5
2.5
2.0
3.0
10.0
2.0
7.5
2.0
6.3
ns
10.5
10.0
—
1.5
1.5
2.5
1.5
3.0
8.0
7.5
—
1.5
1.5
2.5
1.5
3.0
7.0
6.5
—
ns
ns
ns
ns
ns
tSU
tH
Set-up Time HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
Hold Time HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
Set-up Time HIGH or LOW
xCEAB, xCEBA to xCLKAB,
xCLKBA
—
—
—
tSU
—
—
—
tH
Hold Time HIGH or LOW
xCEAB, xCEBA to xCLKAB,
xCLKBA
2.0
—
2.0
—
2.0
—
ns
ns
tW
Pulse Width HIGH or LOW
xCLKAB or xCLKBA(4)
3.0
—
—
3.0
—
—
3.0
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
ns
NOTES:
3096 tbl 08
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5. PropagationDelaysandEnable/DisabletimesarewithVCC =3.3V±0.3V, NormalRange. ForVCC =2.7Vto3.6V, ExtendedRange, allPropagationDelays
and Enable/Disable times should be degraded by 20%.
8.10
5
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
6V
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
←
V
CC
6V
Open
GND
500Ω
500Ω
GND
V
OUT
V IN
Pulse
Generator
Open
D.U.T.
3096 lnk 09
DEFINITIONS:
50pF
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
R
T
C
L
3096 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
PRESET
3096 drw 07
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
3096 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPLH
0.3V
0.3V
VOL
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
3096 drw 08
0V
3096 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
8.10
6
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
Device Type
Temp. Range
Drive
Package
PV
PA
PF
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
952A
952B
952C
Non-Inverting 16-Bit Registered Transceiver
16-Bit 3.3Volt
163
74
-40°C to +85°C
3096 drw 10
8.10
7
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