IDT74FCT16543ATPA8 [IDT]
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74FCT16543ATPA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 |
| 文件： | 总7页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
16-BIT LATCHED
TRANSCEIVER
IDT74FCT16543AT/CT/ET
DESCRIPTION:
FEATURES:
The FCT16543T16-bitlatchedtransceivers are builtusingadvanced
• 0.5 MICRON CMOS Technology
dualmetalCMOStechnology.These high-speed,low-powerdevices are
organized as two independent 8-bit D-type latched transceivers with
separateinputandoutputcontroltopermitindependentcontrolofdataflow
ineitherdirection.Forexample,the A-to-BEnable (xCEAB)mustbe low
inordertoenterdatafromtheAportortooutputdatafromtheBport. xLEAB
controlsthelatchfunction.WhenxLEABislow,thelatchesaretransparent.
Asubsequentlow-to-hightransitionofxLEAB signalputs the Alatches in
the storage mode.xOEAB performs outputenable functiononthe Bport.
Data flowfromthe Bporttothe Aportis similarbutrequires usingxCEBA,
xLEBA, and xOEBA inputs. Flow-through organization of signal pins
simplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise
margin.
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• VCC = 5V ±10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP, TSSOP, and TVSOP packages
The FCT16543T is ideally suited for driving high-capacitance loads
and low-impedance backplanes. The output buffers are designed with
poweroffdisable capabilitytoallow"live insertion"ofboards whenused
as backplane drivers.
FUNCTIONALBLOCKDIAGRAM
56
29
2OEBA
1OEBA
31
54
2CEBA
1CEBA
30
55
2LEBA
1LEBA
1
28
2OEAB
1OEAB
26
3
2CEAB
1CEAB
27
2
2LEAB
1LEAB
C
C
15
5
2A1
1A1
42
52
2B1
D
1B1
D
C
D
C
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JULY 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5444/4
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
(2)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
1OEAB
1LEAB
1OEBA
1LEBA
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
3
1CEAB
GND
1CEBA
GND
4
NOTES:
5
1A1
1B1
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
6
1A2
1B2
VCC
7
VCC
8
1A3
1A4
1B3
1B4
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1A5
1B5
GND
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz)
1A6
1A7
1A8
2A1
2A2
1B6
1B7
1B8
2B1
2B2
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
2A3
2B3
GND
GND
2A4
2A5
2B4
2B5
FUNCTIONTABLE(1, 2)
2A6
2B6
ForA-to-B(SymmetricwithB-to-A)
Latch
Output
Buffers
VCC
VCC
Inputs
Status
xAx to xBx
Storing
2A7
2B7
xCEAB xLEAB xOEAB
xBx
Z
H
X
L
X
H
L
X
X
L
2A8
2B8
Storing
X
GND
GND
Transparent
Current A Inputs
2CEAB
2LEAB
2OEAB
2CEBA
2LEBA
2OEBA
L
L
L
H
L
H
L
H
H
Storing
Transparent
Storing
Previous* A Inputs
Z
Z
NOTES:
1. * Before xLEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
SSOP/ TSSOP/ TVSOP
TOP VIEW
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA
and xOEBA.
PINDESCRIPTION
Pin Names
Description
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-BEnable Input(Active LOW)
B-to-AEnable Input(Active LOW)
A-to-BLatchEnableInput(ActiveLOW)
B-to-ALatchEnableInput(ActiveLOW)
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
xBx
2
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Test Conditions(1)
GuaranteedLogicHIGHLevel
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input HIGH Level
VIL
InputLOWLevel
GuaranteedLogicLOWLevel
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
—
—
0.8
±1
V
IIH
InputHIGHCurrent(Inputpins)(5)
Input HIGH Current (I/O pins)(5)
InputLOWCurrent(Inputpins)(5)
InputLOWCurrent(I/Opins)(5)
HighImpedanceOutputCurrent
(3-StateOutputpins)(5)
VI = VCC
—
µA
—
±1
IIL
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µ A
—
±1
ClampDiodeVoltage
VCC = Min., IIN = –18mA
–0.7
–140
100
5
–1.2
–250
—
V
(3)
IOS
ShortCircuitCurrent
VCC = Max., VO = GND
mA
mV
µ A
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
QuiescentPowerSupplyCurrent
VCC = Max
500
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
OutputDriveCurrent
OutputHIGHVoltage
Test Conditions(1)
(3)
Min.
–50
2.5
2.4
2
Typ.(2) Max.
Unit
mA
V
IO
VCC = Max., VO = 2.5V
—
3.5
3.5
3
–180
—
VOH
VCC = Min.
IOH = –3mA
IOH = –15mA
VIN = VIH or VIL
—
V
(4)
IOH =–32mA
IOL = 64mA
—
V
VOL
OutputLOWVoltage
VCC = Min.
—
0.2
0.55
V
VIN = VIH or VIL
IOFF
Input/OutputPowerOffLeakage(5)
VCC = 0V, VIN = or VO ≤ 4.5V
—
—
±1
μA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
3
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply
CurrentTTLInputs HIGH
VCC = Max.
VIN = 3.4V
—
0.5
1.5
mA
(3)
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
xCEAB and xOEAB = GND
xCEBA = VCC
VIN = VCC
VIN = GND
—
60
100
µ A /
MHz
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max., Outputs Open
fi = 10MHz
VIN = VCC
VIN = GND
—
—
—
—
0.6
0.9
2.4
6.4
1.5
2.3
mA
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND
xCEBA = VCC
VIN = 3.4V
VIN = GND
OneBitToggling
VCC = Max., Outputs Open
fi = 2.5MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB = GND
VIN = VCC
VIN = GND
4.5(5)
16.5(5)
VIN = 3.4V
VIN = GND
xCEBA = VCC
Sixteen BitsToggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
74FCT16543AT
74FCT16543CT 74FCT16543ET
Min.(2) Max. Min.(2)
Max. Unit
Symbol
tPLH
Parameter
Condition(2)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
PropagationDelay
1.5
6.5
1.5
5.1
1.5
3.4
ns
tPHL
TransparentMode
xAx to xBx or xBx to xAx
PropagationDelay
tPLH
tPHL
tPHZ
tPLZ
1.5
1.5
8
9
1.5
1.5
5.6
7.8
1.5
1.5
3.7
4.8
ns
ns
xLEBA to xAx, xLEAB to xBx
OutputEnableTime
xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
OutputDisableTime
tPZH
tPZL
1.5
7.5
1.5
6.5
1.5
4
ns
xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
xLEAB or xLEBA Pulse Width LOW
tSU
tH
2
2
—
—
2
2
—
—
1
1
—
—
ns
ns
(4)
tW
4
—
4
—
3
—
ns
ns
(3)
tSK(o)
OutputSkew
—
0.5
—
0.5
—
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VCC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
Pulse Width
tH
CLOCK ENABLE
ETC.
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16543AT/CT/ET
FASTCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XXX
XX
Temp. Range
Family
Package
Device Type
PV
PVG
PA
PAG
PF
PFG
Shrink Small Outline Package
SSOP - Green
Thin Shrink Small Outline Package
TSSOP - Green
Thin Very Small Outline Package
TVSOP - Green
16-Bit Latched Transceiver
543AT
543CT
543ET
16
74
Double-Density, 5 Volt, High Drive
– 40°C to +85°C
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
logichelp@idt.com
www.idt.com
7
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