IDT74FCT16841AT [IDT]
FAST CMOS 20-BIT TRANSPARENT LATCHES; FAST CMOS 20位透明锁存器
| 型号： | IDT74FCT16841AT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 20-BIT TRANSPARENT LATCHES |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT16841AT/BT/CT/ET
IDT54/74FCT162841AT/BT/CT/ET
FAST CMOS 20-BIT
TRANSPARENT
LATCHES
Integrated Device Technology, Inc.
DESCRIPTION:
FEATURES:
The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/
ET 20-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
andbusdrivers.TheOutputEnableandLatchEnablecontrols
are organized to operate each device as two 10-bit latches or
one 20-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16841AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162841AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimalundershoot,andcontrolledoutputfalltimes–reducing
the need for external series terminating resistors. The
FCT162841AT/BT/CT/ET are plug-in replacements for the
FCT16841AT/BT/CT/ET and ABT16841 for on-board inter-
face applications.
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16841AT/BT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162841AT/BT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
FUNCTIONAL BLOCK DIAGRAM
2OE
2LE
1OE
1LE
1D1
2D1
D
C
D
1Q1
2Q1
C
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
2556 drw 02
2556 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1996
1996 Integrated Device Technology, Inc.
5.18
DSC-2556/7
1
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
1OE
1Q1
1OE
1Q1
2
2
1Q2
GND
1Q3
3
1Q2
GND
1Q3
3
4
4
5
5
1Q4
6
1Q4
6
VCC
1Q5
7
VCC
1Q5
7
8
8
1Q6
9
1Q6
1Q7
9
1D6
1D7
1Q7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
GND
1Q8
GND
GND
1D8
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
1D8
1D9
1D10
2D1
1Q9
1D9
1D10
2D1
2D2
1Q10
SO56-1
SO56-2
SO56-3
E56-1
2Q1
2Q2
2D2
2D3
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
2D3
GND
2D4
2D5
2D6
GND
2D4
2D5
2D6
VCC
2D7
VCC
2D7
2D8
2Q7
2Q8
2D8
GND
2Q9
GND
2D9
GND
2D9
GND
2Q9
2Q10
2OE
2D10
2LE
2Q10
2OE
2D10
2LE
2556 drw 03
2556 drw 04
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.18
2
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
PIN DESCRIPTION
Pin Names
Description
Inputs
xLE
Outputs
xQx
xDx
Data Inputs
xDx
H
x
OE
L
xLE
xOE
xQx
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
H
H
L
H
L
Q(2)
L
L
X
L
2556 tbl 01
X
X
H
Z
NOTES:
2556 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before xLE HIGH-to-LOW Transition.
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
Max.
Unit
Symbol
Parameter(1)
Input
Capacitance
Output
Conditions
IN = 0V
Typ. Max. Unit
(2) Terminal Voltage with Respect to
VTERM
–0.5 to +7.0
V
CIN
V
3.5
6.0
pF
GND
(3) Terminal Voltage with Respect to
GND
VTERM
–0.5 to
VCC +0.5
V
COUT
VOUT = 0V
3.5
8.0
pF
Capacitance
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
2556 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
–60 to +120 mA
2556 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.18
3
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
–80
—
—
—
—
—
0.8
±1
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VCC = Max.
VI = VCC
—
µA
—
±1
II L
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
100
5
–1.2
–225
—
V
IOS
VH
Short Circuit Current
mA
mV
µA
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
2556 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16841T
Symbol
Parameter
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min. Typ.(2) Max.
Unit
IO
Output Drive Current
–50
2.5
2.4
—
3.5
3.5
–180
—
mA
VOH
Output HIGH Voltage
VCC = Min.
IOH = –3mA
V
V
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(4)
IOL = 48mA MIL.
—
2.0
—
3.0
0.2
—
—
0.55
±1
V
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 64mA COM'L.
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2556 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162841T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
I
I
ODL
Output LOW Current
V
CC = 5V, VIN = VIH or VIL,
CC = 5V, VIN = VIH or VIL,
V
OUT = 1.5V(3)
60
–60
2.4
115
200
mA
V
OUT = 1.5V(3)
ODH
Output HIGH Current
Output HIGH Voltage
V
–115 –200
mA
V
V
OH
OL
V
V
V
V
CC = Min.
I
OH = –16mA MIL.
OH = –24mA COM'L.
OL = 16mA MIL.
3.3
0.3
—
IN = VIH or VIL
CC = Min.
IN = VIH or VIL
I
I
I
V
Output LOW Voltage
—
0.55
V
OL = 24mA COM'L.
2556 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.18
4
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
xOE = GND
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fi =10MHz
VIN = VCC
VIN = GND
—
—
0.6
0.9
1.5
2.3
mA
50% Duty Cycle
xOE = GND
xLE = VCC
VIN = 3.4V
VIN = GND
One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
3.0
8.0
5.5(5)
50% Duty Cycle
xOE = GND
VIN = 3.4V
VIN = GND
20.5(5)
xLE = VCC
Twenty Bits Toggling
2556 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.18
5
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841AT/162841AT
FCT16841BT/162841BT
Com'l. Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
xDx to xQx
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 5pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0(4)
—
9.0
1.5
10.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0(4)
—
6.5
1.5
7.5
ns
(LE = HIGH)
13.0
12.0
16.0
11.5
23.0
7.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
3.0
5.0
—
15.0
13.0
20.0
13.0
25.0
9.0
13.0
8.0
15.5
8.0
14.0
6.0
7.0
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0(4)
—
15.0
10.5
18.0
8.5
15.0
6.5
7.5
—
tPLH
tPHL
Propagation Delay
xLE to xQx
ns
ns
ns
tPZH
tPZL
Output Enable Time
xOE to xQx
tPHZ
tPLZ
Output Disable Time
xOE to xQx
8.0
10.0
—
tSU
tH
Set-Up Time HIGH or LOW,
xDx to xLE
—
ns
ns
ns
Hold Time HIGH or LOW,
xDx to xLE
—
—
—
—
tW
xLE Pulse Width HIGH
—
—
—
—
tSK(o) Output skew(3)
0.5
0.5
0.5
0.5
ns
2556 tbl 09
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5.18
6
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841CT/162841CT
FCT16841ET/162841ET
Com'l. Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
xDx to xQx
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(5)
RL = 500Ω
CL = 5pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0(4)
—
5.5
1.5
6.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.0
3.0(4)
—
3.4
—
—
ns
(LE = HIGH)
13.0
6.4
15.0
6.5
12.0
5.7
6.0
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0(4)
—
15.0
6.8
16.0
7.3
13.0
6.0
6.3
—
7.5
3.7
7.5
4.4
9.0
3.6
3.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tPLH
tPHL
Propagation Delay
xLE to xQx
ns
ns
ns
tPZH
tPZL
Output Enable Time
xOE to xQx
tPHZ
tPLZ
Output Disable Time
xOE to xQx
tSU
tH
Set-Up Time HIGH or LOW,
xDx to xLE
ns
ns
ns
Hold Time HIGH or LOW,
xDx to xLE
—
—
—
tW
xLE Pulse Width HIGH
—
—
—
tSK(o) Output skew(3)
0.5
0.5
0.5
ns
2556 tbl 10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5.18
7
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
Open Drain
Disable Low
7.0V
Closed
500Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
2556 lnk 11
D.U.T.
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
50pF
RT = Termination resistance: should be equal to ZOUT of the Pulse
500Ω
T
R
Generator.
C
L
2556 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
2556 drw 07
3V
1.5V
0V
CLEAR
tSU
t
H
CLOCK ENABLE
ETC.
2556 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
2556 drw 09
2556 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.18
8
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
X
Temp. Range
Package
Device Type
Process
Blank
B
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
PV
PA
PF
E
16841AT Non-Inverting 20-Bit Transparent Latch
16841BT
16841CT
16841ET
162841AT
162841BT
162841CT
162841ET
54
74
–55°C to +125°C
–40°C to +85°C
2556 drw 10
5.18
9
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